/* $XConsortium: regmach8.h,v 1.1 94/03/28 21:13:12 dpw Exp $ */ /* REGMACH8.H * * Written by Jake Richter * Copyright (c) 1989, 1990 Panacea Inc., Londonderry, NH - All Rights Reserved * * This code may be freely incorporated in any program without royalty, as * long as the copyright notice stays intact. * * Additions by Kevin E. Martin (martin@cs.unc.edu) * * KEVIN E. MARTIN, RICKARD E. FAITH, SCOTT LAIRD, AND TIAGO GONS DISCLAIM * ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL * KEVIN E. MARTIN, RICKARD E. FAITH, SCOTT LAIRD, OR TIAGO GONS BE LIABLE * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF * CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * Modified for the Mach-8 by Rickard E. Faith (faith@cs.unc.edu) * Further modifications by Scott Laird (lair@kimbark.uchicago.edu) * and Tiago Gons (tiago@comosjn.hobby.nl) */ #ifndef _REGMACH8_H_ #define _REGMACH8_H_ #ifndef _MACH8_ASM_ #include "compiler.h" #include "Xos.h" /* mach-8 registers */ #define CLOCK_SEL 0x4aee #define CONFIG_STATUS_1 0x12ee #define CRT_OFFSET_HI 0x2eee #define CRT_OFFSET_LO 0x2aee #define CRT_PITCH 0x26ee #define DP_CONFIG 0xceee #define EXT_FIFO_STATUS 0x9aee #define GE_OFFSET_HI 0x72ee #define GE_OFFSET_LO 0x6eee #define GE_PITCH 0x76ee #define LINEDRAW_INDEX 0x9aee #define LINEDRAW_OPT 0xa2ee #define LINEDRAW 0xfeee #define ROM_ADDR_1 0x52ee #define SHADOW_CTL 0x46ee #define SHADOW_SET 0x5aee /* mach-32 specific registers */ #define READ_SRC_X 0xdaee /* VESA Approved 8514 Register Definitions */ #define DAC_MASK 0x02ea #define DAC_R_INDEX 0x02eb #define DAC_W_INDEX 0x02ec #define DAC_DATA 0x02ed #define DISP_STAT 0x02e8 #define H_TOTAL 0x02e8 #define H_DISP 0x06e8 #define H_SYNC_STRT 0x0ae8 #define H_SYNC_WID 0x0ee8 #define V_TOTAL 0x12e8 #define V_DISP 0x16e8 #define V_SYNC_STRT 0x1ae8 #define V_SYNC_WID 0x1ee8 #define DISP_CNTL 0x22e8 #define ADVFUNC_CNTL 0x4ae8 #define SUBSYS_STAT 0x42e8 #define SUBSYS_CNTL 0x42e8 #define ROM_PAGE_SEL 0x46e8 #define CUR_Y 0x82e8 #define CUR_X 0x86e8 #define DESTY_AXSTP 0x8ae8 #define DESTX_DIASTP 0x8ee8 #define ERR_TERM 0x92e8 #define MAJ_AXIS_PCNT 0x96e8 #define GP_STAT 0x9ae8 #define CMD 0x9ae8 #define SHORT_STROKE 0x9ee8 #define BKGD_COLOR 0xa2e8 #define FRGD_COLOR 0xa6e8 #define WRT_MASK 0xaae8 #define RD_MASK 0xaee8 #define COLOR_CMP 0xb2e8 #define BKGD_MIX 0xb6e8 #define FRGD_MIX 0xbae8 #define MULTIFUNC_CNTL 0xbee8 #define MIN_AXIS_PCNT 0x0000 #define SCISSORS_T 0x1000 #define SCISSORS_L 0x2000 #define SCISSORS_B 0x3000 #define SCISSORS_R 0x4000 #define MEM_CNTL 0x5000 #define PATTERN_L 0x8000 #define PATTERN_H 0x9000 #define PIX_CNTL 0xa000 #define PIX_TRANS 0xe2e8 /* Composite sync bit in clock select register. */ #define COMPOSITE_SYNC 0x1000 /* Display Status Bit Fields */ #define HORTOG 0x0004 #define VBLANK 0x0002 #define SENSE 0x0001 /* Horizontal Sync Width Bit Field */ #define HSYNCPOL_NEG 0x0020 #define HSYNCPOL_POS 0x0000 /* Vertical Sync Width Bit Field */ #define VSYNCPOL_NEG 0x0020 #define VSYNCPOL_POS 0x0000 /* Display Control Bit Field */ #define DISPEN_NC 0x0000 #define DISPEN_DISAB 0x0040 #define DISPEN_ENAB 0x0020 #define INTERLACE 0x0010 #define DBLSCAN 0x0008 #define MEMCFG_2 0x0000 #define MEMCFG_4 0x0002 #define MEMCFG_6 0x0004 #define MEMCFG_8 0x0006 #define ODDBNKENAB 0x0001 /* Subsystem Status Register */ #define _8PLANE 0x0080 #define MONITORID_8503 0x0050 #define MONITORID_8507 0x0010 #define MONITORID_8512 0x0060 #define MONITORID_8513 0x0060 #define MONITORID_8514 0x0020 #define MONITORID_NONE 0x0070 #define MONITORID_MASK 0x0070 #define GPIDLE 0x0008 #define INVALIDIO 0x0004 #define PICKFLAG 0x0002 #define VBLNKFLG 0x0001 /* Subsystem Control Register */ #define GPCTRL_NC 0x0000 #define GPCTRL_ENAB 0x4000 #define GPCTRL_RESET 0x8000 #define CHPTEST_NC 0x0000 #define CHPTEST_NORMAL 0x1000 #define CHPTEST_ENAB 0x2000 #define IGPIDLE 0x0800 #define IINVALIDIO 0x0400 #define IPICKFLAG 0x0200 #define IVBLNKFLG 0x0100 #define RGPIDLE 0x0008 #define RINVALIDIO 0x0004 #define RPICKFLAG 0x0002 #define RVBLNKFLG 0x0001 /* Current X, Y & Dest X, Y Mask */ #define COORD_MASK 0x07ff /* Advanced Function Control Register */ #define CLOKSEL 0x0004 #define DISABPASSTHRU 0x0001 /* Graphics Processor Status Register */ #define GPBUSY 0x0200 #define DATARDY 0x0100 /* Command Register */ #define CMD_NOP 0x0000 #define CMD_LINE 0x2000 #define CMD_RECT 0x4000 #define CMD_RECTV1 0x6000 #define CMD_RECTV2 0x8000 #define CMD_LINEAF 0xa000 #define CMD_BITBLT 0xc000 #define CMD_OP_MSK 0xf000 #define BYTSEQ 0x1000 #define _16BIT 0x0200 #define PCDATA 0x0100 #define INC_Y 0x0080 #define YMAJAXIS 0x0040 #define INC_X 0x0020 #define DRAW 0x0010 #define LINETYPE 0x0008 #define LASTPIX 0x0004 #define PLANAR 0x0002 #define WRTDATA 0x0001 /* Short Stroke Vector Transfer Register (The angular Defs also apply to the Command Register */ #define VECDIR_000 0x0000 #define VECDIR_045 0x0020 #define VECDIR_090 0x0040 #define VECDIR_135 0x0060 #define VECDIR_180 0x0080 #define VECDIR_225 0x00a0 #define VECDIR_270 0x00c0 #define VECDIR_315 0x00e0 #define SSVDRAW 0x0010 /* Background Mix Register */ #define BSS_BKGDCOL 0x0000 #define BSS_FRGDCOL 0x0020 #define BSS_PCDATA 0x0040 #define BSS_BITBLT 0x0060 /* Foreground Mix Register */ #define FSS_BKGDCOL 0x0000 #define FSS_FRGDCOL 0x0020 #define FSS_PCDATA 0x0040 #define FSS_BITBLT 0x0060 /* The Mixes */ #define MIX_MASK 0x001f #define MIX_NOT_DST 0x0000 #define MIX_0 0x0001 #define MIX_1 0x0002 #define MIX_DST 0x0003 #define MIX_NOT_SRC 0x0004 #define MIX_XOR 0x0005 #define MIX_XNOR 0x0006 #define MIX_SRC 0x0007 #define MIX_NAND 0x0008 #define MIX_NOT_SRC_OR_DST 0x0009 #define MIX_SRC_OR_NOT_DST 0x000a #define MIX_OR 0x000b #define MIX_AND 0x000c #define MIX_SRC_AND_NOT_DST 0x000d #define MIX_NOT_SRC_AND_DST 0x000e #define MIX_NOR 0x000f #define MIX_MIN 0x0010 #define MIX_DST_MINUS_SRC 0x0011 #define MIX_SRC_MINUS_DST 0x0012 #define MIX_PLUS 0x0013 #define MIX_MAX 0x0014 #define MIX_HALF__DST_MINUS_SRC 0x0015 #define MIX_HALF__SRC_MINUS_DST 0x0016 #define MIX_AVERAGE 0x0017 #define MIX_DST_MINUS_SRC_SAT 0x0018 #define MIX_SRC_MINUS_DST_SAT 0x001a #define MIX_HALF__DST_MINUS_SRC_SAT 0x001c #define MIX_HALF__SRC_MINUS_DST_SAT 0x001e #define MIX_AVERAGE_SAT 0x001f /* Memory Control Register */ #define BUFSWP 0x0010 #define VRTCFG_2 0x0000 #define VRTCFG_4 0x0004 #define VRTCFG_6 0x0008 #define VRTCFG_8 0x000C #define HORCFG_4 0x0000 #define HORCFG_5 0x0001 #define HORCFG_8 0x0002 #define HORCFG_10 0x0003 /* Pixel Control Register */ #define MIXSEL_FRGDMIX 0x0000 #define MIXSEL_PATT 0x0040 #define MIXSEL_EXPPC 0x0080 #define MIXSEL_EXPBLT 0x00c0 #define COLCMPOP_F 0x0000 #define COLCMPOP_T 0x0008 #define COLCMPOP_GE 0x0010 #define COLCMPOP_LT 0x0018 #define COLCMPOP_NE 0x0020 #define COLCMPOP_EQ 0x0028 #define COLCMPOP_LE 0x0030 #define COLCMPOP_GT 0x0038 #define PLANEMODE 0x0004 typedef struct { unsigned char r, g, b; } LUTENTRY; struct mach8vmodedef { unsigned short ht,hss,hsw,hd; unsigned short vt,vss,vsw,vd; unsigned short dc,clk; /* dc = DISP_CNTL */ }; /* Wait until "v" queue entries are free */ #define WaitQueue(v) { while (inw(EXT_FIFO_STATUS) & (0x10000 >> (v))); } /* Wait until GP is idle and queue is empty */ #define WaitIdleEmpty() { while (inw(GP_STAT) & (GPBUSY | 1)); } /* * This version is for use in mach8Probe() to prevent a server hang if * there is no 8514/A-style chip present */ #define ProbeWaitIdleEmpty() { int i; \ for (i = 0; i < 100000; i++) \ if (!(inw(GP_STAT) & (GPBUSY | 1))) \ break; \ } /* Wait until GP has data available */ #define WaitDataReady() { while (!(inw(GP_STAT) & DATARDY)); } #define MODE_640 0 #define MODE_1024 1 #define MODE_800 2 #define MODE_CUSTOM 4 #define MACH8_MAX_X 2047 #define MACH8_MAX_Y 2047 #ifndef NULL #define NULL 0 #endif #else /*_MACH8_ASM_ */ /* * Defines used in assembly language files. * Separated to avoid macro expansion problems. */ #define EXT_FIFO_STATUS CONST(0x9aee) #define PIX_TRANS CONST(0xe2e8) #define GP_STAT CONST(0x9ae8) #define FRGD_MIX CONST(0xbae8) #define BKGD_MIX CONST(0xb6e8) #define BKGD_COLOR CONST(0xa2e8) #define FRGD_COLOR CONST(0xa6e8) #define WRT_MASK CONST(0xaae8) #define CUR_X CONST(0x86e8) #define CUR_Y CONST(0x82e8) #define MAJ_AXIS_PCNT CONST(0x96e8) #define MULTIFUNC_CNTL CONST(0xbee8) #define CMD CONST(0x9ae8) #define GP_IDLE_EMPTY CONST(0x0201) #define FSS_PCDATA CONST(0x0040) #define FSS_FRGDCOL CONST(0x0020) #define BSS_BKGDCOL CONST(0x0000) #define SCISSORS_L CONST(0x2000) #define SCISSORS_R CONST(0x4000) #define GP_WRITE_CMD CONST(0x53b1) #define GP_READ_CMD CONST(0x53b0) #define GP_STIP_CMD CONST(0x43f3) #define GP_DEF_FRGD_MIX CONST(0x0027) #define GP_DEF_BKGD_MIX CONST(0x0007) #define GP_DEF_PIXCNTL CONST(0xa000) #define MACH8_MAX_X CONST(2047) #define DATARDY CONST(0x0100) #define MIX_DST CONST(0x0003) #define PIXCNTL_STIP CONST(0xa080) #endif #endif /* _REGMACH8_H_ */