Don't use the `Clocks' command. The clocks are fixed
(i.e. not probed), and
there should be no variation between cards (other than the maximum supported
clock for each chipset).
The following options are of particular interest to the Cirrus driver. Each
of them must be specified in the `svga' driver section of the
XF86Config
file, within the Screen subsections of the depths to which they are
applicable (you can enable options for all depths by specifying them in the
Device section).
This option will disable the use of any accelerated functions. This is likely to help with some problems related to DRAM timing, high dot clocks, and bugs in accelerated functions, at the cost of performance (which will still be reasonable on VLB).
The "fast_dram" option will cause the driver to set the
internal
memory clock (MCLK) register of the video card to a higher value.
Normally, this register is not touched but it appears that the
standard CL-GD542x BIOS initializes it to a value that is somewhat
on the low side (limited by the chip specification), which has a
negative influence on performance of high dot clock modes. This
is especially true if extended RAS timing is being used (this is
indicated in the server probe).
The actual speed of DRAM is not a critical factor in the determining
whether this option is appropriate; one card with 80ns DRAM using
Extended RAS timing, which came with a DOS driver utility to set the
MCLK to this value (0x22), seems to run stable at higher MCLK.
There are also (mainly brand name) cards whose customized BIOS does initialize to a higher non-standard value. In this case, the use of this option is probably not appropriate.
The "slow_dram"
option will set the MCLK to the value used by the
standard CL-GD542x BIOS (0x1c). Symptoms of a MCLK that is too high
can be vertical bands of flickering pixels on the screen, erroneous
pixels appearing in text, and loosing pixels in the textmode font
after running X (note that very similar effects can be caused by an
MCLK setting that is too low).
Upon start-up, the driver will report the value of the MCLK register (check this first), and also any changes that are made.
Typical MCLK values:
This is usually the BIOS default.
It is forced by the "slow_dram" option.
Value used by the "med_dram" option.
Highest value that
542x based cards seem to be able to handle with linear
addressing enabled.
Value that most (Extended RAS) 542x cards seem to be able to
handle, used by the "fast_dram" option.
The official maximum of the 542x chips is 50 MHz. The official spec. for the 5434 is also 50 MHz (0x1c) and that for the 5429 and 5430 is probably 60 MHz (0x22). Current revisions of the 5434 (E and greater) support 60 MHz MCLK in graphics modes, and the driver will program this automatically. If it causes problems, use the "slow_dram" option.
The driver takes the MCLK into account for clock limits that are determined by DRAM bandwidth.
If you are not having any problems (performance or stability at
high dot clocks), it is best not to use the "fast_dram"
option.
This option, when used with a 5426/28/29/3x, will have the effect of disabling the use of the BitBLT engine (which the 5424 does not have), while retaining some acceleration. This will be useful for problems related to functions that use the BitBLT engine.
This option, when used with a 5426/28/29/3x, will have the effect of disabling the use of BitBLT functions that go from system memory to video memory. This is useful for problems relating to image write, such as a little white line at the top left corner of the screen, or a skewed image after a console switch back to the server, which have been observed on some configurations, especially VLB 5426 and 5434 with a fast CPU. Note that this option results in reduced performance.
Force detection of the given chipset. Useful if you have a supported chipset that is not properly detected, or if you have an unsupported chip that might be compatible with a supported one.
This option will override the detected amount of video memory, and pretend the given amount of memory is present on the card. This is useful on cards with 2Mbyte of memory whose DRAM configuration is not compatible with the way the driver enables the upper megabyte of memory, or if the memory detection goes wrong. It must be specified in the Device section.
This option will set the CRT FIFO threshold to a conservative value for high dot clocks (>= 65 MHz), reducing performance but hopefully alleviating problems with `streaks' on the screen (especially when a BitBLT operation is in progress).
This option will set the CRT FIFO threshold to an aggressive value; it will be the same as that used for lower dot clocks. It improves performance at high dot clocks.
This option will cause the driver not to set the `DRAM bank select' bit to enable the upper megabyte of memory on a 2Mbyte card. This should be helpful with cards equipped with 512Kx8 DRAMs, as opposed to 256Kx4/16 DRAMs, when using a virtual screen configuration that uses more than 1Mbyte of memory.
This option will force probing of dot clocks on the card. This
should not be necessary, since the clocks are fixed and the same for
all Cirrus chipsets. However, they do depend on the motherboard
supplying a proper standard 14.31818 MHz frequency on the bus. There
may be ill-designed VLB motherboards that do not supply this
frequency correctly for certain bus speeds (e.g. scaled up from 33
MHz). If in doubt, use this option and run `X -probeonly'.
If the
clocks are very different from the correct clocks shown below, you
can try a Clocks line in the XF86Config
with your deviating clocks.
In this situation, the MCLK is probably also screwed.
Correct clocks:
25.2 28.3 41.1 36.1 31.5 40.0 45.1 49.9 65.0 72.2 75.0 80.0 85.2
This enables programmable clocks. It must be specified in the Device section. With this option, the clocks the modes use will be automatically selected. Do not specify any Clocks line. This option makes a 12.5 MHz clock possible for a 320x200 Doublescan mode. Note that some frequencies may be unstable. Only tried and tested frequencies (like the default clocks) are guaranteed to be stable.
This enables linear addressing, which is the mapping of the entire framebuffer to a high address beyond system memory, so that SVGA bank switching is not necessary. It enhances performance at 256 colors, and is currently required for 16bpp and 32bpp. See section 4 for details.
This sets the physical memory base address of the linear framebuffer. It must be specified in the Device section. It is required for most linear addressing configurations.
This option will, when the BitBLT engine is enabled, favour its use over framebuffer color expansion functions that are normally faster. This can give a performance improvement on a heavily CPU-loaded system (e.g. running gcc and other programs at the same time) in certain situations.
This enables the use of memory-mapped I/O to talk to the BitBLT engine on the 543x/5429, which is a bit faster. It also enables additional acceleration using memory-mapped I/O.
This disables use of the hardware cursor provided by the chip. Try this if the cursor seems to have problems. In particular, use this when using dot clocks greater than 85 MHz on the 5434 since the chip doesn't fully support the hardware cursor at those clocks.
Provides a work-around for problems on the LCD screen of some 62x5 laptop chipsets with maximum white colors.
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