ࡱ; >=  !"#$%&'()*+,-./0123456789:;<@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Root Entry F[臃ݹ CompObjbWordDocument1ObjectPoolݹݹ  !#$%&'()*+,- FMicrosoft Word 6.0 Document MSWordDocWord.Document.6; L\" {ࡱ;   FMicrosoft Word 6.0 Picture MSWordDocWord.Picture.6ࡱ;ࡱ;  Oh+'0 ܥe3 et!1r~l~ll~l~t~t~t~D~~~~~~ ~J1(>>>>BBBɀˀˀˀ),{TσbJt~B<=>BBBJBl~l~>BBBBl~>t~>ɀ~~6l~l~l~l~BɀBBA 0.6um BiCMOS Processor with Dynamic Execution Robert P. Colwell, Randy L. Steck A next generation, Intel Architecture compatible microprocessor with dynamic execution has been implemented with a 0.6um 4 layer metal BiCMOS process [1]. Performance is achieved through the use of a large, full-speed cache accessed through a dedicated bus interface feeding a generalized dynamic execution microengine. A primary 64-bit processor bus includes additional pipelining features to provide high throughput to this CPU and cache. These and other techniques result in a projected performance of greater than 200 Ispec92. Testability features built into the design allow complete access to all structures without the overhead of a full LSSD implementation. Included in this paper are a microarchitecture block diagram, implementation details and a die photo. This processor implements dynamic execution using an out-of-order, speculative execution engine, with register renaming of integer [2], floating point and flags variables, multiprocessing bus support, and carefully controlled memory access reordering. The flow of Intel Architecture instructions is predicted and these instructions are decoded into micro-operations (uops), or series of uops, and these uops are register-renamed, placed into an out-of-order speculative pool of pending operations, executed in dataflow order (when operands are ready), and retired to permanent machine state in source program order. This is accomplished with one general mechanism to handle unexpected asynchronous events such as mispredicted branches, instruction faults and traps, and external interrupts. Dynamic execution, or the combination of branch prediction, speculation and micro-dataflow, is the key to the high performance. The basic operation of the microarchitecture ( Figure 1) is as follows: The 512 entry Branch Target Buffer (BTB) helps the Instruction Fetch Unit (IFU) choose an instruction cache line for the next instruction fetch. ICache line fetches are pipelined with a new instruction line fetch commencing on every CPU clock cycle. Three parallel decoders (ID) convert multiple Intel Architecture instructions into multiple sets of micro-ops (uops) each clock. The sources and destinations of these uops are renamed by the Register Alias Table (RAT), which eliminates register re-use artifacts, and are forwarded to the Reservation Station (RS) and to the ReOrder Buffer (ROB). The renamed uops are queued in the RS where they wait for their source data - this can come from several places, including immediates, data bypassed from just-executed uops, data present in a ROB entry, and data residing in architectural registers (such as EAX). The queued uops are dynamically executed according to their true data dependencies and execution unit availability (IEU, FEU, AGU). The order in which any given uops execute in time has no particular relationship to the order implied by the source program. Memory operations are dispatched from the RS to the Address Generation Unit (AGU) and to the Memory Ordering Buffer (MOB). The MOB ensures that the proper memory access ordering rules are observed. Once a uop has executed, and its destination data has been produced, that result data is forwarded to subsequent uops that need it, and the uop becomes a candidate for retirement. Retirement hardware in the ROB uses uop timestamps to reimpose the original program order on the uops as their results are committed to permanent architectural machine state in the Retirement Register File (RRF). This retirement process must observe not only the original program order, it must correctly handle interrupts and faults, and flush all or part of its state on detection of a mispredicted branch. When a uop is retired, the ROB writes that uops result into the appropriate RRF entry and notifies the RAT of that retirement so that subsequent register renaming can be activated. The component includes separate data and instruction L1 caches (each of which is 8KB), and a unified L2 cache. The L1 Data Cache is dual-ported, non-blocking, supporting one load and one store per cycle. The L2 cache interface runs at the full CPU clock speed, and can transfer 64 bits per cycle. The external bus is also 64-bits and can sustain a data transfer every bus-cycle. This external bus operates at 1/2, 1/3, or 1/4 of the CPU clock speed. Clock distribution was carefully designed to minimize skew across the entire die by generating a master clock with a PLL which has been delay synchronized to output signals. Global clocks distributed to 80 different units across the die are then buffered for the specific load in each clock sub-branch. Tuning of these drivers, and careful routing of the global clocks, results in a worst-case global clock skew of 250 pS. BiCMOS circuits were used extensively thoughout the design, providing lower delay for higher loads, and increasing overall performance by approximately 15%. Figure 2 shows the relative delay to a comparable CMOS inverter and Figure 3 shows the most common implementation of a BiCMOS gate. A Vdd of 2.9v was selected as an optimal point for CMOS and BiCMOS gate performance while reducing overall power. Delayed precharge domino logic, shown in Figure 4, was also used for speed-critical paths, particularly in the instruction decode logic, and resulted in lower power than standard domino logic during transitions with fewer race conditions on outputs. Test structures were defined allowing full access to all processor logic while requiring only 4% of the full die area and incurring no speed penalty. This is accomplished through the use of test registers, mode bits to provide specific logic access, and the use of serial Scanout (scan chains). Scanout in particular provides observability of virtually all important signals within the design with no speed impact, and it is used extensively in test and debug. On-chip BIST is implemented to complement the Scanout observability. The processor is a fully static design accommodating IDDQ testing. Features for lower power operation, (such as StopClock and standby mechanisms) and features intended to improve system management and RAS (Reliability, Availability, Serviceability) are included. An extensive Machine Check Architecture has been incorporated, with facilities to detect errors in hardware and allow those errors to be handled in software. Acknowledgements We are fortunate to represent the work of many talented, dedicated professionals and it is mainly their efforts that are presented here. References [1] Schutz, J., A 3.3V 0.6um BiCMOS SuperScalar Microprocessor, ISSCC Proceedings, pp. 202-203, 1994 [2] Hennessy, J. et al, Computer Architecture A Quantitative Approach, Morgan Kaufman Publishers Inc., 1990  Figure 1 - Basic CPU Block Diagram  EMBED Word.Picture.6   EMBED Word.Picture.6  Figure 2 - BiCMOS vs CMOS relative inverter delay Figure 4 - Delayed Precharge Domino Copyright(R) 1994 Institute of Electrical and Electronics Engineers. Reprinted from ISSCC Proceedings, February 1995. This material is posted here with permission of the IEEE. Such permission of the iEEE does not in any way imply IEEE endorsement of any of Intel's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by sending a blank email message to info.pub.permission@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.         U:P-4|-Y] *K&s H & &$TNPPMicrosoft PowerPoint & TNPPf & &TNPP s  W145&'t 0&dal-- a-dd--' & &]--\]---' & &--h---' & &|U\]--\|-U,U--' & &zrZz--Zz-r*r--' & &gEM--g-EEG--' & &g--g ---' & &{s--sh{ -[--' & &x)--) -mx{x--' & &/--/S -t--' & &(---P!+--' & &--W-H--' & &--:-H--' & &|\"--\z|-,--' & &|\--[\|-,--' & &g-- g ---' & &V--V?- --' & &e--:e---' & &g--Wg-6--' & &]GO--]-GG"--' & &bV^--b-VV,--' & &e--Ge-2--' & &e(1--e-'*0--' & &j~--&j-~~<--' & &Y--(Y-!--' & &|\--\V|-,--' & &--R-Z--' & &H--=H---' & &N$l--lN|-z8--' & &8@c--c-88--' & &5M-- wq-%U--'- $E: $6: & &'ti"Arial-.  2 a External Bus5(,,-5-( & &R^g-vjU--g^RU"ArialU-.   2 MOBC>5 & &Ujv--mU--vjUU"ArialoS-.   2 /IEU69 & &Rg--jU--gRU"Arial-.   2 gMIUC: & &R[g--*sjU--g[RU"ArialoS-.   2 AGU5?9 & &Rg--0jU--gRU"ArialU-.   2 FEU15: & &Rg0--IjU--0gRU"ArialoS-.   2 )ROB:>5"ArialU-.   2 2 &6"ArialoS-.   2 RRF::0 & &w--U--wU"ArialU-.   2 0CBTB516 & &7v--OU--v7U"ArialoS-. "ArialU-.   2 pmBIU@E"ArialoS-.  & &\--tU--\U"ArialU-. "ArialU-.   2 +{IFU1: & &0--IU--0U"ArialoS-. "ArialU-. "ArialoS-. "ArialU-. "ArialoS-.   2 ^I"ArialU-. "ArialoS-.   2 iLD:"ArialU-. "ArialoS-. "ArialU-.  & &M--fU--MU"ArialU-.   2 JMISC5 & &z0--IU--0zU"ArialoS-.   2 ARAT:51 & &X*--CpU--*XU"ArialU-. "ArialU-. "ArialU-. "ArialU-. "ArialU-. "ArialU-. "ArialU-.   2 R:"ArialU-. "ArialU-.   2 iS5"ArialU-. "ArialU-. "ArialU-. "ArialU-. "ArialU-. "ArialU-.  & &\;--TtU--;\U"ArialoS-.   2 L2,- & &Y-- "System-KY---' & &Rge-~j--egR"ArialU-.   2 DCU::9 & &* l"ArialU-.  2 Y"ArialU-.  *2 BIU: Bus Interface Unit595-(-,-(,:-"ArialU-.  2 Y"ArialU-.  K2 -IFU: Instruction Fetch Unit (includes ICache)1:,(,(-,0-(-:,,(-,-(:,(-,"ArialU-.  2 OY"ArialU-.  -2 OBTB: Branch Target Buffer5165-,(-1,,-6,-"ArialU-.  2 Y"ArialU-.  *2 ID: Instruction Decoder:,(-(,-:,(-,,"ArialU-.  2 Y"ArialU-.  62 MIS: Microinstruction SequencerC5B(,,(-(,-5-,-,-(,"ArialU-.  2 oY"ArialU-.  -2 oRAT: Register Alias Table:51:-,(-5-(1-,,"ArialU-.  2 Y"ArialU-.  $2 ROB: ReOrder Buffer:>5:,>,-5--"ArialU-.  2 /Y"ArialU-.  32 /RRF: Retirement Register File::0:,,C,-:-,(-1,"ArialU-.  2 Y"ArialU-.  *2 RS: Reservation Station:59-(,(,-,5-,-"ArialU-.  2 Y"ArialU-.  02 IEU: Integer Execution Unit69-,-,5(-(,-,9-"ArialU-.  2 OY"ArialU-.  :2 O"FEU: Floating point Execution Unit15:1-,-,-,-5(-(,-,9-"ArialU-.  2 Y"ArialU-.  12 AGU: Address Generation Unit5?95-,,((>,-,,-,9-"ArialU-.  2 Y"ArialU-.  .2 MIU: Memory Interface UnitC:C,C,(--,(-:,"ArialU-.  2 oY"ArialU-.  @2 o&DCU: Data Cache Unit (includes DCache)::9:,-:,(-,:--(,-,(::,(-,"ArialU-.  2 Y"ArialU-.  .2 MOB: Memory ReOrder BufferC>5B-B-(:,>,-5--"ArialU-.  2 /Y"ArialU-.  "2 /L2: Level 2 Cache ,--,(-,9-(,- & &"C]l--- $UT"C"d & &"]-- $U"" & &"]0-- $U""( & & ^[-- $So ^  & & [-- $S   & &-- $ & &? z-- $?rr & &3\-- $D3T & &um-- $u~m & &sk&sk-- $s|k & &Xl-- $}XlX &  & &s@&s?-- $s'7 & &X@-- $(XX8 &  & &s&s-- $s & &X-- $XX &  & &pCm&pCl-- $pTCd & &UDm-- $UUDUe &  & &q-- $q & &T4]-- $ET4TU & &s-- $s & &X-- $XX & &-- $ & & -- $ & &#^-- $V## & &%`!-- $X %% & &!-- $  & &Tu}-- $duuT & &S|-- $c_846492135  FݹݹPIC LMETA ?hCompObjb\" %G /&WordMicrosoft Word  k D-Times New Roman[- -O---\----y----- %s|------#---Q--- $?----$ ;;<2=2----"}----#W@----- %---FF--i---$ 99;1<1---;---"U?----"---- $>---t--tt ---- %---9---- %tdd---- $8b8t----y----$ 9::PP9:9:9----$ "9"8899999---JJ-&  `---%II0 0THTHj---- $HZf6f-- & -Y@w@--- $@Rq.q----- %99,,---7x--- x--& -Yb\b--iblb--yb|b--bb--bb--bb--bb--bb--bb--bb--bb-- bb--b b--,b0b--=b@b--MbPb--]bab--nbqb--~bb--bb--bb--bb--kn--{--------------------"--.2-->B--OR--_c--ps------------------------------xu--he--XT--GD--73--'#----------------------sp--c`--YY --YY--YY--YY--YY--YY--YY--YY--YY--Y}Yz--YmYi--Y\YY--YLYI--Y<Y9--Y,Y(--YY--Y Y--YY--YY--YY--YY--YY--YY--YY--YY--YxYu--YhYe- & &} u-``--``--``--``-- ``--` `---`1`-->`A`--N`R`--^`b`--n`r`--``--``--``--``--``--``--``--``--``--``--"`%`--2`5`--B`F`--S`V`--c`g`--s`w`--``--``--``--``--be--rv----------------------%)--59--FI--VZ--gj--wz----------------------{x--kh--[W--KG--:7--*'---- ------------------ws--fc--VR--EB--52--%"------------------------yu--he--XU--HD--74--'$----------------------tq--d`- & &-ee--ee--ee--$e'e--4e8e--EeHe--UeYe--eeie--ueye--ee--ee--ee--ee--ee--ee--ee--ee-- e e--ee--)e,e--9e=e--JeMe--Ze]e--jene--{e~e--ee--ee--ee--ee--jm--z~------------------ -- ---1--=A--NQ--^a--nr------------------------|y--lh--[X--KG--;7--+'---- ------------------wt--gc--WS--FC--62--%"----------------------vs--fc--VR--FB--52--%!----------------------ro- & &-Yd\d--idld--yd|d--dd--dd--dd--dd--dd--dd--dd--dd-- dd--d d--,d0d--=d@d--MdPd--]dad--ndqd--~dd--dd--dd--dd--mp--}-------------------- #--03--@D--QT--ad--qt------------------------------xt--gd--WT--GC--73--&#----------------------sp--c_--YY --YY--YY--YY--YY--YY--YY--YY--YY--Y~Yz--YmYj--Y]YZ--YMYJ--Y=Y9--Y,Y)--YY--Y Y--YY--YY--YY--YY--YY--YY--YY--YY--YyYv--YiYf- & "Arial-2 kClock* 'l"Arial-/2 lkBuffer with skewed delay!$ $ '&nbC-2 CkVcc!'C-2 Ckkeeper' & & k hB-2 BkVcc!'B-2 Bkkeeper' & &C  uV-2 kComplex$* ')-2 kgate' & ~Ar-2 Krka--'~6A-2 Kkb--'~A>-2 K>kc--'a$b- 2 .bka'~&A-2 Kkb--'~A4-2 K4kc--']-2 ]kd--'"&-2 ke--'--/--K"ArialK-,2 kFigure 3 - BiCMOS Gate333 ..<<EA7A..'-- $\w\- --ZRZ--P--z--zz----P--.PP-->.--.P--- $D& - -->P-->PP----- $jk- -`"Arial-2 kD20%'R-2 kD10%'3~- 2 @~kB0'U~- 2 b~kA0'a-2 nkOut#4)%'- \$$- - zz- - - - - ~- - - - %\- - - $x$- - - - ZZ- - - 1 ~- - - - y%- - - RZR- - R- - ZZR- - - $<qqW<- - - - $99Ls- - - \$$- - $x$- - 6- - ;- - ;xx- - >;>- - !S!- - - - - - ;- - @;@- - %- - %- - ;oo- - ;- - ;- - - $56Y- %56Y-  - - - $ <<%%Y- % <<%%Y-  - - YY- - - $ ..<<..%.%.Y- % ..<<..%.%.Y-  - - - -&H ࡱ; >ObjInfo ObjectPoolݹݹWordDocument |hSummaryInformation(ܥe3 e |ho`j`jj`j`````````` ``g1aaaaa^e^e^e^e`e`e`eefggTRh*g`^e-.aP^e^e^eg^ej`j`aa^e^e^e^ej``a`a^e``j`j`j`j`^e^e^e^e a Out# A B e-- d-- b-- c-- D2 D1 c-- b-- a-- Figure 3 - BiCMOS Gate Clock Buffer with skewed delay Vcc keeper Vcc keeper Complex gate ]s[ 2/(|$a20(20(&20(060&\# 2/(x%0.0&% \50R.#9- 88~~484888,D/:A" 010&P$ 2/(n%0-0&% 040&j& P20F*#?; 8> >|~B8B8:\30R$#9- 88~~484888,000&P$ 2/(x^$2/(t^$0/0&P$ 20((20((2/(X^$0/&&GF @/6f6'W+Vd/Z#2 |14841166|1|155|0,0&2! 0/&! 0/&" 0+0&2! 0*0&x(  0)0&(  0(0&:& @!06 p0/&p8 0'0&X2! 0/&!~ 0/&t"54 0/&" D/:!    0&0&P$ 0$0&B$ 2/(j^$0%0&P$ 2/(n^$./$|x!5( d/Z f  M2M51 1ReSe11CC0/&! 0/&2! 0/&N  0/&  2/(  I !H/> 8  @00& 00&P 00&a` 00&!  00& 00&p 00&P0A@ 00&0A@ 00&0!!   @ 06==0 0&0!!   0 0&P` 0 0&`!  H 0>  A./$8 00&8 00& 00& .0$XIX 00&8 0"0&8./$ 00& 00& 00& .0$XEIX 00& 0#0&00&a` 00& 00& H 0>   @D/:=;}] \|\./$G!2* @/6w9! ]d/Z  f |1212115e7e|1|144|./$!4( ./$!4* D/:7!$ ##0/&"~} ./$[!4( ./$!6( @/6A6! ]@/6F" ]./$L"3* d/Z#g |1212116f7f|1|144|/6%gB>g  ==|}1;1;f6^V+U@z@/6=(V U'U/IJc& &' &N &u & & & & &9 &` & & & & &# &K &r & & & & &5 &H  &;H  &cH &H &H &H &H &&H &MH  &tH  &H  &H  &H  &H  &7H  &^H  &H &H &H &H &"H &IH &pH &H  &H  &H  & H &G& & & & & &\ &5 &  & & & &q &J &# & & & & &_ &8 & & &  &  &  &a  &:  &  &  &  & &w &P &) & & & &  &e  &>  &  &  &  &  &{  &T &- & 7fz/pCC#o& &' &N &u & & & & &9 &` & & & & &$ &K &r & & & & &6 &] & & & & &! &H &o & &  &, &S &z & & & & &=  &d  &  &  &  &  &'  &N  &v & & & & &9 &`  &  & &z &S &, & & & & &h &A & & & & &} &V &/ & & & & &k &D & & & & & &Y &2 &  &  &\  &5  &  &  &  &  &r &K &$ & & & &  &`  &9  &  &  &  &  &v  &O &( & /#ek& &' &O &v & & & & &9 &a & & & & &$ &K &s & & & & &6 &] & & & & &! &H & c &4c &[c &c &c &c &c  &c  &Ec  &lc  &c  &c  &c  &c  &0c &Wc &~c &c &c &c &c &Ac  &hc  &c  &C & & & & & &X &1 &  & & & &n &F & & & & & &\ &5 &  & & & &q &J &# &&&s  &L  &% & & & & &b &:  &  &  &  &  &w  &P  &)  & & & & &f &? & ~^6/Jc& &' &N &u & & & & &9 &` & & & & &# &K &r & & & & &5 &H &<H &cH &H &H &H  &H  &&H  &MH  &tH  &H  &H  &H  &H &8H &_H &H &H &H &H  &"H  &IH  &pH  &H  &H  &H  & H&E& & & & & &[ &3 &  & & & &p &I &! & & & & &^ &7 & &  &  &  &  &_  &8  & & & & &u &N &' &  &  &  &  &c  &<  &  &  & & &y &R &+ & 7f2/(]k2/(fYv/l- ((hv/la4 ((v/le%((v./$l% ࡱ; nor~   SYu ]abc U]ab U]abc ]abc uDa oqrwxz{}~   bZ-    K@Normala "A@"Default Paragraph Font #'+05:RYsx    SY-  ./  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklm MEuEw'Gy M  A q  A q  1 u  7 i +[5e%U%U+[Iw5e%m#S/]_Q(8H_WWW9XX%Y@HP LaserJet 4/4MLPT1:HPPCL5EHP LaserJet 4/4M D.XHP LaserJet 4/4M D.X 1Times New Roman Symbol &Arial"h{{e!* Betsy Atler Betsy Atlerࡱ; > $ H l   DhC:\WINWORD\TEMPLATE\NORMAL.DOT Betsy Atler Betsy Atler@ܹ@@ܹ@Microsoft Word 6.02L' ࡱ;   FMicrosoft Word 6.0 Picture MSWordDocWord.Picture.6ࡱ;ࡱ;  Oh+'0 tS & & G4-- $G,z z & & 3A-- $9+  & &-- $ & &0k-- $c00 & &-- $ & &-- $ & &\7-- $\\/ & &f-- $vf & &f-- $vf & &]-- $]]  & & H -- $ @@ & &]-- $]] &  & &TNPP & ---+Fࡱ; >_854363821 F.ݹ.ݹPIC LMETA  (CompObj@2T8@@2T8b'1 | &WordMicrosoft Word  8 D-Times New Roman- --: ----:---   -- &%0 -tW"ArialO-2 i8 Fanout83333'Ae"Arial- 2 8 1*'A- 2 8 2*'A)- 2 )8 3*'A- 2 8 4*'AM- 2 M8 5*'A;- 2 8 6*'Ao- 2 o8 7*'A_- 2 8 8*'A- 2 8 9*'A-2 8 10**'& d 7wx-2 8 1.1**'w-2 8 1.0**' w-2 8 0.9**'+w-2 8 0.8**'Kw-2 8 0.7**' & 6F-2 F8 CMOSBMH='y0-2 08 RelativeB33.3'D&- 2 8 '<_-2 N_8 DelayB33.'- !Ng-|a"Arial-2 m 8 1 CMOS stage *0-'  # '- !Ngm-Nam-2 mm 8 2 CMOS stages *0-'  # ' 9"Arial-2 9 8 Vcc = 2.7v7..0...'-- $- --- $- --- $- --- $- --- $- --- $- --- $- --- $XX\- --- $XX\- --- $- --- $- --- $- --- $- --- $- --- $- --- $- --- $- --- $- --- $- --- $--2- --- $--2- --- $88=- --- $88=- --- $- --- $- --- $<<7- --- $- --- $dd]- --- $- --- $}- --- $ - --- $- --- $773- --- $- --- $&&  - --=--- ./ - --=--!=!--D-T#-2 f#8 BiCMOS=BMH="ArialNe-'-  - -ࡱ; >ObjInfoObjectPool.ݹ.ݹWordDocument SummaryInformation(ܥe3 e Dpppp - 1 ^ T *-  - ppphpppp CMOS Fanout 1 2 3 4 5 6 7 8 9 10 1.1 1.0 0.9 0.8 0.7 BiCMOS Relative Delay 1 CMOS stage 2 CMOS stages Vcc = 2.7v 0"0& 2/( 10/&^<$-  0/&<-  0/&7"I00/&P H' 02/( %I2/($2/(v$2/($2/(7$2/($2/($2/(I$2/($2/( $2/(. $E/Lv (u(u(bu(u( u0*2!0(, 2/(J 2/(2/( r0/&2/(-0/&C2/(C2/(iD/:   D/:!  D/:$   D/:  @/6  @/6"  D/:   @06O  @06"O  @06  @06"  @06@06"@06~   @06"~   @06!  @ 06"!  @ 06  @ 06"  @ 06  @ 06"  @067#  @06"7#  @06C$@06$  @06$  @06b$  @06$@06$  @06j$  @06$  @06+$@06 $  @06$  D0:"F2 E%E100&6{z 00&%"|!000&6N {z 00&6"{z 0 0&G3vu ࡱ; CDRu U]ab U]abc ]^abc ]abc ]abc uDa DIJQRTUWXZ[]^`acdfgijlmpquvz{ 2JFvvvvv.-j K @ Normal ]a c"A@"Default Paragraph Font #&)-27<AFNX[bp     !"#$%&'()*+,-./0123456789:;<=>?@ABAq3e-_'Gy ? o    [ # c ' g ' g 'g'g'g'g'g ;k@HP LaserJet 4/4MLPT1:HPPCL5EHP LaserJet 4/4M D.XHP LaserJet 4/4M D.XD 1Times New Roman Symbol &Arial"V h{{e!* Betsy Atler Betsy Atlerࡱ; > $ H l   DhC:\WINWORD\TEMPLATE\NORMAL.DOT Betsy Atler Betsy Atler@e,ܹ@@(Pܹ@F#Microsoft Word 6.02 Oh+'0 D h   @d C:\WINWORD\TEMPLATE\NORMAL.DOT;A Compatible 0.6um BiCMOS Processor with Dynamic Execution Susan Hunt SusaSummaryInformation("6<@6<n Hunt@Mݹ@@Mݹ@F#Microsoft Word 6.020RST^_$:gq!r!s!t!wºֳ̩̜uU]cuD2UcKuD2]avK uDwUcuDqt2UcKuDqt2]avKUc uDUcUuD!]^c]V]c]cU]c]cU]cU]c &0RSTU 5 / W ^#a]%!$$    P" h< 4h." h( 4h.xx`` ``hx!))*F r!s!t!$v$[$ {$$$$$xxA1%--H1%xPxK@Normal]a "A@"Default Paragraph FontTtt!!!!T tw<!t!=>t::tMD6 USERC:\WORK\ISSCC\ISSCC95N.DOCMD6 USERC:\WORK\ISSCC\ISSCC95N.DOCMD6 USERC:\WORK\ISSCC\ISSCC95N.DOCMD6 USERC:\WORK\ISSCC\ISSCC95N.DOCMD6 USERC:\WORK\ISSCC\ISSCC95N.DOC Betsy AtlerH:\BALTER\PROCS\P6\ISSCC95.DOC Betsy Atler!H:\BALTER\PROCS\P6\CIS\P6TECH.DOC Betsy Atler!H:\BATLER\PROCS\P6\CIS\P6TECH.DOC Betsy Atler!H:\BATLER\PROCS\P6\CIS\P6TECH.DOC Susan HuntL:\P6\P6TECH.DOC@HP LaserJet 4 Plus/4M PlusLPT1:HPPCL5EHP LaserJet 4 Plus/4M Plus  D$۝@6X$HP LaserJet 4 Plus/4M Plus  D$۝@6X$D1Times New Roman Symbol &Arial"hxx$b:A Compatible 0.6um BiCMOS Processor with Dynamic Execution Susan Hunt Susan Huntࡱ; >