;
;        DMA  Channel 0-3  Registers
;
dma0_addr          equ       000h       ; for write -- base and current address
                                        ; for read  -- current address
dma0_count         equ       001h       ; for write -- base and current W count
                                        ; for read  -- current word count
dma1_addr          equ       002h       ; for write -- base and current address
                                        ; for read  -- current address
dma1_count         equ       003h       ; for write -- base and current W count
                                        ; for read  -- current address
dma2_addr          equ       004h       ; for write -- base and current address
                                        ; for read  -- current address
dma2_count         equ       005h       ; for write -- base and current W count
                                        ; for read  -- current word count
dma3_addr          equ       006h       ; for write -- base and current address
                                        ; for read  -- current address
dma3_count         equ       007h       ; for write -- base and current W count
                                        ; for read  -- current W count
dma03_status       equ       008h       ; read only
                                        ; bit 0 = 1 channel 0 has reached TC
                                        ; bit 1 = 1 channel 1 has reached TC
                                        ; bit 2 = 1 channel 2 has reached TC
                                        ; bit 3 = 1 channel 3 has reached TC
                                        ; bit 4 = 1 channel 0 request
                                        ; bit 5 = 1 channel 1 request
                                        ; bit 6 = 1 channel 2 request
                                        ; bit 7 = 1 channel 3 request
dma03_command      equ       08h        ; write only, for channel 0-3
                                        ; bit 0 = memory-to memory enable+
                                        ; bit 1 = channel 0 address hold enable+
                                        ; bit 2 = controller enable-
                                        ; bit 3 = normal-/compressed+ timing
                                        ; bit 4 = fixed-/rotating+ priority
                                        ; bit 5 = late-/extended+ write selection
                                        ; bit 6 = DREQ active low+/high-
                                        ; bit 7 = DACK active low-/high+
dma03_smask        equ       00ah       ; single mask reg, write only
                                        ; bit 1,0 --> for select channel mask bit
                                        ;     00  --> select channel 0
                                        ;     01  --> select channel 1
                                        ;     10  --> select channel 2
                                        ;     11  --> select channel 3
                                        ; bit 2 = 0 clear mask bit
                                        ;       = 1 set mask bit
dma03_mode         equ       00bh       ; mode register, write only
                                        ; bit 0,1 = channel select
                                        ;         = 00 select channel 0
                                        ;         = 01 select channel 1
                                        ;         = 10 select channel 2
                                        ;         = 11 select channel 3
                                        ; bit 2,3 = 00 verify transfer
                                        ;         = 01 write transfer
                                        ;         = 10 read transfer
                                        ;         = 11 reserved
                                        ; bit 4-7 = reserved = 0
dma03_clear        equ       00ch       ; clear byte pointer, write only
dma03_reset        equ       00dh       ; same as hardware reset, write only
dma03_clrmsk       equ       00eh       ; clears the mask bits of channel 0-3
                                        ; enabling them to accept dma requests
dma03_amask        equ       00fh       ; mask reg, write only
                                        ; bit 0 = 0 clear channel 0 mask bit
                                        ;       = 1 set channel 0 mask bit
                                        ; bit 1 = 0 clear channel 1 mask bit
                                        ;       = 1 set channel 1 mask bit
                                        ; bit 2 = 0 clear channel 2 mask bit
                                        ;       = 1 set channel 2 mask bit
                                        ; bit 3 = 0 clear channel 3 mask bit
                                        ;       = 1 set channel 3 mask bit
                                        ; bit 4-7 = don't care
                                        ; bit 0,1 --> for select channel mask bit
                                        ; bit 2 = 0 clear mask bit
                                        ;       = 1 set mask bit
;
;        PIC(8259) control port
;
pic1_port1         equ       020h       ; A0 set to 0
                                        ; for ocw2
                                        ; bit 0-2: L0, L1, L2 -- interrupt level
                                        ;          when bit 6 (SL) = 1
                                        ; bit 3,4 = 0, 0
                                        ; bit 5-7: R, SL, EOI -- for select each
                                        ; function (R, EOI) or combinations
                                        ; R: rotate, EOI: end of interrupt
                                        ; for ocw3
                                        ; bit 0-2: RIS, RR, P
                                        ; bit 3,4 = 0, 1
                                        ; bit 5,6: SMM, ESMM -- Special Mask Mode
                                        ; if ESMM = 1 and SMM = 1 enter S. M. M.
                                        ; if ESMM = 1 and SMM = 0 revert to Normal
                                        ; when ESMM = 0, SMM has no effect
                                        ; Enable Special Mask Mode
                                        ; if ESMM = 1 enable SMM = 1 or 0
                                        ; if ESMM = 0 SMM = x
pic1_port2         equ       021h       ; A0 set to 1
                                        ; sets and clears the mask bits in the
                                        ; IMR. bit 0-7: M0-M7 represent the 8
                                        ; mask bits
;
;        DEVICE and POINT DEVICES
;
device_offset      equ       022h       ;device drive far call offset
device_segment     equ       024h       ;device drive far call segment
pd_flag1           equ       026h       ;pointing device flag
                                        ;bit 7 -- command in progress
                                        ;bit 6 -- resend
                                        ;bit 5 -- ack
                                        ;bit 4 -- error
                                        ;bit 3 -- reserved, 0
                                        ;bit 2-0 -- index count
pd_flag2           equ       027h       ;pointing device flag
                                        ;bit 7 -- device drive far call flag
                                        ;bit 6-3 -- reserved
                                        ;bit 2-0 -- package size
                                        ; 1 - enable watch dog = timer count
;
;   Programmable Interval Timer
;
pit_ch0            equ       040h       ; port address of timer 0(16 bit)
pit_ch1		   equ	     041h	; port address of timer 1(16 bit)
pit_ch2            equ       042h       ; port address of timer 2(16 bit)
pit02_ctrl         equ       043h       ; control word register for timer 0, 1, 2, write only
                                        ; bit 0    = 0, count in binary
                                        ;            1, count in BCD
                                        ; bits 3-1 = mode number (00h - 05h)
                                        ; bits 5,4 = read/write
                                        ;      00  - counter latch command
                                        ;      01  - read/load low byte
                                        ;      10  - read/load high byte
                                        ;      11  - read/load low byte,then high byte
                                        ; bits 7,6 = counter select
                                        ;      00  - select timer 0
                                        ;      01  - select timer 1
                                        ;      10  - select timer 2
                                        ;      11  - read-back command(for read)
                                        ;  *   Read-back command format :
                                        ;  Bit
                                        ; ------------------------------------------
                                        ;   5   = 0  Latch count of selected counter(s)
                                        ;   4   = 0  Latch status of selected counter(s)
                                        ;   3   = 1  Select counter 2
                                        ;   2   = 1  Select counter 1
                                        ;   1   = 1  Select counter 0
                                        ;   0   reserved = 0
kb_port            equ       060h       ; input/output buffer for KB and AUX
cmd_status_8042    equ       064h       ; 8042 command port
                                        ; for write operation
                                        ;   bit 7 = reserved = 0
                                        ;   bit 6 = IBM translate mode
                                        ;   bit 5 = disable_/enable- AUX device
                                        ;   bit 4 = disable+/enable- KB
                                        ;   bit 3 = reserved = 0
                                        ;   bit 2 = system flag
                                        ;   bit 1 = enable AUX interrupt
                                        ;   bit 0 =
                                        ; for read operation
;
;	system control port
;
sysb_ctrl          equ       061h       ; system control port B
                                        ; for write operation
                                        ;   bit 0 = timer 2 gate
                                        ;   bit 1 = speaker data enable
                                        ;   bit 2 = -enable parity check
                                        ;   bit 3 = -enable channel check
                                        ;   bit 4 = reserved
                                        ;   bit 5 = reserved
                                        ;   bit 6 = reserved = 0
                                        ;   bit 7 = reserved
                                        ; for read operation
                                        ;   bit 0 = timer 2 gate
                                        ;   bit 1 = speaker data enable
                                        ;   bit 2 = -enable parity check
                                        ;   bit 3 = -enable channel check
                                        ;   bit 4 = toggle with each refresh request
                                        ;   bit 5 = timer 2 output
                                        ;   bit 6 = channel check
                                        ;   bit 7 = parity error
;status_c	   equ		85h	; read/write
					; same as port_c(328H)
;status_speed	   equ		86h	; bit 7-6	speed status
					;   1 1		smart
					;   0 1         Top speed
					;   0 0         none of above
					; bit 5		Weitek 3167 Math coprocessor
					; bit 4		for 1100/25/20C
					;		1 : 1100/25
					;		0 : 1100/20C
					;	        for MSAT/16/20
					;	        1 : MSAT/20
					;	        0 : MSAT/16
					; bit 3		for 1100/25/20C only
					;		1 : cache on
					;		0 : cache off
					; bit 2		0 : RAM BIOS good
					;		1 : RAM BIOS bad
					; bit 1		0 : RAM VIDEO good
					;		1 : RAM VIDEO bad
					; bit 0		0 : console exist
					;               1 : console unexist
;status_d	   equ         88h	; R/W
					; bit 7         0 : not in setup
					;		1 : in setup
					; bit 6         0 : non CONNER
					;		1 : CONNER WDD for 2nd WDD
					; bit 5         0 : non CONNER
					;		1 : CONNER WDD for 1st WDD
					; bit 4		0 : 1st WDD active
					;		1 : 2nd WDD active
					; bit 3         reserved
					; bit 2		0 : cache good
					;		1 : cache bad
					; bit 1         status bit 1 of port_D
					; bit 0         0 : jump F000:FFF0H
					;               1 : clod start
port_c		   equ	       328h	; write only
					; bit 7-5	speed parameter(valid when bit 2 = 1)
                                        ;   000         6 MHZ
                                        ;   001         8 MHZ
                                        ;   xxx         bigger value, more fast 
					; bit 4         1 : flush cache memory
					;               0 :  
					; bit 3		1 : enable cache system
					; 		0 : disable cache system
					; bit 2		speed select
					;		1 : enable speed change
					;		0 : disable speed change
					; bit 1		1 : enable RAM BIOS write 
					;		0 : disable RAM BIOS Write
					; bit 0		1 : enable RAM BIOS 
					;		0 : disable RAM BIOS
port_d		   equ	       329h	; write only
				 	; bit 1         fast gate A20
					;     		0 : off gate A20
					;   		1 : on gate A20
;
;     RT/CMOS control port
;
cmos_addr          equ        070h      ; cmos address register
                                        ;   address       function
                                        ; -----------   ------------
                                        ;     00h          Seconds
                                        ;     01h       Second Alarm
                                        ;     02h          Minutes
                                        ;     03h       Minute Alarm
                                        ;     04h           Hours
                                        ;     05h        Hour Alarm
                                        ;     06h        Day of Week
                                        ;     07h       Date of Month
                                        ;     08h           Month
                                        ;     09h           Year
                                        ;     0Ah     Status Register A
                                        ;     0Bh     Status Register B
                                        ;     0Ch     Status Register C
                                        ;     0Dh     Status Register D
cmos_data          equ        071h      ; cmos data register
;
; DMA Page Register
;
dma_ch0           equ        087h       ; dma channel 0
dma_ch1           equ        083h       ; dma channel 1, for diagnostic
dma_ch2           equ        081h       ; dma channel 2
dma_ch3           equ        082h       ; dma channel 3
dma_ch4           equ        08fh       ; dma channel 4, for refresh memory
dma_ch5           equ        08bh       ; dma channel 5
dma_ch6           equ        089h       ; dma channel 6
dma_ch7           equ        08ah       ; dma channel 7
;
pic2_port1         equ       0a0h       ; A0 set to 0
                                        ; for ocw2
                                        ; bit 0-2: L0, L1, L2 -- interrupt level
                                        ;          when bit 6 (SL) = 1
                                        ; bit 3,4 = 0, 0
                                        ; bit 5-7: R, SL, EOI -- for select each
                                        ; function (R, EOI) or combinations
                                        ; R: rotate, EOI: end of interrupt
                                        ; for ocw3
                                        ; bit 0-2: RIS, RR, P
                                        ; bit 3,4 = 0, 1
                                        ; bit 5,6: SMM, ESMM -- Special Mask Mode
                                        ; if ESMM = 1 and SMM = 1 enter S. M. M.
                                        ; if ESMM = 1 and SMM = 0 revert to Normal
                                        ; when ESMM = 0, SMM has no effect
                                        ; Enable Special Mask Mode
                                        ; if ESMM = 1 enable SMM = 1 or 0
                                        ; if ESMM = 0 SMM = x
pic2_port2         equ       0a1h       ; A0 set to 1
                                        ; sets and clears the mask bits in the
                                        ; IMR. bit 0-7: M0-M7 represent the 8
                                        ; mask bits
;
;        DMA  Channel 4-7  Registers
;
dma4_addr          equ       0c0h       ; for write -- base and current address
                                        ; for read  -- current address
dma4_count         equ       0c2h       ; for write -- base and current W count
                                        ; for read  -- current word count
dma5_addr          equ       0c4h       ; for write -- base and current address
                                        ; for read  -- current address
dma5_count         equ       0c6h       ; for write -- base and current W count
                                        ; for read  -- current address
dma6_addr          equ       0c8h       ; for write -- base and current address
                                        ; for read  -- current address
dma6_count         equ       0cah       ; for write -- base and current W count
                                        ; for read  -- current word count
dma7_addr          equ       0cch       ; for write -- base and current address
                                      ; for read  -- current address
dma7_count         equ       0ceh       ; for write -- base and current W count
                                        ; for read  -- current W count
dma47_status       equ       0d0h       ; read only
                                        ; bit 0 = 1 channel 4 has reached TC
                                        ; bit 1 = 1 channel 5 has reached TC
                                        ; bit 2 = 1 channel 6 has reached TC
                                        ; bit 3 = 1 channel 7 has reached TC
                                        ; bit 4 = 1 channel 4 request
                                        ; bit 5 = 1 channel 5 request
                                        ; bit 6 = 1 channel 6 request
                                        ; bit 7 = 1 channel 7 request
dma47_command      equ       0d0h       ; write only, for channel 4-7
                                        ; bit 0 = memory-to memory enable+
                                        ; bit 1 = channel 0 address hold enable+
                                        ; bit 2 = controller enable-
                                        ; bit 3 = normal-/compressed+ timing
                                        ; bit 4 = fixed-/rotating+ priority
                                        ; bit 5 = late-/extended+ write selection
                                        ; bit 6 = DREQ active low+/high-
                                        ; bit 7 = DACK active low-/high+
dma47_smask        equ       0d4h       ; single mask reg, write only
                                        ; bit 1,0 --> for select channel mask bit
                                        ;     00  --> select channel 4
                                        ;     01  --> select channel 5
                                        ;     10  --> select channel 6
                                        ;     11  --> select channel 7
                                        ; bit 2 = 0 clear mask bit
                                        ;       = 1 set mask bit
dma47_mode         equ       0d6h       ; mode register, write only
                                        ; bit 1,0 = channel select
                                        ;         = 00 select channel 4
                                        ;         = 01 select channel 5
                                        ;         = 10 select channel 6
                                        ;         = 11 select channel 7
                                        ; bit 3,2 = 00 verify transfer
                                        ;         = 01 write transfer
                                        ;         = 10 read transfer
                                        ;         = 11 reserved
                                        ; bit 7-4 = reserved = 0
dma47_clear        equ       0d8h       ; clear byte pointer, write only
dma47_reset        equ       0dah       ; same as hardware reset, write only
dma47_clrmsk       equ       0dch       ; clears the mask bits of channel 0-3
                                        ; enabling them to accept dma requests
dma47_amask        equ       0deh       ; mask reg, write only
                                        ; bit 0 = 0 clear channel 4 mask bit
                                        ;       = 1 set channel 4 mask bit
                                        ; bit 1 = 0 clear channel 5 mask bit
                                        ;       = 1 set channel 5 mask bit
                                        ; bit 2 = 0 clear channel 6 mask bit
                                        ;       = 1 set channel 6 mask bit
                                        ; bit 3 = 0 clear channel 7 mask bit
                                        ;       = 1 set channel 7 mask bit
                                        ; bit 4-7 = don't care
                                        ; bit 0,1 --> for select channel mask bit
                                        ; bit 2 = 0 clear mask bit
                                        ;       = 1 set mask bit
;
;        Math Coprocessor I/O port
;
math_0             equ       0f0h       ; clare math coprocessor '-busy'
math_1             equ       0f1h       ; reset math coprocessor
;
; hard disk port
;

;
; Game I/O port
;
game_io0           equ         200h
game_io1           equ         201h
game_io2           equ         202h
game_io3           equ         203h
game_io4           equ         204h
game_io5           equ         205h
game_io6           equ         206h
game_io7           equ         207h
;
;        Parallel Port
;
paral3_data        equ         278h     ; parallel port 3 data address
paral3_status      equ         279h     ; parallel port 3 status address
paral3_ctrl        equ         37ah     ; parallel port 3 conttol address
paral2_data        equ         378h     ; parallel port 2 data address
paral2_status      equ         379h     ; parallel port 2 status address
paral2_ctrl        equ         37ah     ; parallel port 2 control address
paral1_data        equ         3bch     ; parallel port 1 data address
paral1_status      equ         3bdh     ; parallel port 1 status address
paral1_ctrl        equ         3beh     ; parallel port 1 control address
;
;        Serial Port 1
;
                                        ; i/o addr.   register selected         DLAB state
                                        ; ---------   -----------------         ----------
                                        ; xf8h        TX buffer                 0 (write)
                                        ; xf8h        RX buffer                 0 (read)
                                        ; xf8h        divisor latch LSB         1
                                        ; xf9h        divisor latch MSB         1
                                        ; xf9h        interrupt enable reg      0
;
tx_buf2            equ         2f8h     ;transmitter holding register
                                        ;
int_ena2           equ         2f9h     ;interrupt enable register
                                        ;
int_iden2          equ         2fah     ;interrupt identification register
                                        ;
line_ctrl2         equ         2fbh     ;line control register
                                        ;
modem_ctrl2        equ         2fch     ;modem control register
                                        ;
line_status2       equ         2fdh     ;line status register
                                        ;
modem_status2      equ         2feh     ;modem status register
                                        ;bit 7 -- reserved
tx_buf1            equ         3f8h     ;transmitter holding register
                                        ;bit 0~7 -- data bit 0~7
int_ena1           equ         3f9h     ;interrupt enable register
                                        ;bit 7 - 4 -- reserved
                                        ;bit 3 -- receive modem status
                                        ;bit 2 -- receive line status
                                        ;bit 1 -- Tx holding register empty
                                        ;bit 0 -- receive data available
int_iden1          equ         3fah     ;interrupt identification register
                                        ;bit 7 - 3 = 0
                                        ;bit 1 - 2 -- interrupt id
                                        ;bit 0 = 0 -- interrupt pending
                                        ; id = 1 1 -- receive line status
                                        ;      1 0 -- receive data available
                                        ;      0 1 -- transmit holding empty
                                        ;      0 0 -- modem status
                                        ;
line_ctrl1         equ         3fbh     ;line control register
                                        ;bit 7 -- DLAB
                                        ;bit 6 -- set break
                                        ;bit 5 -- stick parity
                                        ;bit 4 -- even parity
                                        ;bit 3 -- parity enable
                                        ;bit 2 -- # of stop bit
                                       ;bit 1, 0 -- word length
modem_ctrl1        equ         3fch     ;modem control register
                                        ;bit 7 - 5 = 0
                                        ;bit 4 -- loop
                                        ;bit 3 -- out 2
                                        ;bit 2 -- out 1
                                        ;bit 1 -- RTS
                                        ;bit 0 -- DTR
line_status1       equ         3fdh     ;line status register
                                        ;bit 7 = 0
                                        ;bit 6 -- Tx shift register empty
                                        ;bit 5 -- Tx holding register empty
                                        ;bit 4 -- break interrupt
                                        ;bit 3 -- FE
                                        ;bit 2 -- PE
                                        ;bit 1 -- OE
                                        ;bit 0 -- data ready
modem_status1      equ         3feh     ;modem status register
                                        ;bit 7 -- data carrier
                                        ;bit 6 -- RI
                                        ;bit 5 -- DSR
                                        ;bit 4 -- CTS
                                        ;bit 3 -- delta data carrier
                                        ;bit 2 -- trailing edge RI
                                        ;bit 1 -- delta DSR

;
;	diagnostic port
;
diag_port1	  equ	      3bch	; for BIOS team
diag_port2	  equ	      378h	;	
diag_port3	  equ	      300h	; for debug board	
diag_port4	  equ	      080h	; for debug board
                                        ;bit 0 -- delta CTS
;
;        Disk Controller Ports
;
hd_ctrl		   equ	      3f6h	; fixed disk contrl register
					;  bit 7 - 3      reserved = 0
					;  bit 2          reset
					;  bit 1	  enable IREQ
					;  bit 0	  reserved = 0
hd_alt             equ        3f6h      ; fixed disk alternate status
					;   same as status register
hd_port0	   equ	      1f0h	; data register
hd_port1	   equ	      1f1h	; error reg./write precomp reg	
hd_port2	   equ	      1f2h	; sector count register
hd_port3	   equ	      1f3h	; sector number register
hd_port4	   equ	      1f4h	; cylinder low register
hd_port5	   equ	      1f5h	; cylinder high register
hd_port6	   equ	      1f6h	; device/head
hd_port7	   equ	      1f7h	; status reg./command register
					;  bit 7	  busy
					;  bit 6	  Ready
					;  bit 5	  write fault
					;  bit 4	  seek completed
					;  bit 3	  data request
					;  bit 2	  data corrected
					;  bit 1	  index
					;  bit 0	  error status
;
;      Diskette Controller Ports
;
dsk_sta_b          equ         3f1h     ; reserved
sdisk_outreg       equ         3f2h     ; digital output register
                                        ; bit 0 -- drive select = 0 -- drive A
                                        ;                       = 1 -- drive B
                                        ; bit 1 -- reserved
                                        ; bit 2 -- diskette function reset
                                        ; bit 3 -- enable diskette int. and dma
                                        ; bit 4 -- drive A motor enable
                                        ; bit 5 -- drive B motor enable
                                        ; bit 6 -- reserved
                                        ; bit 7 -- reserved
main_status        equ         3f4h     ; main status register
                                        ; bit 7 = RQM -- request to master
                                        ; bit 6 = DIO -- data input/output
                                        ;         = 1 -- data tranfer from FDC
                                        ;                data reg. to processor
                                        ;         = 0 -- in reverse order above
                                        ; bit 5 = NDM -- non-DMA mode
                                        ; bit 4 = CB  -- diskette controller
                                        ;                busy = 1 -- FDC busy
                                        ; bit 3 -- reserved
                                        ; bit 2 -- reserved
                                        ; bit 1 = DBB -- diskette drive B busy
                                        ;                =1 -- FDD busy
                                        ; bit 0 = DAB -- diskette drive a busy
                                        ;                =1 -- FDD busy
data_reg           equ         3f5h     ; FDC data register(read/write)
sdisk_inreg        equ         3f7h     ;digital input register
                                        ; for read
                                        ;   bit 7  --  diskette change
                                        ;              1  -  active
                                        ;              0  -  inactive
                                        ;   bit 6  --  write gate(for WDD)
                                        ;   bit 5  --  head select 3(for WDD)
                                        ;   bit 4  --  head select 2(for WDD)
                                        ;   bit 3  --  head select 1(for WDD)
                                        ;   bit 2  --  head select 0(for WDD)
                                        ;   bit 1  --  drive select 1(for WDD)
                                        ;   bit 0  --  drive select 0(for WDD)
                                        ; for write
                                        ;  bit 7-2  -  reserved
                                        ;  bit 1-0  -  select data rate
                                        ;      00   -  500K data rate
                                        ;      01   -  300 data rate
                                        ;      10   -  250K data rate
                                        ;    else   -  reserved

;
;
line_ctrl3         equ       3220h
line_ctrl4         equ       3228h
line_ctrl5         equ       4220h
line_ctrl6         equ       4228h
line_ctrl7         equ       5220h
line_ctrl8         equ       5228h
