












                           XT-8000E

                    Product Specification
                   and OEM Technical Manual























Document 1015226
Revision E
January 1990















       


























































                       REVISION RECORD


                               
      Revision      Date Published    Revised Contents



        A           October 1986      Preliminary Issue



        B           December 1986     General Changes



        C           June 1987         General Changes



        D           July 1988         General Changes
        D (Adden 1) July 1989         General Changes



        E           January 1990      General Changes




                  Document Number:  1015226

                           WARRANTY

Maxtor warrants  the XT-8000E  Family of  disk drives  against
defects in  materials and  workmanship for  a period of twelve
months, for  the original  purchaser.   Direct  any  questions
regarding the  warranty to  your Maxtor  Sales Representative.
Maxtor   maintains    Customer   Service   Centers   for   the
repair/reconditioning of  all Maxtor  products.    Direct  all
requests for repair to the Maxtor Service Center in your area.
This assures you of the fastest possible service.

                     REGULATORY APPROVALS

          UL Recognition obtained: File Number E87276
          CSA Certification obtained:   File Number LR54048
          VDE Recognition obtained:     Registration    Number
37230G
Address comments concerning this manual to:
Maxtor Corporation
Technical Publications
211 River Oaks Parkway
San Jose, California 95134-1913
Telephone:  (408) 432-1700
Telex:  171074
FAX:  (408) 434-6469










Technical Data Restrictions

In case  of sale  to or use of units by DoD:  Use, duplication
or  disclosure   of  any   software,   firmware   or   related
documentation is  subject to  restrictions stated in paragraph
(c) (1)  (ii) of  the Rights  in Technical  Data and  Computer
Software clause  at DFAR 252.227-7013.  For Civilian Agencies:
Use, reproduction,  or disclosure  of the software and related
documentation is  subject to  restrictions set  forth  in  FAR
52.227-19.   Unpublished rights  reserved under  the copyright
laws of the United States.  Maxtor Corporation, 211 River Oaks
Parkway, San Jose, CA 95134.










Copyright Notice

This manual  and all material contained in it are copyrighted.
The manual may not be copied, in whole or in part, without the
written consent  of Maxtor  Corporation.  The contents of this
manual may be revised without prior notice.

  Copyright 1990 by Maxtor Corporation, San Jose, California,
USA.  All rights reserved
       
PREFACE
Maxtor reserves  the right to make changes and/or improvements
to  its   products  without   incurring  any   obligation   to
incorporate such  changes or  improvements in units previously
sold or shipped.

Maxtor publishes descriptive brochures and data sheets, and an
OEM technical  manual for  each product  line.   In  addition,
important changes  to a  product  are  conveyed  in  technical
bulletins sent  to all  product customers  of record.  Changes
that affect  the content of any manual are covered by publish-
ing addenda or revisions to the affected manual.


REFERENCE NUMBERS

For information concerning drive set-up and operation, contact
Maxtor Technical Support at (408) 432-4893.

For information  regarding PC  AT/XT, PS-2,  and  Macintosh
applications, contact  Storage Dimensions Inc. (SDI) Technical
Support at (408) 395-2688, extensions 278-281.
    XT-8000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS

    XT-8000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS


PREFACE.....................................................V


REFERENCE NUMBERS...........................................V


1.0..............................................INTRODUCTION   
   1


2.0....................................PRODUCT SPECIFICATIONS   
   3

  2.1.................................Physical Specifications   
      3
  2.2 .............................Performance Specifications   
      4
  2.3...............................Functional Specifications   
      5
  2.4..............................Reliability Specifications   
      5
  2.5.............................................Error Rates   
      6
  2.6...............................Standards and Regulations   
      6

3.0................................FUNCTIONAL CHARACTERISTICS   
   9

  3.1.............................General Theory of Operation   
      9
  3.2......................Read/Write and Control Electronics   
      9
  3.3.........................................Drive Mechanism   
      10
  3.4...................................Air Filtration System   
      10
  3.5...................................Positioning Mechanism   
      11
  3.6..............................Read/Write Heads and Disks   
      12








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    XT-8000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS

4.0......................................FUNCTIONAL OPERATION   
   15

  4.1.......................................Power Up Sequence   
      15
  4.2 ........................................Drive Selection   
      16
  4.3.......................................Drive Termination   
      17

5.0......................................ELECTRICAL INTERFACE   
   19

  5.1.....................................Control Input Lines   
      25
     5.1.1.........................HEAD SELECT 2 0, 21, 22, 23   
          26
     5.1.2.........................................WRITE GATE   
          26
     5.1.3..........................................READ GATE   
          30
     5.1.4.......................................COMMAND DATA   
          30
     5.1.5.......................................TRANSFER REQ   
          36
     5.1.6................................ADDRESS MARK ENABLE   
          38
       A.....................................Soft Sector Mode   
          38
       B...........................Hard and Soft Sector Modes   
          38
  5.2 ...................................Control Output Lines   
      39
     5.2.1.....................................DRIVE SELECTED   
          39
     5.2.2..............................................READY   
          39
     5.2.3.................................CONFIG-STATUS DATA   
          39
       A................................Status Response Flags   
          40
       B...................Vendor Unique Status Response Bits   
          41
       C.....................Configuration Response Flag Bits   
          44
     5.2.4.......................................TRANSFER ACK   
          45
     5.2.5..........................................ATTENTION   
          45
     5.2.6..............................................INDEX   
          46




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                      TABLE OF CONTENTS

     5.2.7...................ADDRESS MARK FOUND (Soft Sector)   
          46
     5.2.8..........................SECTOR MARK (Hard Sector)   
          47
     5.2.9...................................COMMAND COMPLETE   
          48
  5.3..................Spindle Synchronization Control Option   
      48
  5.4................................Additional Signals on J6   
      49
  5.5.....................................Data Transfer Lines   
      49
     5.5.1......................................NRZ READ DATA   
          50
     5.5.2.....................................NRZ WRITE DATA   
          51
     5.5.3...............................READ/REFERENCE CLOCK   
          52
     5.5.4........................................WRITE CLOCK   
          52

6.0........................................PHYSICAL INTERFACE   
   53

  6.1.........................................J1/P1 Connector   
      54
  6.2.........................................J2/P2 Connector   
      55
  6.3.........................................J3/P3 Connector   
      56
  6.4............................J4/P4 Frame Ground Connector   
      58
  6.5...............................J6/P6 Auxiliary Connector   
      58

7.0...................................PHYSICAL SPECIFICATIONS   
   61

  7.1....................................Mounting Orientation   
      61
  7.2..........................................Mounting Holes   
      61
  7.3.....................................Physical Dimensions   
      62
  7.4...................................Shipping Requirements   
      64
  7.5.....................................Removable Faceplate   
      64







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                      TABLE OF CONTENTS

8.0........................................PCB JUMPER OPTIONS   
   65

  8.1..........................Drive Address Selection Jumper   
      65
  8.2.................................Read Gate Delay Jumpers   
      73
  8.3...................Write Protect Selection Jumper (JP14)   
      74
  8.4............Sequential Spindle Motor Spinup Jumper (JP6)   
      74
  8.5..................................Test Jumpers (JP1-JP3)   
      74
  8.6...........Hard Sector Configuration Jumpers (JP16-JP29)   
      75

9.0.................................MEDIUM DEFECTS AND ERRORS   
   77


APPENDIX:  UNITS OF MEASURE................................81


GLOSSARY...................................................83































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                           FIGURES

    XT-8000E Product Specification & OEM Technical Manual


                           FIGURES

Figure 31..............................Air Filtration System   
11
Figure 32............................Head Positioning System   
12
Figure 41................Power Up Sequence (Jumper JP6 Open)   
15
Figure 42...............................Drive Select Circuit   
16
Figure 51........................Control Cable J1/P1 Signals   
20
Figure 52...........................Data Cable J2/P2 Signals   
22
Figure 53Typical Auxiliary Cable, and Spindle Synchronization
Connection.................................................24
Figure 54.......Control Signals, Driver/Receiver Combination   
26
Figure 55..........Soft Sector Address Mark, WRITE GATE, PLO
Synchronization Format Timing..............................27
Figure 56.Hard Sector WRITE GATE, PLO Synchronization Format
Timing  28
Figure 57.Hard Sector WRITE GATE, PLO Synchronization Format
Timing, Using ADDRESS MARK ENABLE..........................29
Figure 58.............................WRITE GATE Termination   
30
Figure 59........................Typical Serial Operation(s)   
31
Figure 510.......................COMMAND DATA Word Structure   
33
Figure 511..................One Bit Transfer Timing-To Drive   
37
Figure 512................One Bit Transfer Timing-From Drive   
37
Figure 513.........................Write Address Mark Timing   
38
Figure 514.................CONFIG-STATUS DATA Word Structure   
40
Figure 515......................................INDEX Timing   
46
Figure 516............Read Address Mark Timing (Soft Sector)   
47
Figure 517.................Sector Pulse Timing (Hard Sector)   
48
Figure 518.............Data Line Driver/Receiver Combination   
50
Figure 519.......................NRZ READ/WRITE DATA Timings   
51

    XT-8000E Product Specification & OEM Technical Manual


                           FIGURES

Figure 61.............Interface Connector Physical Locations   
54
Figure 62.............................J1 Connector Dimension   
55
Figure 63............................J2 Connector Dimensions   
56
Figure 64..............J3 Connector (Drive PCB, Solder Side)   
56
Figure 65...........Typical Motor Start Current Requirements   
57
Figure 71.....Mechanical Outline and Mounting Hole Locations   
62
Figure 72..........Mechanical Outline, Bottom and Side Views   
63
Figure 73................................Removable Faceplate   
64
Figure 81.....Drive Jumper Options (PCB Part Number 1014150)   
66
Figure 82.....Drive Jumper Options (PCB Part Number 1015468)   
67
Figure 83.....Drive Jumper Options (PCB Part Number 1014520)   
68
Figure 91.................................Defect List Format   
78

    XT-8000E Product Specification & OEM Technical Manual


                            TABLES

    XT-8000E Product Specification & OEM Technical Manual


                            TABLES

Table 21................................Environmental Limits   
3
Table 22...............................Mechanical Dimensions   
3
Table 23..........................Performance Specifications   
4
Table 24...........................Functional Specifications   
5
Table 25..........................Reliability Specifications   
5
Table 26.........................................Error Rates   
6
Table 27...............................DC Power Requirements   
6
Table 41..............................Drive Selection Matrix   
17
Table 51.................Control Cable J1/P1 Pin Assignments   
21
Table 52....................Data Cable J2/P2 Pin Assignments   
23
Table 53................Auxiliary Cable (J6) Pin Assignments   
25
Table 54.............................COMMAND DATA Definition   
32
Table 55........................REQUEST STATUS MODIFIER BITS   
34
Table 56.................REQUEST CONFIGURATION Modifier Bits   
34
Table 57...........................Configuration Subscripted   
35
Table 58...............................CONTROL Modifier Bits   
35
Table 59..........................TRACK OFFSET Modifier Bits   
36
Table 510......................Standard Status Response Bits   
40
Table 511.................Vendor Unique Status Response Bits   
42
Table 512.......................................Motor Status   
43
Table 513.......................SEEK Calibration Error Codes   
43
Table 514................General Configuration Response Bits   
44
Table 515...............Specific Configuration Response Bits   
45

    XT-8000E Product Specification & OEM Technical Manual


                            TABLES

Table 61...............................DC Power Requirements   
58
Table 62...........J6 Auxiliary Signal Cable Pin Assignments   
59
Table 81................................Drive Select Jumpers   
65
Table 82.......................Drive Model Selection Jumpers   
69
Table 83.....................JP37 and JP39 Jumper Selections   
70
Table 84.........Jumper Selections (PCB Part Number 1014150)   
71
Table 85.........Jumper Selections (PCB Part Number 1015468)   
72
Table 86.........Jumper Selections (PCB Part Number 1014520)   
73
Table 87.....................Read Gate Delay Jumper Settings   
74
Table 88....................................Test Pin Jumpers   
75
Table 89.........................Customer Selectable Jumpers   
76
Table 91...........................Maximum Number of Defects   
77

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1.0  INTRODUCTION

       The XT-8000EFamily  disk drives  are  low  cost,  high
       capacity,  high   performance  random   access  storage
       devices using from five to eight nonremovable 5.25-inch
       disks as  storage media.  Each disk surface employs one
       moveable head  to access  1,632 data tracks.  The total
       unformatted capacity  of the  disk drives  ranges  from
       410.09 to 768.92 megabytes.

       The  disk   incorporates  the   Enhanced  Small  Device
       Interface (ESDI)  high performance  5.25-inch standard.
       Among the  resultant benefits  are  a  15  megabit  per
       second  transfer   rate,   status   and   configuration
       reporting across  the interface,  and nonreturn to zero
       (NRZ) data transfer.

       Low cost  and high performance are achieved through the
       use of  a rotary  voice coil actuator and a closed loop
       servo system  using a  dedicated servo  surface.    The
       innovative MAXTORQ rotary voice coil actuator provides
       average access  times of  16 or  18 milliseconds  and a
       track-to-track access  time of  3 milliseconds.    This
       level of  performance is  usually  achieved  only  with
       larger, higher  powered linear  actuators.   The closed
       loop servo  system and  dedicated servo surface combine
       to allow  state-of-the-art recording  densities  (1,376
       tracks per  inch (tpi),  31,596 flux  changes per  inch
       (fci)) in a 5.25-inch package.

       High capacity  is achieved by a balanced combination of
       high areal  recording density, run-length limited (RLL)
       data encoding  techniques, and  high density  packaging
       techniques.     Maxtor's  advanced  MAXPAK  electronic
       packaging  techniques   use  miniature   surface  mount
       devices to allow all electronic circuitry to fit on one
       printed circuit  board (PCB).   Advanced head flexures,
       and thin  film sliders,  allow closer spacing of disks,
       and therefore allow a higher number of disks in a 5.25-
       inch  package.     Maxtor's   unique  integrated  drive
       motor/spindle design allows a deeper head disk assembly
       (HDA)   casting   than   conventional   designs,   thus
       permitting more disks to be used.

       The  electrical   interface  is   compatible  with  the
       industry standards  established by  the ESDI committee.
       The drive  size and  mounting are also identical to the
       industry standard  5.25-inch floppy and Winchester disk
       drives, and  the disk uses the same direct current (DC)
       voltages and  connectors.   No alternating current (AC)
       power is required.






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       Key features of the drive include:

         Storage  capacity  of  410.09  to  768.92  megabytes
         nominal unformatted.

         Same physical  size and  mounting as standard floppy
         disk drives.

         Same  control   and  data   cabling  as   ST-506/412
         interface drives.

         Same DC voltages as standard floppy disk drives.

         No AC voltage required.

         Rotary voice  coil actuator  and closed  loop  servo
         system for fast, accurate head positioning.

         Microprocessor-controlled  servo   for  fast  access
         times, high  reliability, and high density functional
         packaging.

         15.0 megabit per second transfer rate.

         ESDI interface.

         Track capacity of 31,410 bytes minimum, unformatted.

         Single PCB for improved reliability.

         Automatic actuator lock.

         Brushless DC spindle motor inside disk hub.

         Microprocessor-controlled    spindle    motor    for
         precision  speed   control  (0.1%)  under  all  load
         conditions.

         Dynamic braking during power down cycle.

         User selectable hard or soft sectors.

         Synchronization of  spindle motors for parallel data
         transfer of multiple drives.













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2.0  PRODUCT SPECIFICATIONS


2.1  PHYSICAL SPECIFICATIONS


                               

                          Table 21
                     Environmental Limits



                               

                          Table 22
                    Mechanical Dimensions


       NOTE:   Forced air  cooling of approximately 500 linear
       feet per minute across the PCB is recommended.


2.2  PERFORMANCE SPECIFICATIONS


                               

                          Table 23
                  Performance Specifications



2.3  FUNCTIONAL SPECIFICATIONS


                               

                          Table 24
                  Functional Specifications



2.4  RELIABILITY SPECIFICATIONS


                               

                          Table 25
                  Reliability Specifications

    XT-8000E Product Specification & OEM Technical Manual


2.5  ERROR RATES


                               

                          Table 26
                         Error Rates



                               

                          Table 27
                    DC Power Requirements



2.6  STANDARDS AND REGULATIONS

       It is  intended that the Maxtor XT-8000E Family of disk
       drives satisfy the following standards and regulations.

       UNDERWRITERS LABORATORIES (UL) is United States safety;
       UL 478,  Standard  for  Safety,  Electronic  Processing
       Units and Systems.

       CANADIAN  STANDARDS   ASSOCIATION  (CSA)   is  Canadian
       safety; CSA C22.2 No. 220, 1986, Information Processing
       and  Business   Equipment  (Consumer   and   Commercial
       Products).

       VERBAND  DEUTSCHER  ELECTROTECHNIKER  (VDE)  is  German
       safety; VDE  0806/8.81, Safety of Office Appliances and
       Business Equipment.























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3.0  FUNCTIONAL CHARACTERISTICS


3.1  GENERAL THEORY OF OPERATION

       The  drive   consists   of   read/write   and   control
       electronics, read/write  heads, a  servo head,  a  head
       positioning actuator,  media,  and  an  air  filtration
       system.     The  components   perform   the   following
       functions:

         Interpret and generate control signals
         Position the heads over the desired track
         Read and write data
         Provide a contamination-free environment


3.2  READ/WRITE AND CONTROL ELECTRONICS

       Drive electronics  are packaged  on a single PCB.  This
       board, which includes two microprocessors, performs the
       following functions:

          Reading and writing of data
          Index detection
          Head positioning
          Head selection
          Drive selection
          Fault detection
          Voice coil actuator drive circuitry
          Track zero detection
          Recalibration to track zero on power up
          Track position counter
          Power and speed control for spindle drive motor
          Braking for the spindle drive motor
          Drive up-to-speed indication circuit
          Monitoring for write fault conditions
          Control of all internal timing
          Generation of seek complete signals
          RLL encoding/decoding
          Data separation
          Address mark detection (soft sector)
          Sector detection (hard sector)
          Spindle synchronization


3.3  DRIVE MECHANISM

       A  brushless  DC  drive  motor,  contained  within  the
       spindle hub,  rotates the  spindle at 3,600 revolutions
       per minute.   The  motor and  spindle are  designed  to
       ensure a  low vibration level.  Dynamic braking is used

    XT-8000E Product Specification & OEM Technical Manual


       to quickly  stop the  spindle motor  when power  is re-
       moved.     The  HDA   is  shock   mounted  to  minimize
       transmission of vibration through the chassis or frame.


3.4  AIR FILTRATION SYSTEM

       The disks  and read/write  heads are  assembled  in  an
       ultra clean-air environment, and then sealed within the
       HDA.   The HDA  contains an  internal absolute  filter,
       mounted  inside   the  casting,   to  provide  constant
       internal air  filtration.   A second filter, located on
       the  bottom  of  the  base  casting,  permits  pressure
       equalization between  internal and  ambient air.    See
       Figure 31, Air Filtration System.


                               

                          Figure 31
                    Air Filtration System



3.5  POSITIONING MECHANISM

       The  read/write   heads  are   mounted  on  a  head/arm
       assembly, which  is then  mounted  on  a  ball  bearing
       supported shaft.   See  Figure  32,  Head  Positioning
       System.   The voice  coil,  an  integral  part  of  the
       head/arm assembly,  lies inside the magnet housing when
       installed  in  the  drive.    Current  from  the  power
       amplifier, controlled  by the  servo system,  causes  a
       magnetic field  in the voice coil, which either aids or
       opposes the  field around  the permanent magnets.  This
       reaction causes  the voice  coil  to  move  within  the
       magnetic field.   Since  the  head/arm  assemblies  are
       mounted on  the voice  coil, the voice coil movement is
       transferred, through  the pivot  point, directly to the
       heads,  and   positions  the  heads  over  the  desired
       cylinder.


                               

                          Figure 32
                   Head Positioning System


       Actuator movement  is controlled  by the servo feedback
       signal from  the servo  head.  The servo information is






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       prewritten at  the factory.   This servo information is
       used as  a control  signal for  the actuator to provide
       track-crossing signals  during a seek operation, track-
       following signals  during on  cylinder  operation,  and
       timing information,  such as index, sector pulses (hard
       sector) and servo clock.


3.6  READ/WRITE HEADS AND DISKS

       The medium  uses thin  metallic film  deposited on  130
       millimeter diameter  aluminum substrates.   The coating
       formulation, together  with the low load force/low mass
       Whitney-type  heads,  permit  highly  reliable  contact
       start/stop operation.    The  metallic  recording  film
       yields high amplitude signals, and very high resolution
       performance,  compared  to  conventional  oxide  coated
       medium.   The metallic  medium also  provides a  highly
       abrasion-resistant surface,  decreasing  the  potential
       for damage caused by shipping shock and vibration.

       Data on  each of  the data surfaces is read by one of 8
       or 15  read/write heads,  each of  which accesses 1,632
       tracks.   There  is  one  surface  dedicated  to  servo
       information in each drive.

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4.0  FUNCTIONAL OPERATION


4.1  POWER UP SEQUENCE

       DC power  (+5 volts  and +12 volts) may be supplied to the
       drive in any order, but +12 volts DC are required to start
       the spindle  motor.   See Figure  4.1, Power  Up  Sequence
       (Jumper JP6  Open).   The motor  power up is controlled by
       the status  of jumper  JP6 on  the drive  electronics  PCB
       assembly.   (The location  and function of all PCB jumpers
       are shown  in Figures  81, 82,  and  83,  Drive  Jumper
       Options,  and   in  Tables   84,  85,  and  86,  Jumper
       Selections.)


                                

                           Figure 41
               Power Up Sequence (Jumper JP6 Open)


       If jumper  JP6 is open, the spindle power up sequencing is
       initiated by  the issuance  of  the  START  MOTOR  CONTROL
       command.

       When the  spindle reaches  full speed,  the actuator  lock
       automatically disengages and the heads then recalibrate to
       track zero.   Upon  successfully recalibrating,  READY and
       COMMAND COMPLETE  status signals  are true.  The unit does
       not perform any read, write, or seek functions until READY
       is true.  (If after starting, 1,000 revolutions per minute
       is not  reached in  7  seconds,  an  automatic  shut  down
       procedure is initiated; power to the spindle motor is shut
       off and the drive does not become READY.)

       If jumper  JP6 is shorted, the spindle power up sequencing
       is initiated  by the  application  of  DC  power.    (When
       shipped, the JP6 jumper is shorted.)


4.2  DRIVE SELECTION

       Drive selection  occurs when  the  controller  places  the
       address of  the drive  to be  selected on  the three drive
       select lines.   See  Figure 42, Drive Select Circuit, and
       Table 41,  Drive Selection  Matrix.   Only  the  selected
       drive responds to the input signals, and only that drive's
       output signals  are then  gated to  the controller.    The
       details of  setting the drive selection jumper are covered
       in section 8.1, Drive Address Selection Jumper.






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                           Figure 42
                      Drive Select Circuit



                                

                            Table 41
                     Drive Selection Matrix



4.3  DRIVE TERMINATION

       If more  than one  Maxtor drive  is used  in a system, the
       terminator packs  (RN13 and  RN14) must  be removed in all
       but the  last drive  in the string.  Figures 81, 82, and
       83, Drive  Jumper Options,  show the location of RN13 and
       RN14.
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      XT-8000E Product Specification & OEM Technical Manual


5.0  ELECTRICAL INTERFACE

       The interface  to the  drive  can  be  divided  into  four
       separate  categories,   each  of   which   is   physically
       separated.

         Control signals
         Data signals
         DC power
         Auxiliary signals

       All control  lines are digital (open collector transistor-
       transistor logic (TTL)), and either provide signals to the
       drive  (input)  or  signals  to  the  host  (output),  via
       interface connection J1/P1.  The data transfer signals are
       differential, and  provide data  either to (write) or from
       (read) the drive, via J2/P2.

       Figure  51,  Control  Cable  J1/P1  Signals,  Table  51,
       Control Cable  J1/P1 Pin  Assignments,  Figure  52,  Data
       Cable J2/P2  Signals, and  Table 52, Data Cable J2/P2 Pin
       Assignments,   show    connector   pin   assignments   and
       interconnection of cabling between the host controller and
       drives.


                                

                           Figure 51
                   Control Cable J1/P1 Signals



                                

                            Table 51
               Control Cable J1/P1 Pin Assignments



                                

                           Figure 52
                    Data Cable J2/P2 Signals



                                

                            Table 52
                Data Cable J2/P2 Pin Assignments






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       Figure  53,   Typical  Auxiliary   Cable,   and   Spindle
       Synchronization Connection, and Table 53, Auxiliary Cable
       (J6) Pin  Assignments, show  connector pin assignments and
       interconnection  of   cabling  between   drives  for   the
       auxiliary signals.


                                

                           Figure 53
 Typical Auxiliary Cable, and Spindle Synchronization Connection



                                

                            Table 53
              Auxiliary Cable (J6) Pin Assignments



5.1  CONTROL INPUT LINES

       The control  input signals  are of two types:  those to be
       multiplexed in  a multidrive system, and those intended to
       do the  multiplexing.   The signals  to be multiplexed are
       WRITE GATE,  TRANSFER REQ,  and COMMAND DATA.  The signals
       to do the multiplexing are DRIVE SELECT 1, DRIVE SELECT 2,
       and DRIVE SELECT 3.

       The   input    lines   have   the   following   electrical
       specifications.   Refer to  Figure 54,  Control  Signals,
       Driver/Receiver Combination, for the recommended circuit.

       TRUE: 0.0 V DC to 0.4 V DC = 1 @ -48 mA (max)
       FALSE:  2.5 V  DC to  5.25 V  DC  =  0  @  +250  A  (open
       collector)


                                

                           Figure 54
          Control Signals, Driver/Receiver Combination



5.1.1     HEAD SELECT 20, 21, 22, 23

       The  four  HEAD  SELECT  lines  allow  selection  of  each
       individual read/  write head  in a  binary coded sequence.
       HEAD SELECT  20 is the least significant line.  Data heads
       are numbered  and addressed continuously from zero through
       the maximum  head number.   When all HEAD SELECT lines are
       high (inactive), head zero is selected.



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       Addressing more  heads than  contained in the drive (eight
       heads for  the XT-8380E, fifteen for the XT-8760E) results
       in a  write fault  when  attempting  to  perform  a  write
       operation.

       A 150 ohm resistor pack allows for line termination.


5.1.2     WRITE GATE

       The active  state of  this signal,  or low  level, enables
       write data to be written on the disk.

       The HI  to LO  transition of  this signal  creates a write
       splice, and initiates the writing of the data phase-locked
       oscillator (PLO)  synchronization field  by the drive, see
       Figure 55,  Soft Sector  Address Mark,  WRITE  GATE,  PLO
       Synchronization Format Timing, and Figure 56, Hard Sector
       WRITE GATE,  PLO Synchronization Format Timing.  When for-
       matting, WRITE GATE should be deactivated for 2 bit times,
       minimum, between  the address  area and  the data area, to
       identify to  the drive  the beginning of the data PLO syn-
       chronization field.

       NOTE: The controller must send zeros during the writing of
       a PLO synchronization field.


                                

                           Figure 55
Soft Sector Address Mark, WRITE GATE, PLO Synchronization Format
                             Timing



                                

                           Figure 56
    Hard Sector WRITE GATE, PLO Synchronization Format Timing


       An alternate  format timing in hard sector mode, using the
       ADDRESS MARK  ENABLE signal,  is shown in Figure 57, Hard
       Sector WRITE  GATE,  PLO  Synchronization  Format  Timing,
       Using ADDRESS MARK ENABLE.


                                

                           Figure 57
Hard Sector WRITE GATE, PLO Synchronization Format Timing, Using
                       ADDRESS MARK ENABLE




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       This line  is protected  from  terminator  power  loss  by
       implementation of  the circuit  shown in Figure 58, WRITE
       GATE Termination.


                                

                           Figure 58
                     WRITE GATE Termination



5.1.3     READ GATE

       The active  state of  this signal,  or low  level, enables
       data to  be read  from the  disk.   This signal  should be
       activated only  during a  PLO synchronization  field.  The
       PLO synchronization  field  length  is  indicated  by  the
       response to  the REQUEST  PLO SYNC  FIELD LENGTH  command.
       READ GATE  must be  deactivated when  passing over a write
       splice area.

       A 150 ohm resistor pack allows for line termination.


5.1.4     COMMAND DATA

       When presenting  a command,  sixteen information  bits  of
       serial data,  plus parity,  are presented  on  this  line.
       This data  is to  be controlled  by the handshake protocol
       with signals  TRANSFER REQ  and TRANSFER  ACK.  See Figure
       59, Typical  Serial Operation(s).   Upon  receipt of this
       serial data,  the drive performs the required function, as
       specified by  the bit  configuration.  Data is transmitted
       most significant  byte first.  See Table 54, COMMAND DATA
       Definition,  for   the  meaning   of   the   various   bit
       combinations,  and   Figure  510,   COMMAND   DATA   Word
       Structure.    See  also  Figure  511,  One  Bit  Transfer
       Timing-To Drive.   Odd  parity must  be maintained.   (The
       number of  bits set to one in a command, including parity,
       must be odd.)


                                

                           Figure 59
                   Typical Serial Operation(s)



                                

                            Table 54
                     COMMAND DATA Definition



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       No communications  may be  attempted  unless  the  COMMAND
       COMPLETE line is true.

       Reading and  writing are inhibited during the execution of
       commands.

       NOTE:   The COMMAND DATA line must be at a logic zero when
       not in use.

       A 150 ohm resistor pack allows for line termination.


                                

                           Figure 510
                   COMMAND DATA Word Structure


       SEEK (0000):  This command causes the drive to seek to the
       cylinder indicated  in bits  eleven through  zero.  A SEEK
       command restores track offsets to zero.

       RECALIBRATE (0001):   This  command causes the actuator to
       return to  cylinder 0000.   A RECALIBRATE command restores
       track offsets to zero.

       REQUEST STATUS  (0010):   This command causes the drive to
       send  16  bits  of  standard  status  information  to  the
       controller, as  determined by  the command  modifier bits.
       See Table 59, Standard Status Response Bits

       When the  command modifier  bits (eleven through eight) of
       the REQUEST  STATUS command  are 0000,  the drive responds
       with 16  bits of  standard status.  See Table 55, REQUEST
       STATUS MODIFIER BITS.  Bits fifteen through twelve of this
       status are  defined as  state bits,  which  do  not  cause
       ATTENTION to  be asserted.   Bits  eleven through  zero of
       this status  are fault,  or change  of status, bits, which
       cause ATTENTION to be asserted each time one is set.

       REQUEST STATUS  MODIFIER BITS:   When the command modifier
       bits (eleven  through eight) of the REQUEST STATUS command
       are 0001  through 0111, the drive responds with the vendor
       unique status.   See  Table 55,  REQUEST STATUS  MODIFIER
       BITS.   The  number  of  vendor  unique  status  words  is
       specified by the configuration data.


                                

                            Table 55
                  REQUEST STATUS MODIFIER BITS





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       REQUEST CONFIGURATION  (0011):   This command  causes  the
       drive to  send  16  bits  of  configuration  data  to  the
       controller.    The  specific  configuration  requested  is
       specified by  bits eleven through eight of the command, as
       shown in  Table 56,  REQUEST CONFIGURATION Modifier Bits.
       Furthermore,  the   drive  responds   to  the  subscripted
       command, REQUEST FOR CONFIGURATION, as shown in Table 57,
       Configuration Subscripted.


                                

                            Table 56
               REQUEST CONFIGURATION Modifier Bits



                                

                            Table 57
                    Configuration Subscripted


       CONTROL  (0101):     This   command  causes   the  control
       operations specified  by bits  eleven through  eight to be
       performed as  described in  Table  58,  CONTROL  Modifier
       Bits.


                                

                            Table 58
                      CONTROL Modifier Bits


       TRACK OFFSET  (0111): This  command causes  the  drive  to
       perform  a  track  offset  in  the  direction  and  amount
       specified by  bits eleven  through eight,  as outlined  in
       Table 59,  TRACK OFFSET Modifier Bits.  Each offset value
       is 36  microinches.  SEEK and RECALIBRATE commands restore
       track offsets to zero.

       NOTE: Whenever there  is any  track offset, writing is not
       allowed.


                                

                            Table 59
                   TRACK OFFSET Modifier Bits


       INITIATE DIAGNOSTICS  (1000):   This  command  causes  the
       drive to  perform 10,000 random seeks as a diagnostic aid.



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       Successful completion  of the  diagnostics is indicated by
       COMMAND COMPLETE with no ATTENTION.

       SET UNFORMATTED  BYTES PER  SECTOR (1001):   This  command
       causes the  drive to  set the  number of unformatted bytes
       per sector  indicated in  bits eleven  through zero.  This
       command is  valid only if the drive is configured to be in
       the drive  hard sectored  mode, JP31  removed, and  jumper
       JP30 is  installed.   (Jumper 16  through 29  settings are
       ignored.)   For less  than 4,095 bytes per sector, command
       A40Xh is used.

       SET HIGH  ORDER VALUE  (1010):  A40Xh, where X defines the
       upper four  bits of  the number  of unformatted  bytes per
       hard sector.

       SET CONFIGURATION  (1110):   E101h sets  the drive to soft
       sector mode.   E102h  sets the  drive to hard sector mode.
       The number of bytes per sector defaults to 258.


5.1.5     TRANSFER REQ

       This line  functions as a handshake signal, in conjunction
       with TRANSFER ACK, during command and configuration/status
       transfers.   See Figure  511, One  Bit Transfer Timing-To
       Drive, and  Figure  512,  One  Bit  Transfer  Timing-From
       Drive, for  timing.   The  transfer  speed  (one  complete
       handshake) takes  typically 11.76  microseconds  per  bit.
       Longer times may be experienced, depending on the overhead
       experienced at the controller.


                                

                           Figure 511
                One Bit Transfer Timing-To Drive



                                

                           Figure 512
               One Bit Transfer Timing-From Drive













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5.1.6     ADDRESS MARK ENABLE


A    SOFT SECTOR MODE

       This signal,  when  active  with  WRITE  GATE,  causes  an
       address mark to be written.  ADDRESS MARK ENABLE is active
       for 24  bit times.   See  Figure 513,  Write Address Mark
       Timing, for timing.

       ADDRESS MARK  ENABLE, when  active without  WRITE GATE  or
       READ GATE, causes a search for address marks.


                                

                           Figure 513
                    Write Address Mark Timing



B    HARD AND SOFT SECTOR MODES

       If WRITE  GATE is  true,  the  LO  to  HI  transition,  or
       deassertion of  ADDRESS MARK  ENABLE, causes  the drive to
       begin writing the ID PLO synchronization field.  The drive
       does not  write an  address mark  in this mode (see Figure
       55,  Soft   Sector  Address   Mark,   WRITE   GATE,   PLO
       Synchronization Format Timing, and Figure 57, Hard Sector
       WRITE  GATE,  PLO  Synchronization  Format  Timing,  Using
       ADDRESS MARK ENABLE).  The controller must send zeros when
       writing the PLO synchronization field.

       A 150 ohm transistor pack allows for line termination.


5.2  CONTROL OUTPUT LINES

       The  output  control  signals  are  driven  with  an  open
       collector output stage, capable of sinking a maximum of 48
       milliamps at  low level,  or true  state, with  a  maximum
       voltage of  0.4 volts,  measured at  the driver.  When the
       line driver  is in  the high  level, or  false state,  the
       driver transistor  is off and collector leakage current is
       a maximum of 250 microamps.

       All J1  output lines are enabled by their respective DRIVE
       SELECT decodes.

       Figure 54,  Control Signals, Driver/Receiver Combination,
       shows the recommended circuit.






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5.2.1     DRIVE SELECTED

       DRIVE SELECTED  is a  status line,  provided at  the J2/P2
       connector, to  inform the  host system  of  the  selection
       status of the drive.  The DRIVE SELECTED line is driven by
       a TTL  open collector  driver, as  shown  in  Figure  54,
       Control Signals, Driver/Receiver Combination.  This signal
       becomes active only when the drive is selected, as defined
       in section  4.2, Drive  Selection.  The DRIVE SELECT lines
       at J1/Pl are activated by the host system.


5.2.2     READY

       This signal  indicates that  the spindle  is up  to speed.
       This interface  signal, when  true, together  with COMMAND
       COMPLETE, indicates  that the  drive  is  ready  to  read,
       write, or  seek.   When the line is false, all writing and
       seeking is inhibited.


5.2.3     CONFIG-STATUS DATA

       The drive  presents serial  data on this line upon request
       from the  controller.   See  Figure  59,  Typical  Serial
       Operation(s), for  typical operation.   This CONFIG-STATUS
       serial data is presented to the interface, and transferred
       using the  handshake protocol,  with signals  TRANSFER REQ
       and TRANSFER  ACK.   See Figure  511,  One  Bit  Transfer
       Timing-To Drive.   Once  initiated, 16  bits, plus parity,
       are transmitted most significant bit first.  Odd parity is
       maintained.   See Figure  514,  CONFIG-STATUS  DATA  Word
       Structure.


                                

                           Figure 514
                CONFIG-STATUS DATA Word Structure



A    STATUS RESPONSE FLAGS

       In response  to the  REQUEST STATUS  command  16  bits  of
       status information  are returned  to the  controller.  See
       section 5.1.4, COMMAND DATA.  Odd parity is maintained.

       If the  command modifier  bits (eleven  through eight) are
       0000, the  standard status  information is  returned.  See
       Table 510, Standard Status Response Bits.






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                           Table 510
                  Standard Status Response Bits


       Bits fifteen  through twelve  of the status are defined as
       state bits,  which do  not cause ATTENTION to be asserted.
       Bits eleven  through zero  are fault, or change of status,
       bits which cause ATTENTION to be asserted.

       Conditions that can cause a write fault are:

              Having no write current with WRITE GATE active and
            the drive selected.
              Writing before COMMAND COMPLETE.
              Having multiple  heads selected, no head selected,
            or  improperly  selecting  a  head  with  WRITE  GATE
            active.
              Writing while the head is off track.
              Having DC voltages grossly out of tolerance.
              Having WRITE  GATE active  to  a  write  protected
            drive.
              Sending nonzero  data during a PLO synchronization
            field write.
              Simultaneously  activating  READ  GATE  and  WRITE
            GATE.


B    VENDOR UNIQUE STATUS RESPONSE BITS

       If the  command modifier  bits (eleven  through eight) are
       used, the  vendor unique status information shown in Table
       511, Vendor Unique Status Response Bits, is returned.


                                

                           Table 511
               Vendor Unique Status Response Bits


       The motor  status portion of word one of the vendor unique
       response is translated as in Table 512, Motor Status.


                                

                           Table 512
                          Motor Status


       The SEEK  calibration error  portion of  word two  is only
       valid with  bit nine  of word one set.  With this bit set,



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       the error  code is  interpreted as  in  Table  513,  SEEK
       Calibration Error Codes.


                                

                           Table 513
                  SEEK Calibration Error Codes



C    CONFIGURATION RESPONSE FLAG BITS

       In response  to the REQUEST CONFIGURATION command  16 bits
       of  configuration   information  are   returned   to   the
       controller.   See section 5.1.4, COMMAND DATA.  Odd parity
       is maintained.

       If the  command modifier  bits (eleven  through eight) are
       0000, the  general configuration  status information shown
       in Table  514, General  Configuration Response  Bits,  is
       returned.


                                

                           Table 514
               General Configuration Response Bits


       If other  command modifier  bits are  used,  the  specific
       configuration information  shown in  Table 515,  Specific
       Configuration Response Bits, is returned.


                                

                           Table 515
              Specific Configuration Response Bits


       One subscripted  status  response  command  is  supported,
       SPINDLE SYNCHRONIZATION STATUS (0011 0000 0000 0001).  The
       response is 1000 0000 0000 0000 if spindle synchronization
       is active, or 0000 0000 0000 0000 if it is not active.


5.2.4     TRANSFER ACK

       This signal  functions as  a handshake  signal, along with
       TRANSFER  REQ,   during  COMMAND  data  and  CONFIG-STATUS
       transfers.   See Figure  511, One  Bit Transfer Timing-To





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       Drive, and  Figure  512,  One  Bit  Transfer  Timing-From
       Drive.


5.2.5     ATTENTION

       This  output   is  asserted   when  the  drive  wants  the
       controller to  request its  standard status.    Generally,
       this is  a result  of a  fault condition  or a  change  of
       status.   Writing is inhibited when ATTENTION is asserted.
       ATTENTION is  deactivated by the RESET INTERFACE ATTENTION
       command (section 5.1.4, COMMAND DATA).


5.2.6     INDEX

       This pulse  is provided  by the drive once each revolution
       to indicate  the beginning  of a  track.   Normally,  this
       signal is high and makes the transition to low to indicate
       INDEX.   Only the  transition at  the leading  edge of the
       pulse is  accurately controlled.   The  period (T) of this
       signal is  reciprocal of the rotational speed.  See Figure
       515, INDEX  Timing.   This signal  is  available  on  the
       command cable  J1/P1 (gated)  and on  the data cable J2/P2
       (ungated).   Jumpers R220  and R221,  or JP9, depending on
       PCB level,  allow selection  of  2.8  microseconds  or  70
       microsecond pulse width.  Default factory selection is 2.8
       microsecond pulse width.


                                

                           Figure 515
                          INDEX Timing



5.2.7     ADDRESS MARK FOUND (Soft Sector)

       This signal  indicates the  detection of  the  end  of  an
       address mark.   See  Figure 516,  Read Address Mark (Soft
       Sector), for timing.


                                

                           Figure 516
             Read Address Mark Timing (Soft Sector)









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5.2.8     SECTOR MARK (Hard Sector)

       This optional  interface signal  indicates the  start of a
       sector.   No short  sectors are allowed.  The leading edge
       of the  asserted sector  pulse is  the only  edge that  is
       accurately controlled.   The  INDEX pulse indicates sector
       zero.  See Figure 517, Sector Pulse Timing (Hard Sector).


                                

                           Figure 517
                Sector Pulse Timing (Hard Sector)



5.2.9     COMMAND COMPLETE

       This signal  is  a  status  line  provided  at  the  J2/P2
       connector.   This is  an ungated  output from  the  drive,
       which allows  the host  to  monitor  the  drive's  COMMAND
       COMPLETE  status   during  overlapped   commands,  without
       selecting the  drive.   This signal  line becomes false in
       the following cases:

         When a  recalibration sequence  is initiated  (by drive
          logic) at  power on,  if the  read/write heads  are not
          over track zero.

         Upon receipt  of the  first COMMAND  DATA bit.  COMMAND
          COMPLETE  stays   false  during   the  entire   command
          sequence.

       This signal  is driven  by an  open collector  driver,  as
       shown in  Figure  54,  Control  Signals,  Driver/Receiver
       Combination.


5.3  SPINDLE SYNCHRONIZATION CONTROL OPTION

       This feature  allows up  to 48  drives to  synchronize the
       angular position  of their  spindles such that their INDEX
       signals line  up to within 20 microseconds of each other.
       All drives  synchronize their spindles to the MAPIN signal
       of J6  such that  their INDEX signal leads MAPIN by 40 10
       microseconds.  In the absence of a MAPIN signal, the drive
       synchronizes to its internal clock.

       The MAPIN  is a  TTL signal at 60.0 Hz, with a pulse width
       of 20 microseconds.  It is derived from either an external
       source, or from the MAPOUT signal available on J6 from one
       drive defined as the master drive.





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       In the  event synchronization  is lost after the drive has
       reported it achieved synchronization, ATTENTION is set.


5.4  ADDITIONAL SIGNALS ON J6

       The light-emitting diode (LED) output on J6 is an optional
       drive-selected signal that is available for use in systems
       that cannot use the LED on the faceplate.

       The REMOTE  WRITE PROTECT  input allows  the drive  to  be
       write protected via the J6 connector.  The active state of
       this signal,  or low  level,  prohibits  data  from  being
       written to the drive.

       See Figure  53,  Typical  Auxiliary  Cable,  and  Spindle
       Synchronization Connection, for a typical configuration.


5.5  DATA TRANSFER LINES

       All lines associated with the transfer of data between the
       drive and  the host  system are  differential and  are not
       multiplexed.   These  lines  are  provided  at  the  J2/P2
       connectors on all drives.

       Four pairs  of balanced  signals are used for the transfer
       of data  and clock:  NRZ WRITE DATA , NRZ READ DATA, WRITE
       CLOCK, and  READ/REFERENCE CLOCK.   Figure 518, Data Line
       Driver/Receiver Combination,  illustrates the  recommended
       driver/receiver circuit.


                                

                           Figure 518
              Data Line Driver/Receiver Combination



5.5.1     NRZ READ DATA

       The data  recovered by  reading  a  prerecorded  track  is
       transmitted to  the host  system via the differential pair
       of NRZ  READ DATA lines.  This data is clocked by the READ
       CLOCK signal.    See  Figure  519,  NRZ  READ/WRITE  DATA
       Timings, for timing.  These lines are held at a zero level
       until PLO  synchronization has  been obtained  and data is
       valid.








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                           Figure 519
                   NRZ READ/WRITE DATA Timings



5.5.2     NRZ WRITE DATA

       This is  a differential  pair that  defines the data to be
       written on  the track.   This data is clocked by the WRITE
       CLOCK signal.    See  Figure  519,  NRZ  READ/WRITE  DATA
       Timings, for  timing.   These lines must be held at a zero
       level during the writing of PLO synchronization.


5.5.3     READ/REFERENCE CLOCK

       The  timing   diagram,  as   shown  in  Figure  519,  NRZ
       READ/WRITE DATA  Timings,  depicts  the  necessary  timing
       restrictions for proper read/write operation of the drive.
       The REFERENCE  CLOCK signal  from the drive determines the
       data transfer  rate.   The transition from REFERENCE CLOCK
       to READ  CLOCK is performed without glitches.  Two missing
       clock cycles are permissible.

       The REFERENCE CLOCK rate is 15.080 megahertz, typical.

       The READ CLOCK rate is 15.080 megahertz, typical.


5.5.4     WRITE CLOCK

       WRITE CLOCK  is provided  by the controller and must be at
       the bit  data transfer  rate.   This  clock  frequency  is
       dictated by  the READ/REFERENCE  CLOCK  during  the  write
       operation.   See Figure  519, NRZ READ/WRITE Timings, for
       timing.

       WRITE CLOCK  need not  be  continuously  supplied  to  the
       drive.   WRITE CLOCK  is supplied before beginning a write
       operation and  must last  for the  duration of  the  write
       operation.














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6.0  PHYSICAL INTERFACE

       The electrical  interface between  the drive  and the host
       controller is via four connectors:

         J1 - Control signals (multiplexed)
         J2 - Read/write signals (radial)
         J3 - DC power input
         J4 - Frame ground

       J6  is   the  spindle  synchronization  connector  and  is
       connected to the drives using this option.

       Refer  to   Figure  61,   Interface  Connector   Physical
       Locations, for connector locations.


                                

                           Figure 61
             Interface Connector Physical Locations



6.1  J1/P1 CONNECTOR

       Connection  to  J1  is  via  a  thirty-four-pin  PCB  edge
       connector.  The dimensions for this connector are shown in
       Figure  62,  J1  Connector  Dimensions.    The  pins  are
       numbered one  through  thirty-four,  with  the  even  pins
       located on  the component  side of  the PCB.   Pin  two is
       located on  the end of the PCB connector closest to the DC
       power connector  J3/P3.   A key  slot is  provided between
       pins four  and six.   The recommended mating connector for
       P1 is  AMP  ribbon  connector,  part  number  88373-3,  or
       equivalent.


                                

                           Figure 62
                     J1 Connector Dimension



6.2  J2/P2 CONNECTOR

       Connection of  J2 is  via a twenty-pin PCB edge connector.
       The dimensions  for the connector are shown in Figure 63,
       J2 Connector  Dimensions.    The  pins  are  numbered  one
       through  twenty,   with  the  even  pins  located  on  the
       component  side  of  the  PCB.    The  recommended  mating
       connector for  P2 is  AMP ribbon  connector,  part  number




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       88373-6.   A key  slot is  provided between  pins four and
       six.


                                

                           Figure 63
                     J2 Connector Dimensions



6.3  J3/P3 CONNECTOR

       The DC  power connector  (J3), Figure  64,  J3  Connector
       (Drive PCB,  Solder Side),  is a  four-pin AMP MATE-N-LOCK
       connector, part  number 350543-1,  mounted on  the  solder
       side of the PCB.  The recommended mating connector (P3) is
       AMP part  number 1-480424-0,  using AMP  pins part  number
       350078-4 (strip),  or part  number 61173-4  (loose piece).
       J3 pins are numbered as shown in Figure 64.


                                

                           Figure 64
              J3 Connector (Drive PCB, Solder Side)


       The required  voltages and  current  levels  on  connector
       J3/P3 are shown in Figure 65, Typical Motor Start Current
       Requirements, and Table 61, DC Power Requirements.

       NOTE:   A short  duration in-rush  current  exceeding  the
       maximum specification  on both  the 5  volt  and  12  volt
       supplies may  be observed  at power on.  This is dependent
       on the power supply used, and is due to charging of bypass
       and storage capacitors.  See Table 61.


                                

                           Figure 65
            Typical Motor Start Current Requirements



                                

                            Table 61
                      DC Power Requirements







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6.4  J4/P4 FRAME GROUND CONNECTOR

       The frame  ground connection  is a Faston-type connection,
       AMP part number 61761-2.  The recommended mating connector
       is AMP  62187-1.   If wire  is used,  the hole  in J4  ac-
       commodates a  maximum wire size of 18 AWG.  Normally, this
       connection should not be used.


6.5  J6/P6 AUXILIARY CONNECTOR

       The auxiliary  connector  is  a  Berg  68451-121,  ten-pin
       connector.   The mating  connector is a 3M 3473-6010.  See
       Table 62,  J6 Auxiliary Signal Cable Pin Assignments, for
       pin assignments.


                                

                            Table 62
            J6 Auxiliary Signal Cable Pin Assignments




































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7.0  PHYSICAL SPECIFICATIONS

       This  section   describes  the   mechanical  and  mounting
       recommendations for the drive.


7.1  MOUNTING ORIENTATION

       The drive may be mounted in any orientation.  In any final
       mounting configuration,  insure that  the operation of the
       three shock  mounts, which  isolate the  base casting from
       the frame,  is not  restricted.   Certain switching  power
       supplies may  emanate electrical  noise which degrades the
       specified read  error rate.   For best results, orient the
       drive so  that the  PCB assembly  is not adjacent to these
       noise sources.


7.2  MOUNTING HOLES

       Eight mounting  holes, four  on the bottom and two on each
       side,  are   provided  for  mounting  the  drive  into  an
       enclosure.  The size and location of these holes, shown in
       Figure  71,   Mechanical  Outline   and   Mounting   Hole
       Locations,  are  identical  to  industry  standard  floppy
       drives.

       CAUTION:   The casting is very close to the frame mounting
       holes in  some locations.   Mounting screw lengths must be
       chosen such that no more than 0.125 inches of the screw is
       available to  enter the  frame mounting  hole.  The torque
       applied to  the mounting screws should be between 9 and 12
       inch-pounds.


                                

                           Figure 71
         Mechanical Outline and Mounting Hole Locations



7.3  PHYSICAL DIMENSIONS

       Overall height,  width, and  depth, along  with other  key
       dimensions, are  shown in  Figure 71,  Mechanical Outline
       and Mounting  Hole Locations,  and Figure  72, Mechanical
       Outline, Bottom and Side Views.


                                

                           Figure 72
            Mechanical Outline, Bottom and Side Views



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7.4  SHIPPING REQUIREMENTS

       At power down, the heads are automatically positioned over
       the nondata,  dedicated landing zone on each disk surface.
       The automatic  shipping lock  solenoid is  also engaged at
       this time.


7.5  REMOVABLE FACEPLATE

       The faceplate may be removed in installations that require
       it.   Remove the two E-clips and unplug the LED cable from
       the PCB.  See Figure 73, Removable Faceplate.


                                

                           Figure 73
                       Removable Faceplate






































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8.0  PCB JUMPER OPTIONS


8.1  DRIVE ADDRESS SELECTION JUMPER

       In  multidrive   configurations,  it  is  necessary  to
       configure each  drive with a unique address.  A maximum
       of seven  drives is permitted per host controller.  The
       address for  the drive  is determined by installing the
       jumper plug  in the appropriate jumper location.  Table
       81, Drive  Select Jumpers,  shows the  drive selection
       jumpers.   As shipped  from the factory, the DS1 jumper
       is  installed.     Removing   the  jumper  entirely  is
       equivalent to a "no select."  See Figures 81, 82, and
       83,   Drive Jumper  Options, and  Tables 84, 85, and
       86, Jumper Selections.


                               

                          Table 81
                     Drive Select Jumpers



                               

                          Figure 81
        Drive Jumper Options (PCB Part Number 1014150)



                               

                          Figure 82
        Drive Jumper Options (PCB Part Number 1015468)



                               

                          Figure 83
        Drive Jumper Options (PCB Part Number 1014520)



                               

                          Table 82
                Drive Model Selection Jumpers







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                          Table 83
               JP37 and JP39 Jumper Selections



                               

                          Table 84
         Jumper Selections (PCB Part Number 1014150)



                               

                          Table 85
         Jumper Selections (PCB Part Number 1015468)



                               

                          Table 86
         Jumper Selections (PCB Part Number 1014520)



8.2  READ GATE DELAY JUMPERS

       Jumpers JP7  and JP8  have been  provided  to  allow  a
       specified delay  to be set on the read gate received by
       the controller.   As  shipped  by  the  factory,  these
       jumpers are  configured for  zero delay.  See Table 87
       below for reference.


                               

                          Table 87
               Read Gate Delay Jumper Settings



8.3  WRITE PROTECT SELECTION JUMPER (JP14)

       Jumper JP14  is the  write project  jumper.   When  the
       jumper is  present  (installed),  the  drive  is  write
       protected and  can only  be read;  no writing  can take
       place.   As shipped  from the  factory, jumper  JP14 is
       removed.






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8.4  SEQUENTIAL SPINDLE MOTOR SPINUP JUMPER (JP6)

       The spindle  motor spinup  jumper (JP6) allows a string
       of drives to be started sequentially by the controller.
       When the  jumper  is  present  (installed),  the  drive
       automatically spins up as soon as power is applied.  If
       JP6 is  removed, the  drive is  started by  issuing the
       appropriate command  from the  controller.   As shipped
       from the factory, jumper JP6 is installed.


8.5  TEST JUMPERS (JP1-JP3)

       These jumpers  provide access  to certain test signals.
       The specific  signals and  the normal  factory settings
       are shown below in Table 88, Test Pin Jumpers.


                               

                          Table 88
                       Test Pin Jumpers



8.6  HARD SECTOR CONFIGURATION JUMPERS (JP16-JP29)

       Jumper JP31 selects the mode of operation.  Jumper JP31
       installed configures  the drive as a soft sector drive;
       removed, it  configures the  drive as  a hard  sectored
       drive.

       Jumpers JP16  through JP29  allow the user to configure
       the drive's  hard sector  size.   The sector  size  can
       range from  a minimum  of 123  to a  maximum of  31,410
       unformatted bytes per sector, with 1 byte granularity.

       The hard  sector configuration jumpers are encoded in a
       binary fashion,  with JP16  being the least significant
       byte and  JP29 being  the most  significant byte.    An
       installed jumper  selects the  binary value.  See Table
       89, Customer Selectable Jumpers.

       Jumper JP30,  if installed,  enables setting  the  hard
       sector size  over the  ESDI.  The drive must be in hard
       sector mode, that is, JP 31 removed.


                               

                          Table 89
                 Customer Selectable Jumpers





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9.0  MEDIUM DEFECTS AND ERRORS

       Defects on  the medium surface are identified on both a
       paper defect  map and a defect map written on the drive
       according to  the ESDI format rules.  These defect maps
       indicate the  head number,  track number, and number of
       bytes from index, for each defect.

       The maximum  number of  encoded (NRZ) defects per drive
       is 200 for the XT-8380E, and 300 for the XT-8760E.  The
       maximum number  of defects  per surface  cannot  exceed
       100.    See  Table  91,  Maximum  Number  of  Defects.
       Cylinder zero  is certified  to be  defect-free.    The
       maximum number  of multiple  defect tracks  is  15  per
       drive.


                               

                          Table 91
                  Maximum Number of Defects


       As shipped,  the drive  contains three  copies  of  the
       defect map,  written  in  different  locations  on  the
       disks.

       One complete  defect list  resides on  sector  zero  of
       cylinder 1,631.  Identical copies are located on sector
       zero of  cylinder 1,623  and sector  zero  of  cylinder
       1,632.   This allows  for redundancy  should  an  error
       occur on  cylinder 1,631.   Sector  zero of any surface
       contains the  defects for that surface.  The format for
       the data  field portion  of this  sector is  512 bytes,
       with 2  bytes of  cyclic redundancy  check (CRC) (x16 +
       x12 + x5 + 1).  See Figure 91, Defect List Format.


                               

                          Figure 91
                      Defect List Format


       Defect locations are identified by fields 5 bytes long.
       Other byte  definitions are  shown in Figure 91.  Byte
       count is the number of bytes from INDEX.

       The location of the start of the actual defect may vary
       from the location specified on the defect list by up to
       10 bytes.






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       The  end  of  the  defect  list  for  each  surface  is
       indicated by  5 bytes  of ones  in the  defect location
       field, or the end of the sector.

       The CRC  check bytes should be used, if that capability
       exists, but may be ignored if multiple reads are a more
       desirable approach.

       READ GATE  can  be  asserted  between  bytes  five  and
       twenty-five, from  INDEX, to read the header for drives
       reporting   14-byte    PLO   synchronization    fields.
       Likewise, for drives reporting 24-byte PLO fields, READ
       GATE can  be asserted  between bytes  five and  twenty.
       For the  data field  it is not necessary to toggle READ
       GATE to  reacquire the  clock.  If it is, however, READ
       GATE can  be asserted  between bytes  zero  and  seven,
       after receiving  the CRC  bytes on  NRZ READ  DATA, for
       drives reporting  14-byte PLO  synchronization  fields.
       Likewise,   for    drives   reporting    24-byte    PLO
       synchronization  fields,  READ  GATE  may  be  asserted
       between bytes zero and two from the CRC bytes.




































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APPENDIX:  UNITS OF MEASURE
          Abbreviation   Meaning
          

          A/m  amps per meter
          AWG  average wire gauge
          bpi  bits per inch
          fci  flux changes per inch
          g    gram
          Gbyte     gigabyte
          Hz   hertz
          mA   milliamp
          A   microamp
          Mbit megabit
          Mbyte     megabyte
          m   micrometer
          msec millisecond
          sec microsecond
          nsec nanosecond
          Oe   oersted
          RH   relative humidity
          rpm  revolutions per minute
          tpi  tracks per inch
          xxB  binary values
          xxh  hexadecimal values
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GLOSSARY

       3rdPty.  Third party

       ack.  Acknowledge

       ADR.  Address

       ANSC.  American National Standards Committee

       ANSI.  American National Standards Institute

       arbitration winner.  The arbitrating SCSI device which has
          the highest SCSI address.

       assert.  A signal driven to the true state.

       async.  Asynchronous

       BCV.  Buffer control valid

       bit.  Binary digit

       byte.  Eight consecutive binary digits

       C/C.  Continuous/composite (format)

       CCS.  Common Command Set

       CDB.   Command descriptor  block, the  structure  used  to
          communicate requests from an initiator to a target.

       cmd.  Command

       connect.   The function  that  occurs  when  an  initiator
          selects a target to start an operation.

       CRC.  Cyclic redundancy check

       CSA.  Canadian Standards Association

       dBA.  Decibel, audible

       DC.  Direct current

       DCR.  Disabled correction (signal)

       disconnect.   The  function  that  occurs  when  a  target
          releases control  of the  SCSI bus allowing it to go to
          the BUS FREE phase.

       DMA.  Direct memory access

       DTE.  Disable transfer on error



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       EBP.  Erase bypass

       ECC.  Error correction code

       ECL.  Emitter-coupled logic

       EDAC.  Error detection and correction

       EEC.  Enable early connection

       EIA.  Electrical Industry Association

       ENDEC.  Encoder/decoder

       ERA.  Erase all

       ESDI.  Enhanced Small Device Interface

       FCC.  Federal Communication Commission

       firmware.   Computer programs  encoded permanently  into a
          ROM

       FW.  Firmware

       G.  Constant of gravitation

       gnd.  Ground

       HDA.  Head disk assembly

       HW.  Hardware

       I/O.  Input and/or output

       initiator.   A SCSI  device, usually  a host  system, that
          requests that an operation be performed by another SCSI
          device.

       intermediate status.   A status code sent from a target to
          an initiator  upon completion  of each command in a set
          of linked  commands, except for the last command in the
          set.

       ISG.  Inter-sector gap

       ISO.  International Standardization Organization

       LBA.  Logical block address

       LED.  Light-emitting diode






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       logical thread.   The logical path which exists between an
          initiator's memory  and a  bus device  LUN, even though
          the physical path may be disconnected.

       logical unit.   A  physical or  virtual device addressable
          through a target.

       LSB.  Least significant byte

       LUN.  Logical unit number, an encoded 3-bit identifier for
          the logical unit.

       MFM.  Modified frequency modulation (encoding)

       MO.  Magneto optics

       MSB.  Most significant byte

       MTBF.  Mean time between failures

       MTTR.  Mean time to repair

       MZCAV.  Maxtor Zoned Constant Angular Velocity (format)

       N.C.  No connection

       negate.  A signal driven to the false state

       nom.  Nominal

       OEM.  Original equipment manufacturer

       one.  True signal value

       P-P.  Peak to peak

       P/N.  Part number

       parity.   A method  of checking  the  accuracy  of  binary
          numbers

       PC.  Polycarbonate

       PCB.  Printed circuit board

       PCF.  Page control field

       peripheral device.  A peripheral that can be attached to a
          SCSI device

       PLL.  Phase-locked loop

       PLO.  Phase-locked oscillator




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       PM.  Preventive maintenance

       PMI.  Partial medium indicator

       POH.  Power On hours

       PTRN.  Pattern

       R/W.  Read and/or write

       RAM.  Random-access memory

       reconnect.  The function that occurs when a target selects
          an initiator to continue an operation after disconnect.

       req.  Request

       reserved.   Bits, bytes,  fields and  code values that are
          set aside for future standardization.

       RLL.  Run-length limited

       ROM.  Read-only memory

       SCSI.  Small Computer Systems Interface

       status.   One byte of information sent from a target to an
          initiator upon completion of each command.

       STD.  Standard

       SW.  Software

       sync.  Synchronization, synchronous

       Tahiti Family  disk drive.  Family of magneto optical disk
          drive

       target.     A  SCSI  device  that  performs  an  operation
          requested by an initiator.

       tbd.   To be  determined.  Values which are not defined as
          of the date this manual is published.

       TLA.  Top level assembly

       TTL.  Transistor-transistor logic

       typ.  Typical

       UL.  Underwriter's Laboratories, Inc.

       UNC.  United Core Thread, "C" Category




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       VDE.  Verband Deutscher Electrotechniker

       vendor unique.   The bits, fields, or code values that are
          vendor specific.

       WORM.  Write once read multiple

       zero.  False signal code

       C.  Microcomputer















































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