












                           XT-4000E

                    Product Specification
                   and OEM Technical Manual























Document 1011004
Revision C
January 1990



                       REVISION RECORD



          Revision  Date Published    Revised Contents



          01        February 1987     Preliminary Issue



          A         July 1987         General Changes



          B         September 1988    General Changes



          C         January 1990      General Changes




                   Document Number: 1011004

                           WARRANTY

Maxtor warrants  the XT-4000E  Family of  disk drives  against
defects in  materials and  workmanship for  a period of twelve
months, for  the original  purchaser.   Direct  any  questions
regarding the  warranty to  your Maxtor  Sales Representative.
Maxtor  maintains   Customer  Service   Centers  for  the  re-
pair/reconditioning  of  all  Maxtor  products.    Direct  all
requests for  repair to the Maxtor Service Center in San Jose.
This assures you of the fastest possible service.

                     REGULATORY APPROVALS

          UL Recognition obtained: File Number E87276
          CSA Certification obtained:   File Number LR54048
          VDE Recognition obtained:     Registration    Number
37230G
Address comments concerning this manual to:
Maxtor Corporation
Technical Publications
211 River Oaks Parkway
San Jose, California 95134-1913
Telephone:  (408) 432-1700
Telex:  171074
FAX:  (408) 434-6469










Technical Data Restrictions

In case  of sale  to or use of units by DoD:  Use, duplication
or  disclosure   of  any   software,   firmware   or   related
documentation is  subject to  restrictions stated in paragraph
(c) (1)  (ii) of  the Rights  in Technical  Data and  Computer
Software clause  at DFAR 252.227-7013.  For Civilian Agencies:
Use, reproduction,  or disclosure  of the software and related
documentation is  subject to  restrictions set  forth  in  FAR
52.227-19.   Unpublished rights  reserved under  the copyright
laws of the United States.  Maxtor Corporation, 211 River Oaks
Parkway, San Jose, CA 95134.










Copyright Notice

This manual  and all material contained in it are copyrighted.
The manual may not be copied, in whole or in part, without the
written consent  of Maxtor  Corporation.  The contents of this
manual may be revised without prior notice.

  Copyright 1989 by Maxtor Corporation, San Jose, California,
USA.  All rights reserved
                               


       

PREFACE
Maxtor reserves  the right to make changes and/or improvements
to  its   products  without   incurring  any   obligation   to
incorporate such  changes or  improvements in units previously
sold or shipped.

Maxtor publishes descriptive Brochures and Data Sheets, an OEM
Manual, and a Quick Reference Guide for each product line.  In
addition, important  changes to  a product are conveyed in the
form of  a Technical Bulletin sent to all product customers of
record.   Changes that  affect the  content of  any manual are
covered by  publishing addendum  or revisions  to the affected
manual.


REFERENCE NUMBERS

For information concerning drive set-up and operation, contact
Maxtor Technical Support at (408)432-4893.

For  information  regarding  PC  AT/XT  applications,  contact
Storage Dimensions  Inc. (SDI)  Technical Support at (408)395-
2688, extensions 278-281.
    XT-4000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS

    XT-4000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS


PREFACE.....................................................V


REFERENCE NUMBERS...........................................V


1.0..............................................INTRODUCTION   
    1

  1.1.....................................General Description   
      1
  1.2 ....................................Disk Drive Features   
      2

2.0....................................PRODUCT SPECIFICATIONS   
    3

  2.1..............................Performance Specifications   
      3
  2.2...............................Functional Specifications   
      3
  2.3 ...................................Environmental Limits   
      4
  2.4.....................................Physical Dimensions   
      5
  2.5..............................Reliability Specifications   
      5
  2.6.............................................Error Rates   
      5
  2.7...................................DC Power Requirements   
      6
  2.8...............................Standards and Regulations   
      7

3.0................................FUNCTIONAL CHARACTERISTICS   
    9

  3.1......................Read/Write and Control Electronics   
      9
  3.2.........................................Drive Mechanism   
      10
  3.3...................................Air Filtration System   
      10
  3.4...................................Positioning Mechanism   
      11




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    XT-4000E Product Specification & OEM Technical Manual


                      TABLE OF CONTENTS

  3.5..............................Read/Write Heads and Disks   
      12

4.0.......................................THEORY OF OPERATION   
    15

  4.1...................................Spindle Motor Control   
      16
     4.1.1.............................Hardware Configuration   
          17
     4.1.2.........................Spindle Modes of Operation   
          18
  4.2........................................Actuator Control   
      21
     4.2.1......................................Servo Pattern   
          21
     4.2.2..................................Block Description   
          22
       A........................Read Amplifier/Pulse Detector   
          24
       B..............................Phase-Locked Oscillator   
          25
       C....Synchronization Detector and Servo Data Separator   
          25
       D...............................Data and Index Decoder   
          25
       E..................................Hard Sector Control   
          26
       F.........................Position Demodulator Control   
          26
       G..............................Main Servo Control Loop   
          26
       H............................Microprocessor Controller   
          27
       I..............................................Jumpers   
          27
  4.3......................................Read/Write Channel   
      28
     4.3.1.........................HDA Flex Circuit Interface   
          28
       A......................Preamplifier Integrated Circuit   
          28
       B................................................Power   
          28
       C.......................................Head Selection   
          28
       D..........................................Read Signal   
          32
       E..........................WRITE Mode and Write Unsafe   
          32





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                      TABLE OF CONTENTS

     4.3.2.....................................Pulse Detector   
          32
       A.......................Signal Amplification Using AGC   
          33
       B.....................................Signal Filtering   
          33
       C...................Pulse Qualification/Peak Detection   
          33
       D...............Write-to-Read and Head Switch Recovery   
          35
     4.3.3........................Clock Recovery and Decoding   
          36
       A.......................................Data Separator   
          37
       B.....................................ENDEC, READ Mode   
          38
     4.3.4............................Write Path and Encoding   
          38
       A....................................Soft Sector WRITE   
          39
       B....................................Hard Sector WRITE   
          39
       C........................................Encoding Data   
          40
       D.......................................Encoding Rules   
          40
     4.3.5.............................Address Mark Detection   
          41

5.0......................................FUNCTIONAL OPERATION   
    43

  5.1.......................................Power Up Sequence   
      43
  5.2 ...................................Disk Drive Selection   
      44
  5.3..................................Disk Drive Termination   
      45

6.0......................................ELECTRICAL INTERFACE   
    47

  6.1.....................................Control Input Lines   
      54
     6.1.1.....................HEAD SELECT 2 0, 21, 22, and 23   
          55
     6.1.2 ........................................WRITE GATE   
          55
     6.1.3..........................................READ GATE   
          59





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                      TABLE OF CONTENTS

     6.1.4.......................................COMMAND DATA   
          59
     6.1.5.......................................TRANSFER REQ   
          64
     6.1.6................................ADDRESS MARK ENABLE   
          65
       A................................Soft Sector Mode Only   
          65
       B...........................Hard and Soft Sector Modes   
          66
  6.2 ...................................Control Output Lines   
      66
     6.2.1.....................................DRIVE SELECTED   
          67
     6.2.2..............................................READY   
          67
     6.2.3.................................CONFIG-STATUS DATA   
          67
     6.2.4.......................................TRANSFER ACK   
          73
     6.2.5..........................................ATTENTION   
          73
     6.2.6..............................................INDEX   
          74
     6.2.7...................ADDRESS MARK FOUND (Soft Sector)   
          74
     6.2.8..........................SECTOR MARK (Hard Sector)   
          75
     6.2.9...................................COMMAND COMPLETE   
          76
  6.3..................Spindle Synchronization Control Option   
      76
  6.4.....................................Data Transfer Lines   
      77
     6.4.1......................................NRZ READ DATA   
          78
     6.4.2.....................................NRZ WRITE DATA   
          78
     6.4.3...............................READ/REFERENCE CLOCK   
          80
     6.4.4........................................WRITE CLOCK   
          80

7.0........................................PHYSICAL INTERFACE   
    81

  7.1.........................................J1/P1 Connector   
      82
  7.2.........................................J2/P2 Connector   
      83





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                      TABLE OF CONTENTS

  7.3.........................................J3/P3 Connector   
      84
  7.4............................J4/P4 Frame Ground Connector   
      85
  7.5...............................J6/P6 Auxiliary Connector   
      85

8.0........................................PCB JUMPER OPTIONS   
    87

  8.1.....................Disk Drive Address Selection Jumper   
      87
  8.2.................Data Head Selection Jumpers (JP32-JP36)   
      89
  8.3...................Write Protect Selection Jumper (JP14)   
      90
  8.4.Option for Sequential Spindle Motor Spinup Jumper (JP6)   
      90
  8.5..........................Test Jumpers (JP1, JP41, JP42)   
      90
  8.6.............Hard Sector Configuration Jumpers (JP16-29)   
      91

9.0...................................DISK DRIVE INSTALLATION   
    93

  9.1....................................Mounting Orientation   
      93
  9.2..........................................Mounting Holes   
      93
  9.3...................................Shipping Requirements   
      96
  9.4.....................................Removable Faceplate   
      96

APPENDIX A:  MEDIUM DEFECTS AND ERRORS.....................99


APPENDIX B:  UNITS OF MEASURE.............................101


GLOSSARY..................................................103













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                           FIGURES

    XT-4000E Product Specification & OEM Technical Manual


                           FIGURES

Figure 21.............Typical 12 Volt Current Power Up Cycle   
7
Figure 31..............................Air Filtration System   
11
Figure 32............................Head Positioning System   
12
Figure 41..............................General Block Diagram   
16
Figure 42...........................Spindle Control Hardware   
17
Figure 43.........................Spindle Control Flow Chart   
18
Figure 44...............Servo Pattern and Read-Back Signal I   
22
Figure 45.......................................Servo System   
23
Figure 46............................Main Servo Control Loop   
24
Figure 47...........................Head and Drive Selection   
29
Figure 48...Preamplifier Head Selection and Read-Back Signal   
30
Figure 49.................................Head Selection Map   
31
Figure 410....................................Peak Detection   
34
Figure 411....................................Pulse Detector   
36
Figure 412....................ENDEC/Data Separator READ Mode   
37
Figure 413........................................Write Path   
39
Figure 51................Power Up Sequence (Jumper JP6 Open)   
43
Figure 52...............................Drive Select Circuit   
44
Figure 61........................Control Cable J1/P1 Signals   
48
Figure 62...........................Data Cable J2/P2 Signals   
50
Figure 63Typical Auxiliary Cable and Spindle Synchronization
Connection.................................................52
Figure 64......................Typical Multidrive Connection   
54
Figure 65.......Control Signals, Driver/Receiver Combination   
55

    XT-4000E Product Specification & OEM Technical Manual


                           FIGURES

Figure 66..........Soft Sector Address Mark, WRITE GATE, PLO
Synchronous Format Timing..................................56
Figure 67.....Hard Sector WRITE GATE, PLO Synchronous Format
Timing, Using ADDRESS MARK ENABLE............................   
57
Figure 68.............................WRITE GATE Termination   
58
Figure 69.....Hard Sector WRITE GATE, PLO Synchronous Format
Timing  58
Figure 610..................One Bit Transfer Timing-To Drive   
61
Figure 611.......................COMMAND DATA Word Structure   
61
Figure 612................One Bit Transfer Timing-From Drive   
65
Figure 613.........................Write Address Mark Timing   
66
Figure 614.................CONFIG-STATUS DATA Word Structure   
67
Figure 615.......................Typical Serial Operation(s)   
68
Figure 616......................................INDEX Timing   
74
Figure 617............Read Address Mark Timing (Hard Sector)   
75
Figure 618.................Sector Pulse Timing (Hard Sector)   
76
Figure 619.............Data Line Driver/Receiver Combination   
77
Figure 620.......................NRZ READ/WRITE DATA Timings   
79
Figure 71..............Interface Connector Physical Location   
82
Figure 72............................J1 Connector Dimensions   
83
Figure 73............................J2 Connector Dimensions   
84
Figure 74...............J3 Connector (Drive PCB Solder Side)   
84
Figure 81..........................Disk Drive Jumper Options   
88
Figure 91.....Mechanical Outline and Mounting Hole Locations   
94
Figure 92..........Mechanical Outline, Bottom and Side Views   
95
Figure 93................................Removable Faceplate   
97
Figure A1.................................Defect List Format   
100

    XT-4000E Product Specification & OEM Technical Manual



                            TABLES

    XT-4000E Product Specification & OEM Technical Manual



                            TABLES

                               
Table 21..........................Performance Specifications   
3
Table 22...........................Functional Specifications   
4
Table 23................................Environmental Limits   
4
Table 24.................................Physical Dimensions   
5
Table 25..........................Reliability Specifications   
5
Table 26.........................................Error Rates   
6
Table 27...............................DC Power Requirements   
6
Table 51..............................Drive Selection Matrix   
45
Table 61.................Control Cable J1/P1 Pin Assignments   
49
Table 62....................Data Cable J2/P2 Pin Assignments   
51
Table 63................Auxiliary Cable (J6) Pin Assignments   
53
Table 64.............................COMMAND DATA Definition   
60
Table 65........................REQUEST STATUS Modifier Bits   
62
Table 66.................REQUEST CONFIGURATION Modifier Bits   
63
Table 67.......................CONTROL Command Modifier Bits   
63
Table 68..................TRACK OFFSET Command Modifier Bits   
64
Table 69.......................Standard Status Response Bits   
69
Table 610.................Vendor Unique Status Response Bits   
70
Table 611.......................................Motor Status   
71
Table 612........................SEEK Calibration Error Code   
71
Table 613................General Configuration Response Bits   
72

    XT-4000E Product Specification & OEM Technical Manual



                            TABLES

                               
Table 614...............Specific Configuration Response Bits   
73
Table 71...................Power Connector (J3) Requirements   
85
Table 72...........J6 Auxiliary Signal Cable Pin Assignments   
86
Table 81...........................Disk Drive Select Jumpers   
87
Table 82...................................Jumper Selections   
89
Table 83..................Data Head Number Selection Jumpers   
90
Table 84....................................Test Pin Jumpers   
91
Table 85.........................Customer Selectable Jumpers   
92
Table A1...........................Maximum Number of Defects   
99

    XT-4000E Product Specification & OEM Technical Manual
    XT-4000E Product Specification & OEM Technical Manual

       

    XT-4000E Product Specification & OEM Technical Manual


1.0  INTRODUCTION


1.1  GENERAL DESCRIPTION

       The XT-4000E  Family disk  drives are  high  capacity,
       high performance  random access  storage devices  using
       from five  to eight  nonremovable  51/4-inch  disks  as
       storage media.   Each disk surface employs one moveable
       head to  access 1,224  data  tracks.    The  total  un-
       formatted capacity of the disk drive ranges from 179 to
       385 megabytes.

       The disk  drive incorporates  the Enhanced Small Device
       Interface (ESDI)  high performance  51/4-inch standard.
       Among the  resultant benefits  are  a  10  megabit  per
       second  transfer   rate,   status   and   configuration
       reporting across  the interface,  and nonreturn to zero
       (NRZ) data transfer.

       Low cost  and high performance are achieved through the
       use of  a rotary  voice coil actuator and a closed loop
       servo system  using a  dedicated servo  surface.    The
       innovative MAXTORQ rotary voice coil actuator provides
       an average access time of 16 milliseconds, typical, for
       the eight-disk model (14 milliseconds, typical, for the
       five-disk model).   Track-to-track  access time  is 2.5
       milliseconds for all models.  This level of performance
       is usually  achieved only  with larger, higher powered,
       linear actuators.   The  closed loop  servo system  and
       dedicated servo  surface combine  to allow state of the
       art recording  densities (1,070  tracks per  inch,  and
       14,043 flux changes per inch) in a 51/4-inch package.

       High  capacity   is   achieved   through   a   balanced
       combination of high areal recording density, run-length
       limited  (RLL)   data  encoding  techniques,  and  high
       density  packaging   techniques.     Maxtor's  advanced
       MAXPAK electronic  packaging  techniques  use  surface
       mount devices  to allow all electronic circuitry to fit
       on one  printed circuit  board (PCB).    Advanced  3380
       Whitney-type flexures  allow closer  spacing of  disks,
       and therefore allow a higher number of disks in a 51/4-
       inch package.   Maxtor's  unique integrated  disk drive
       motor/spindle design allows a deeper head/disk assembly
       (HDA)   casting   than   conventional   designs,   thus
       permitting more disks to be used.

       The  electrical   interface  is   compatible  with  the
       industry standards  established by  the ESDI committee.
       The same  basic disk drive/HDA is also available with a
       Small Computer System Interface (SCSI).  The disk drive

    XT-4000E Product Specification & OEM Technical Manual


       size and  mounting conform  to  the  industry  standard
       51/4-inch floppy  and Winchester  disk drives,  and the
       disk drive  uses the  same direct current (DC) voltages
       and connectors.  No AC power is required.


1.2  DISK DRIVE FEATURES

       The key features of the disk drive are as follows:

         storage capacity of 179 to 385 megabytes unformatted
         same physical  size and  mounting as standard floppy
       disk drives
         same control and data cabling as ST506/412 interface
       drives
         same DC voltages as standard floppy disk drives
         no AC voltage required
         rotary voice  coil actuator  and closed  loop  servo
          system for fast, accurate head positioning
         microprocessor-controlled  servo   for  fast  access
         time, high  reliability, and  high density functional
         packaging
         10.0 megabit per second transfer rate
         ESDI interface
         track capacity of 20,940 bytes, unformatted
         thin film  metallic media for higher bit density and
       resolution plus improved durability
         single PCB for improved reliability
         automatic actuator lock
         brushless DC spindle motor inside disk hub
         microprocessor-controlled    spindle    motor    for
         precision  speed   control  (0.1%)  under  all  load
         conditions
         dynamic braking during power down cycle
         user selectable hard or soft sectors
         synchronization of  spindle motors for parallel data
       transfer of multiple drives

    XT-4000E Product Specification & OEM Technical Manual




      XT-4000E Product Specification & OEM Technical Manual
      XT-4000E Product Specification & OEM Technical Manual

       

      XT-4000E Product Specification & OEM Technical Manual


2.0  PRODUCT SPECIFICATIONS

       This section  lists all  specifications for  the  XT-4000E
       Family disk drives.


2.1  PERFORMANCE SPECIFICATIONS

       Table   21,   Performance   Specifications,   lists   the
       performance specifications for the disk drive.


                                

                            Table 21
                   Performance Specifications



2.2  FUNCTIONAL SPECIFICATIONS

       Table 22, Functional Specifications, lists the functional
       specifications for the disk drive.


                                

                            Table 22
                    Functional Specifications



2.3  ENVIRONMENTAL LIMITS

       Table 23,  Environmental Limits,  lists the environmental
       limits of the disk drive.


                                

                            Table 23
                      Environmental Limits



2.4  PHYSICAL DIMENSIONS

       Table  24,   Physical  Dimensions,   lists  the  physical
       dimensions of the disk drive.

      XT-4000E Product Specification & OEM Technical Manual


                                

                            Table 24
                       Physical Dimensions



2.5  RELIABILITY SPECIFICATIONS

       Table   25,   Reliability   Specifications,   lists   the
       reliability specifications for the disk drive.


                                

                            Table 25
                   Reliability Specifications



2.6  ERROR RATES

       Table   26,   Error   Rates,   lists   the   error   rate
       specifications for the disk drive.


                                

                            Table 26
                           Error Rates



2.7  DC POWER REQUIREMENTS

       Table 27,  DC Power  Requirements,  lists  the  DC  power
       requirements of the disk drive.


                                

                            Table 27
                      DC Power Requirements



                                

                           Figure 21
             Typical 12 Volt Current Power Up Cycle

      XT-4000E Product Specification & OEM Technical Manual


2.8  STANDARDS AND REGULATIONS

       The  Maxtor   XT-4000E  Family  disk  drives  satisfy  the
       following standards and regulations:

       UNDERWRITERS LABORATORIES  (UL) = United States safety; UL
       478, Standard  for Safety, Electronic Processing Units and
       Systems.

       CANADIAN STANDARDS  ASSOCIATION (CSA)  = Canadian  safety;
       CSA  C22.2  No.  220,  1986,  Information  Processing  and
       Business Equipment (Consumer and Commercial Products).

       VERBAND DEUTSCHER  ELECTROTECHNIKER (VDE) = German safety;
       VDE 0806/8.81,  Safety of  Office Appliances  and Business
       Equipment.

       INTERNATIONAL   ELECTROTECHNICAL    COMMISSION   (IEC)   =
       International safety  commission; IEC  950 (formerly 380),
       Safety of Information Technology Equipment.

       FEDERAL COMMUNICATIONS  COMMISSION (FCC)  = United  States
       radiation emissions;  Part 15, Subpart J, Class B Consumer
       Computing Devices.

       CAUTION:     Connections between  equipment must  be  made
       with shielded  cables, and  a shielded  power cord must me
       used to connect AC power to the unit.

       CAUTION:     This  equipment   generates  and  uses  radio
       frequency energy,  and may cause interference to radio and
       television reception  if not  installed and used in strict
       accordance with the instructions in this manual.

       The disk  drive has  been tested  and found to comply with
       the limits  for a  Class B computing device, in accordance
       with the  specifications in  Subpart J  of Part  15 of FCC
       Rules, which are designed to provide reasonable protection
       against radio  and television  reception interference in a
       residential installation.   However, there is no guarantee
       that  interference   will  not   occur  in   a  particular
       installation.   If this  equipment does cause interference
       to radio  or television reception, which can be determined
       by  turning   the  equipment  off  and  on,  the  user  is
       encouraged to try to correct the interference using one or
       more of the following measures:

         reorient the receiving antenna
         reorient the computer with respect to the receiver
         move the computer away from the receiver
         plug the  computer into a different outlet, so that the
         computer and receiver are on different branch circuits

      XT-4000E Product Specification & OEM Technical Manual


       If  necessary,   consult  the  dealer,  or  an  experience
       radio/television technician,  for additional  suggestions.
       You may  find the  FCC booklet How to Identify and Resolve
       Radio TV  Interference Problems  helpful.  This booklet is
       available  from  the  United  States  Government  Printing
       Office, Washington,  D.C., 20402,  stock  number  004-000-
       00345-4.

       Maxtor is  not responsible  for any  radio  or  television
       interference caused  by unauthorized  modifications to the
       disk drive.   It  is the  responsibility of  the  user  to
       correct such interference.
      XT-4000E Product Specification & OEM Technical Manual
      XT-4000E Product Specification & OEM Technical Manual

       
























































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      XT-4000E Product Specification & OEM Technical Manual


3.0  FUNCTIONAL CHARACTERISTICS

       The XT-4000E  Family disk drive consists of read/write and
       control electronics,  read/write heads,  a servo  head,  a
       head positioning  actuator, media,  and an  air filtration
       system.  The components perform the following functions:

         interpret and generate control signals
         position the heads over the desired track
         read and write data
         provide a contamination-free environment


3.1  READ/WRITE AND CONTROL ELECTRONICS

       Drive electronics  are packaged  on a  single PCB.    This
       board, which  includes two  microprocessors, performs  the
       following functions:

         reading/writing of data
         index detection
         head positioning
         head selection
         drive selection
         fault detection
         voice coil actuator drive circuitry
         track zero detection
         recalibration to track zero on power up
         track position counter
         power and speed control for spindle drive motor
         braking for spindle drive motor
         drive up-to-speed indication circuit
         monitoring for write fault conditions
         control of all internal timing
         generation of seek complete signals
         RLL encoding/decoding
         data separation
         address mark detection (soft sector)
         sector detection (hard sector)
         spindle synchronization


3.2  DRIVE MECHANISM

       A brushless  DC drive  motor, contained within the spindle
       hub, rotates  the spindle at 3,600 revolutions per minute.
       The spindle  is direct  driven, with  no belt  or  pulleys
       being used.   Dynamic  braking is used to quickly stop the
       spindle motor  when power  is removed.   The  HDA is shock
       mounted to  minimize transmission of vibration through the
       chassis or frame.






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      XT-4000E Product Specification & OEM Technical Manual


3.3  AIR FILTRATION SYSTEM

       The disks  and read/write  heads are assembled in an ultra
       clean-air environment  and then  sealed within the module.
       The module  contains an  internal absolute filter, mounted
       inside the  casting,  to  provide  constant  internal  air
       filtration (see  Figure 31,  Air Filtration  System).   A
       second filter, located on top of the base casting, permits
       pressure equalization between internal and ambient air.


                                

                           Figure 31
                      Air Filtration System



3.4  POSITIONING MECHANISM

       The read/write  heads are  mounted on a head arm assembly,
       which is  then mounted  to a ball bearing supported shaft.
       The voice coil, an integral part of the head/arm assembly,
       lies inside  the magnet  housing  when  installed  in  the
       drive. Current from the power amplifier, controlled by the
       servo system,  causes a  magnetic field  in the voice coil
       which  either   aids  or  opposes  the  field  around  the
       permanent magnets.  This reaction causes the voice coil to
       move  within  the  magnetic  field.  Since  the  head  arm
       assemblies are  mounted on  the voice coil, the voice coil
       movement is translated through the pivot point directly to
       the  heads,  and  positions  the  head  over  the  desired
       cylinder.  See Figure 32, Head Positioning System.


                                

                           Figure 32
                     Head Positioning System


       Actuator movement  is controlled  by  the  servo  feedback
       signal from  the servo head.  The servo head is located on
       the lower  surface of  the fourth disk from the top, where
       servo information  is prewritten  at the  factory.    This
       servo information  is used  as a  control signal  for  the
       actuator to  provide track-crossing  signals during a seek
       operation,  track-following  signals  during  on  cylinder
       operation, and  timing information,  such as index, sector
       pulses (hard sector), and servo clock.







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3.5  READ/WRITE HEADS AND DISKS

       The  drive   employs  thin  film  heads  and  Whitney-type
       flexures.  This  configuration  of  sliders  and  flexures
       provides   improved    aerodynamic   stability,   superior
       head/disk compliance, and a higher frequency response than
       conventional ferrite heads.

       The medium  uses  thin  metallic  film  deposited  on  130
       millimeter  diameter  aluminum  substrates.  The  metallic
       surface,  together   with  the  low  load  force/low  mass
       Whitney-type  heads,   permit  highly   reliable   contact
       start/stop operation.   The metallic recording film yields
       high  amplitude   signals,  and   very   high   resolution
       performance compared  to conventional  oxide coated media.
       The metallic medium also provides a highly abrasion-resis-
       tant surface,  decreasing the  potential for damage caused
       by shipping shock and vibration.

       Data on  each of  the data  surfaces is  read  by  one  of
       fifteen read/write  heads, each  of which  accesses  1,224
       tracks.     There  is   one  surface  dedicated  to  servo
       information in each drive.


































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4.0  THEORY OF OPERATION

       The drive  PCB assembly  provides four major functions,
       1) spindle  motor  control;  2)  actuator  control  for
       head/positioning; 3)  the read  and write data channel;
       and 4)  ESDI hardware  and protocol implementation.  In
       addition,  power   conditioning   and   monitoring   is
       provided.  Figure 41, General Block Diagram, shows the
       organization  of   these  functions   and   the   major
       subsections of each.  The following paragraphs describe
       each of these in more detail.


                               

                          Figure 41
                    General Block Diagram



4.1  SPINDLE MOTOR CONTROL

       The spindle  motor in  the  drive  uses  a  three-phase
       delta-wound brushless  DC motor located inside the hub.
       Commutation is  determined by three hall effect sensors
       which are  mounted on  a flex  circuit at the bottom of
       the casting.   These  hall effect sensors sense magnets
       under the spindle motor.


4.1.1     Hardware Configuration

       Figure  42,   Spindle  Control  Hardware,  presents  a
       component block  diagram of  the spindle  system.   The
       hardware provides  the functions  described below.  The
       Z8 microcontroller  is  the  central  element  in  this
       diagram, serving to coordinate, direct, and control all
       of the activity of the spindle.


                               

                          Figure 42
                   Spindle Control Hardware


       The output  of the  hall sensors  is mapped  by the  Z8
       microcontroller  into   a   three   phase   commutation
       sequence.   This sequence  continuously commutates  the
       in-the-hub four-pole  three phase  spindle drive  motor
       through the  three phase  H-bridge  power  module  (six
       power transistors).   The  current through the motor is





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       monitored by  the voltage  across  the  0.1  ohm  sense
       resistor.  Current control is obtained by comparing the
       sense voltage  with the  digital analog converter (DAC)
       output at  a high  gain op-amp,  and then  closing  the
       analog  control   loop  through   the   (lower)   power
       transistors; an integrating capacitor around the op-amp
       stabilizes the loop.  The net effect of this loop is to
       desensitize the  circuit to  variations  in  the  power
       transistor parameters.

       Additional  analog   circuitry  shown  in  Figure  42,
       Spindle Control  Hardware, provides current limiting of
       the  motor  current,  and  provides  graceful  shutdown
       (homing of  the actuator  and dynamic  braking  of  the
       spindle) in  the event  of loss  of power,  or  if  the
       spindle motor is turned off by a STOP command in remote
       mode.


4.1.2     Spindle Modes of Operation

       Figure  43,   Spindle  Control   Flow  Chart,   is   a
       diagrammatic  description   of  the   in-line/real-time
       microcontroller diagnostics  for  the  spindle  control
       system.


                               

                          Figure 43
                  Spindle Control Flow Chart


       The flowchart describes the sequence of microcontroller
       activity required  during each  of the spindle modes of
       operation; this  sequence provides  a detailed overview
       of the  diverse control  and auxiliary functions of the
       spindle.  The sequence, programmed as algorithms in the
       microcontroller,  provides   three   basic   modes   of
       operation for  the drive:   START  mode, RUN  mode, and
       SYNCSP (synchronous spindle) mode.

       START Mode:  At power up with the spindle at rest, full
       current (limited to 4.0 amps) is applied to the spindle
       motor.   Progressive diagnostic  and timing  checks are
       performed to  detect a spindle drive malfunction and to
       take corrective action as follows:

         Detect a Stalled Spindle Motor
          The  hall   sensors  are  tested  for  (commutation)
         motion.  If one second elapses without motion, either






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         a "stuck"  spindle  or  a  power  module  failure  is
         indicated; actuator  dither is invoked to free up the
         spindle, and  STATUS 2  is posted.  At the end of two
         seconds of dither, motion is checked again and if not
         detected, STATUS  2 is  posted and the spindle aborts
         (powers down).

         Detect a Hall Sensor Failure
          The states  of the  hall  sensors  are  continuously
         checked at commutation until velocity lock on.  If an
         illegal state  occurs in two consecutive revolutions,
         STATUS 1 is posted and the spindle aborts.

         Check 1,000 revolutions per minute at 7 Seconds
          The commutation  is timed  for 1,000 revolutions per
         minute  to   occur  within   7  seconds.    If  1,000
         revolutions per  minute do  not occur, this indicates
         excessive drag forces from the head or bearings, or a
         motor/driver failure;  STATUS 3  is  posted  and  the
         spindle aborts.

         Check 3,000 revolutions per minute at 21 Seconds:
          The commutation  is timed  for 3,000 revolutions per
         minute to  occur within  21 seconds.   If above 3,000
         revolutions per  minute, the spindle tries to achieve
         3,600 revolutions  per minute;  in  contrast  to  the
         stalled  spindle  motor  and  1,000  revolutions  per
         minute  in   7  seconds  checks,  a  sufficient  back
         electromotive force  from the  motor has  reduced the
         voltage overhead  across the  drivers  in  the  power
         module such that the reduced power dissipation of the
         drivers allows  multiple retries.   (A  RETRY is per-
         formed beyond  this point  for any  return  into  the
         START mode.)

       RUN Mode:   Upon entering RUN mode, the microcontroller
       sequentially enters  a) an  adaptive routine to compute
       the quiescent  drag force  of the  bearing/disks and to
       compute the  dynamic system constant from the DAC input
       to  motor   velocity;  b)   an  electronic  commutation
       routine; and  c) a  velocity lock-on-routine (in thirty
       revolutions) to  insure (monitored)  velocity operation
       of 3,600  revolutions per  minute 0.1%.  The system is
       then given  a STATUS  0 identification  of normal  mode
       operation.  If a failure occurs at any point between a)
       and c),  the system  goes into  RETRY mode  (into START
       mode) and  is monitored  for five  successive  failures
       without velocity lock-on before ABORT.

       At velocity  lock-on, a  READY signal  is posted to the
       interface microcontroller to signal that the spindle is
       at recording velocity (3,600 revolutions per minute).





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       A feature of the drive is the capability of synchronous
       spindle operation  (spindle locked  operation) in which
       INDEX lock is achieved between a master drive and up to
       forty eight  slave drives.   This feature allows serial
       data streams  to operate  in parallel  and thereby mul-
       tiplies the  system data  transfer rate  (drive-to-host
       computer) by the number of slave drives.

       When the  drive  is  in  RUN  mode,  the  code  of  the
       microcontroller provides  two  simultaneous  functions:
       1) generation  of a  MAPOUT (master  pulse out); and 2)
       search for a MAPIN (master pulse in).  Normal operation
       implies the  lack of  a MAPIN  pulse, and while in this
       mode, the drive defaults to a master drive designation.

       If a  MAPIN pulse is detected, the drive is posted with
       a slave  drive designation  (MAPIN available)  and  the
       drive goes into SYNCSP mode.

       SYNCSP  Mode:     Upon   detection  of   MAPIN  by  the
       microcontroller, the  slave drive  enters a  high-speed
       CAPTURE mode  to bring  the  MAPIN  pulse  to  the  MAP
       (master pulse)  window.   Normal velocity control is in
       effect during this operation (NORMAL mode).

       As MAPIN  approaches the  outer boundaries  of the  MAP
       window, a  velocity adjustment  is made  to  the  slave
       drive to  return the  drive to normal velocity prior to
       entering the  MAP window  and  subsequent  phase  lock.
       Within the  MAP window,  bounds are tested for velocity
       error and  phase error.   When the two are within their
       tolerance  zones,   the  system  switches  to  a  phase
       controlled configuration,  wherein the  slave drive  is
       locked to  the MAPIN  pulse,  and  synchronous  spindle
       operation (spindle locked) STATUS 8 is posted.

       In the  SYNCSP mode,  the velocity  and phase error are
       constantly monitored to assure velocity and INDEX phase
       tolerances as follows:
          velocity:  3,600 revolutions per minute 0.1%
          master INDEX/slave INDEX lock 40 microseconds

       If the  SYNCSP lock  error (MAPERR) is out of tolerance
       (STATUS 10),  the system  reverts to  CAPTURE mode.  If
       the velocity  is  out  of  tolerance  (spindle  control
       lost),   RETRIES   are   performed   via   START   mode
       (recalibration of  the adaptive  loop) and if SYNCSP is
       not  achieved   (with  MAPIN   available),   a   SYNCSP
       inoperative condition  error (STATUS  10) is posted and
       the system attempts operation in NORMAL mode.







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4.2  ACTUATOR CONTROL

       This section describes the servo system used in the XT-
       4000E Family  disk drives.   The  same servo  system is
       used for  both models, with small modifications made to
       accommodate the  different number  of heads  unique  to
       each model.   Two  functions  are  provided,  precision
       track following, and carriage motion to specific tracks
       in response  to interface  commands.  Typical track-to-
       track and  average access times are 14 milliseconds for
       the XT-4170E and 16 milliseconds for the XT-4380E.

       A dedicated  servo surface and quadrature servo pattern
       is used.   This  servo  incorporates  evolutionary  and
       detail improvements  over prior  generations of  Maxtor
       servos.

       The level  of electronics  integration  is  very  high.
       Three custom  analog integrated  circuits, an  actuator
       driver integrated  circuit, and  a standard  cell servo
       logic chip  (SLC), are  used  to  implement  the  servo
       functions.      In   addition,   the   servo   uses   a
       microcontroller,  which   is  shared   with  the  drive
       interfacing function.


4.2.1     Servo Pattern

       The servo  pattern consists  of 3,808  servo frames per
       track with  twenty-two servo clock intervals per frame.
       This yields  a 228 kilohertz frame rate for the system.
       Four  dibit   pulses  encode  the  quadrature  position
       information, and  one pulse  each is  used for synchro-
       nization and  data (see  Figure 44,  Servo Pattern and
       Read-Back Signal  I).   When the data pulse is present,
       the frame  has a  logical "1" value.  When the pulse is
       not present,  the frame  has a logical "0" value.  This
       serial pulse  stream is  decoded in  16-bit words, with
       parity, and  is  used  to  encode  the  absolute  track
       address, index,  and configuration  data  used  by  the
       drive and  the servo.  Thus, the words are repeated 238
       times per  revolution for a word rate of 14.3 kilowords
       per second.   The  synchronization pulse, which follows
       the data  pulse, is  present in every frame and is used
       to synchronize to the servo pattern.  The first pair of
       position pulses,  A and  B, are used for positioning on
       even numbered  data tracks.  The second pair of pulses,
       C and  D, are  used for  positioning  on  odd  numbered
       tracks.








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                          Figure 44
             Servo Pattern and Read-Back Signal I



4.2.2     Block Description

       Refer to Figure 45, Servo System, and Figure 46, Main
       Servo Loop, when reading the following descriptions.


                               

                          Figure 45
                         Servo System



                               

                          Figure 46
                   Main Servo Control Loop



A    READ AMPLIFIER/PULSE DETECTOR

       The  read   amplifier  and   pulse  detector   provides
       automatic gain control (AGC) a buffer amplifier for the
       servo filter and a pulse detector for the dibit pulses.
       The raw  servo signal  from the preamplifier enters the
       read amplifier  and is  applied to  the AGC  amplifier.
       The  AGC   loop  is   closed   through   the   position
       demodulator.  The amplified and normalized servo signal
       then passes  through a  filter for  noise reduction and
       then on to the pulse detector and peak detector.

       The pulse  detector detects  the zero  crossing between
       the positive  and negative  going portions of the dibit
       pulses.  The digital output of this detector is used to
       decode data  pulses and  issued as  the input  for  the
       phase-locked oscillator.  The peak detector samples the
       peak values  of the  position pulses  and establishes a
       reference baseline  from which  to measure  these  peak
       values.   The discharge current of the peak detector is
       switchable to  allow the  use of  a long  time constant
       (peak  hold)   during  servoing,  and  a  shorter  time
       constant which is used to facilitate lock up of the AGC
       loop at power on.






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B    PHASE-LOCKED OSCILLATOR

       The phase-locked oscillator (PLO) harmonically locks to
       the incoming  pulse stream  from  the  pulse  detector.
       During synchronization  the oscillator  locks in  phase
       and frequency  mode to  a reference  clock generated in
       the SLC.   Also,  in the  SLC, the oscillator output is
       divided and  used to  generate the  5 megahertz  master
       clock from  which timing gates are derived.  This clock
       is divided  again to provide the 2.5 megahertz feedback
       clock for  the PLO.   The fundamental oscillator output
       frequency is 20 megahertz.

       Since the  PLO output is synchronized with the physical
       rotation of  the disk  stack, it  is used  as the write
       clock and  as the clock for the sector counter for hard
       sector mode operation.


C    SYNCHRONIZATION DETECTOR AND SERVO DATA SEPARATOR

       The synchronization  detector and  servo data separator
       in  the   SLC  detect   the  data  and  synchronization
       transitions, which  are the  first two dipulses present
       in  each   servo  frame.    The  extracted  synchronous
       transitions are  used  to  create  the  absolute  frame
       reference for  synchronizing the  servo frame  and  for
       decoding servo  position information.    Capability  is
       provided for tolerating servo surface defects which may
       cause missing  synchronization pulses.  The serial data
       stream of data pulse transitions is used to verify lock
       by virtue  of its  limited run  length  of  zeros  when
       proper lock  is in effect.  Parity of the data words is
       also checked.   The  microprocessor constantly monitors
       synchronization and  data and  initiates relocking  the
       PLO and  reinitializing the servo if synchronization is
       lost.


D    DATA AND INDEX DECODER

       The data and index decoder in the SLC is a 16-bit shift
       register whose  contents are read every sixteen frames.
       If all  the frames  are valid  the word is passed on to
       other logic  in the  SLC and then to the microprocessor
       controller.   Index is delineated by a preindex and in-
       dex word  sequence.  Absolute track information is also
       encoded  with   redundancy.      The   absolute   track
       information is  constantly monitored to verify that the
       servo is  positioned on the correct track.  In addition
       to index  and track  coding, the  guard  bands  contain
       configuration data  which is  used to configure a given





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       PCB for  a given HDA.  In this way, the same PCB may be
       used for  a family  of products.    Configuration  data
       includes the  number of  data  tracks  and  heads,  the
       servowriter version and drive capacity, and the dynamic
       constants to be used when seeking.


E    HARD SECTOR CONTROL

       The hard  sector capability of the drive is provided by
       a programmable  counter in  the SLC.   This  counter is
       clocked by  the PLO  and is  synchronized  with  index.
       User defined  jumpers on  the PCB  are used  to set the
       desired number of bytes per sector.  Alternatively, the
       desired number  of bytes  per sector may be set via the
       drive interface.   The  microprocessor either reads the
       jumpers or  receives the interface command, and in turn
       sets the  decode logic for the proper sector size.  The
       sector pulses  are very  accurately timed to data since
       the sector clock is locked to disk rotation.


F    POSITION DEMODULATOR CONTROL

       Timing windows  are created  in the  SLC  to  gate  the
       synchronization pulses, data pulses, and servo position
       dipulses.   The servo master clock derived from the PLO
       divides  each   servo  frame   into  twenty-two   equal
       segments, and  is used  as the reference for generating
       these gates.   A  nominal disk  rotation speed of 3,600
       and  3,808   frames  per  revolution  results  in  a  5
       megahertz servo master clock.

       The synchronization pulse is used to align the gates to
       the   servo   frames.      The   gate   generated   for
       synchronization   is    used   to    verify   lock   to
       synchronization.   If  lock  is  lost,  synchronization
       pulses stop  appearing in  the  proper  synchronization
       window  and  a  relock  process  is  initiated  by  the
       microprocessor.   The gate generated for data pulses is
       used to  decode servo  data.   When  no  transition  is
       detected in  the window,  the frame  has a  logical "0"
       value, and  when a  data transition  does occur  in the
       window, the frame has a logical "1" value.

       The four gates generated for the four position dipulses
       (A, B,  C, and D) are used to switch the peak detectors
       in the  position demodulator  from a tracking mode to a
       hold  mode,   providing  position  information  to  the
       control system.







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G    MAIN SERVO CONTROL LOOP

       The peak-detected  A, B,  C, and D dipulses are used to
       create  the   locking  edges  for  the  position  loop.
       Difference signals  corresponding to A-B, B-A, C-D, and
       D-C are  synthesized  and  used  for  servoing  on  the
       appropriate data tracks.

       With the quadrature pattern, track zero uses A-B, track
       one uses  C-D, track two uses B-A, and track three uses
       D-C.   This pattern  is repeated  every fourth track so
       that tracks  zero, four,  eight, twelve,  etc., use A-B
       for generating the position error signal.

       Digital to  analog converters in the SLC are controlled
       by the  microprocessor.   During  SEEKs,  position  and
       velocity control  trajectories are  calculated  by  the
       microprocessor and  output to  the servo  control loops
       via these  DAC's.   These trajectories  are  calculated
       based on  the configuration data which is read at power
       up.    The  configuration  data  contains  the  dynamic
       constants  which  are  used  in  calculating  the  SEEK
       trajectories.

       During track following, the position error is monitored
       by hardware  to obtain  fast response  to shut down the
       write current  should  an  off  track  condition  occur
       during a write operation.


H    MICROPROCESSOR CONTROLLER

       The servo  microprocessor exercises supervisory control
       over the  servo during track following mode, and active
       control while  seeking.    In  addition  to  the  servo
       function, the microprocessor performs interface control
       functions per ESDI specifications.

       The  various   peripherals,  such   as  the   SLC   and
       configuration  jumpers,   are  memory   mapped.     The
       microprocessor makes  use of  registers inside  the SLC
       for drive  status, control,  seek current  DAC  output,
       position offset  current  DAC  output,  track  address,
       servo data  words, and  peripheral control  via  output
       port pins in the SLC.

       The  microprocessor  also  controls  the  recalibration
       sequence when  power is  first applied  to  the  drive.
       When the  drive is  jumpered  to  enable  starting  and
       stopping the  spindle  motor  via  the  interface,  the
       microprocessor controls  the reset  line to the spindle
       control microprocessor.   The  status  of  the  spindle





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       control  microprocessor   is  monitored  by  the  servo
       microprocessor to determine status and detect any error
       conditions in  the system.   Such status information is
       then available to the host through the drive interface.

       The servo  microprocessor also  controls  the  actuator
       latch and  releases the  actuator when  the spindle  is
       locked to  the proper  speed.   After power  is removed
       from the  drive, or  a spindle stop command is received
       from the  interface, the  actuator  driver  pushes  the
       headstack into  the  landing  zone  and  the  latch  is
       enabled.   This action takes place while the spindle is
       still spinning and before dynamic braking begins.


I    JUMPERS

       Two classes  of servo  jumpers are  used in  the drive.
       The  first   class  includes   factory  jumpers   which
       configure the  PCB to  work properly for the particular
       model of drive on which it is installed.  These jumpers
       program the  number of  heads, the  data transfer rate,
       and the  synchronization field  required  by  the  data
       separator.   The microprocessor reads these jumpers and
       performs accordingly.

       The second  class of  jumpers comprises user selectable
       jumpers.   These jumpers are for setting a hard or soft
       sectored mode  of operation,  selecting the sector size
       in hard  sector mode, enabling or disabling the ability
       to set  the hard  sector size  through the drive inter-
       face, and enabling or disabling automatic spinup.


4.3  READ/WRITE CHANNEL

       The read/write  channel is  described in  the following
       paragraphs.


4.3.1     HDA Flex Circuit Interface

       A  description  of  the  HDA  flex  circuit  interface,
       including the  preamplifier integrated  circuit, power,
       head selection, the READ signal, and the WRITE mode and
       write unsafe, follow.











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A    PREAMPLIFIER INTEGRATED CIRCUIT

       The preamplifier/write  driver that is used on the flex
       circuit is  the SSI  521 integrated circuit.  This is a
       thin  film   head   compatible   circuit   capable   of
       interfacing with  up to six heads.  There are three SSI
       521 chips  used on  the flex  circuit so that a maximum
       number (fifteen) of heads for a drive can be selected.


B    POWER

       Power is  supplied from  the main drive PCB through the
       flex circuit  connector, J4.   The voltage requirements
       are Vcc = +5 volts, Vdd = +12 volts.


C    HEAD SELECTION

       The  head   selection  circuitry  starts  at  the  ESDI
       interface connector,  J1.   There are  four head select
       lines used  at the ESDI interface (Figure 47, Head and
       Drive Selection).

          -Headselect 20
          -Headselect 21
          -Headselect 22
          -Headselect 23


                               

                          Figure 47
                   Head and Drive Selection


       These are  then encoded  by the  SLC  into  three  chip
       select lines  and three head select lines that are used
       by the  flex circuit.   These  lines are  listed  below
       (also, see  Figure 48, Preamplifier Head Selection and
       Read-Back Signal).

          CS0*
          CS1*
          CS2*
          HS0
          HS1
          HS2

       *  Negative true







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                          Figure 48
       Preamplifier Head Selection and Read-Back Signal


       The encoding  for the  heads is  listed in  Figure 49,
       Head Selection  Map.   Also shown is the mapping of the
       heads within the HDA.


                               

                          Figure 49
                      Head Selection Map



D    READ SIGNAL

       The amplified  read-back signal is output from the flex
       on the RDX (read data x) line.  RDY (read data y) lines
       are shown  in Figure  49, Head  Selection  Map.    The
       nominal gain  from the head input, HnX and HnY (where n
       is the head number), of the preamplifier to the RDX and
       RDY outputs is 100.


E    WRITE MODE AND WRITE UNSAFE

       Write data  is sent by the main PCB to the flex circuit
       via the  WDI (write  data input) pin on J4.  A negative
       transition on the WDI line changes the direction of the
       write current in the SSI 521, causing a data transition
       to be  written.   (The SSI 521 integrated circuit has a
       divide-by-two flip-flop  internally in  the write  data
       path).   Write current is selected by three programming
       resistors on the main PCB, one resistor per SSI 521.

       The WUS (write unsafe output) is normally HIGH (unsafe)
       when in  READ or  IDLE mode.   When  a  WRITE  mode  is
       initiated, WUS  goes low  after a  period of  up  to  1
       microsecond; this  indicates a  safe condition  when in
       WRITE mode.   An  unsafe condition exists if any of the
       following occur:

         the WDI frequency is too low
         there is no write current
         the device is in READ mode
         the chip is disabled







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4.3.2     Pulse Detector

       The primary function of the pulse detector is to detect
       "legitimate" peaks  of the  read-back signal  from  the
       head,  disk,  and  preamplifier.    A  legitimate  peak
       corresponds to  a written  flux transition on the disk.
       Other undesired  peaks can  be caused  by noise.    The
       pulse detector must detect these legitimate peaks while
       preserving the  timing associated with them.  Each peak
       is represented by the presence of a narrow pulse on the
       +ENDATA (encoded data) line, with timing information in
       the leading  edge.   This  pulse  stream,  representing
       encoded data,  is ultimately  time synchronized  by the
       PLL data  separator so  that it  can be  decoded by the
       encoder/decoder (ENDEC).

       The pulse  (or peak)  detection function is implemented
       with an 8464 pulse detector integrated circuit.

       The following functions are used to achieve the primary
       purpose of this circuitry as stated above.

       NOTE: Differential signals are denoted by pin pairs.


A    SIGNAL AMPLIFICATION USING AGC

       Figure 411,  Pulse Detector,  shows  the  preamplified
       head signal as the input to a gain-controlled amplifier
       in the  8464 pulse detector.  AGC is used to maintain a
       constant, predetermined  signal level  at the  input to
       the hysteresis  comparator in the 8464 (pins twenty-one
       and twenty-two).

       This is important because a DC voltage level on the SET
       HYSTERESIS  line  (pin  three)  programs  a  comparator
       hysteresis which  is intended  to be a fixed percentage
       of the  average zero-to-peak  signal amplitude  at  the
       comparator input.

       This  hysteresis   comparator  provides  the  means  to
       amplitude-qualify signal  peaks as legitimate.  This is
       illustrated  below,   in   Section   4.3.2   C,   Pulse
       Qualification/Peak Detection.

       A gain-control  signal for the first amplifier stage is
       derived from  the signal at pins twenty-one and twenty-
       two by  full-wave rectifying  that signal, filtering it
       by means  of the  AGC capacitor  on  pin  sixteen,  and
       comparing  it  to  a  reference  level,  VREF  (voltage
       reference), at  pin four.  The VREF thus determines the
       signal amplitude  at pins  twenty-one  and  twenty-two,





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       while the  DC  level  on  pin  three,  SET  HYSTERESIS,
       determines the  amplitude qualification  level for peak
       detection.   The discharge  circuit  connected  to  pin
       sixteen allows  AGC discharge current to flow only when
       pulses are  present at  +ENDATA, thereby  allowing  the
       graceful detection  of address marks without perturbing
       the AGC loop.


B    SIGNAL FILTERING

       The amplified  read-back signal  at pins  eighteen  and
       nineteen is  processed by a 6.5 megahertz Bessel filter
       before being  input to  the differentiator  input (pins
       two and  twenty-three).    An  additional  8  megahertz
       Bessel  filter   is  placed   before   the   hysteresis
       comparator  (pins   twenty-one   and   twenty-two)   to
       compensate  for  the  additional  group  delay  in  the
       differentiator, as  well as  some internal delay within
       the system.

       The  differentiator   network  is  a  two  pole  Bessel
       configuration.


C    PULSE QUALIFICATION/PEAK DETECTION

       Figure 410, Peak Detection, shows pertinent wave forms
       which are  referenced to  the pulse detector integrated
       circuit.    The  gate  channel  input  signal  (to  the
       hysteresis comparator) is shown with the SET HYSTERESIS
       level on  pin three.  This is essentially the same wave
       form that  is input  to the time channel differentiator
       stage  at   pins  two   and  twenty-three.    The  time
       differentiated version  of  this  wave  form  has  zero
       crossings that  represent the  peaks of  the input wave
       form.   These zero  crossings are  detected by  a level
       comparator which  triggers  a  bidirectional  one-shot.
       The resulting  pulses at  pins twelve and thirteen thus
       have leading  edges which  carry the timing information
       of the signal peaks.


                               

                         Figure 410
                        Peak Detection


       These clocks  toggle the  pulse-qualifier flip-flop  in
       the 8464  only if the AMPLITUDE QUALIFICATION signal at






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       pin fifteen  (D of  the flip-flop)  has  changed  state
       since the  last clock  was received.   Every  flip-flop
       toggle produces a pulse on pin fourteen (+ENDATA) whose
       leading edge  retains the  timing of  the corresponding
       signal peak.

       Note that  the flip-flop  D  changes  state,  and  thus
       qualifies the  next flip-flop  clock only  if the  gate
       channel input  signal  exceeds  the  preset  hysteresis
       level.

       Note  that  "shoulders"  on  the  differentiator  input
       produce "droop"  on the differentiated output which can
       generate spurious  zero crossing.   Figure  410,  Peak
       Detection,    illustrates     the    pulse    amplitude
       qualification.


D    WRITE-TO-READ AND HEAD SWITCH RECOVERY

       Referring to  Figure 411,  Pulse Detector,  the  drive
       uses a  -SQUELCH command,  derived in the SLC, which is
       related to  the system  WRITE command  in the following
       manner:

         when WRITE  is true,  -SQUELCH is true (low) and pin
          eleven is  held high,  which puts  the 8464 in WRITE
          mode.   The 8464  reacts by  lowering  its  internal
          input impedance  at pins  eighteen and nineteen, and
          maintaining the AGC voltage at pin sixteen

         when WRITE  is false,  -SQUELCH remains  true for  5
          microseconds and then becomes false.  This maintains
          the reduced  input impedance  across  pins  six  and
          seven for the 5 microseconds by virtue of the 8464's
          internal circuit,  as well  as an  external  circuit
          shown as "squelch net"


                               

                         Figure 411
                        Pulse Detector


       When a  head switch occurs, -SQUELCH becomes true for 5
       microseconds with the same result as described above.

       The reduced  input impedance during squelch permits the
       input coupling  capacitors to  pins six  and  seven  to
       discharge more  quickly after any new DC offset voltage






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       which may be the result of write-to-read mode switching
       or  head  switching.    If  these  capacitors  are  not
       discharged by  the time the next read data comes along,
       the resulting  pin six  and  seven  differential  input
       voltage hinders a read operation.


4.3.3     Clock Recovery and Decoding

       The clock  recovery and  data standardization functions
       are provided  by the  DP8459 integrated  circuit  which
       receives +ENDATA  from the pulse detector.  Decoding is
       provided  by   the  DP8463B  ENDEC  integrated  circuit
       according to  the rules  of (2,  7) 1/2  code.   Figure
       412, ENDEC/Data  Separator, READ Mode, illustrates the
       system in  READ mode.  The additional logic in the read
       gate synchronization  block and the data resynchronizer
       ensures that the data separator/ENDEC combination meets
       all ESDI specifications.


                               

                         Figure 412
                ENDEC/Data Separator READ Mode



A    DATA SEPARATOR

       The data  separator uses  a phase-lock  loop  (PLL)  to
       recover the  write clock  information from  the encoded
       data stream, +ENDATA.  It operates in three modes under
       control of  the  read  gate  synchronization  circuits.
       When not  reading or  writing (IDLE  mode), or  when in
       WRITE mode,  the data  separator is locked to the write
       clock from  the servo  PLL, and operates in a wide band
       width, phase/frequency  mode.   This insures proper PLL
       lock-up, both  for phase and frequency.  When READ GATE
       is asserted,  RDGAT to  the data separator becomes true
       at the  same time,  beginning a  lock-up sequence;  the
       voltage  controlled   oscillator  (VCO)   in  the  data
       separator stops  and then  restarts synchronously  with
       the incoming  data stream  on +ENDATA,  and  the  phase
       detector goes  into phase  only  mode.    Stopping  and
       restarting  the  VCO  ensures  that  a  relatively  low
       initial phase  error occurs so that the lock-up time is
       well below  the time  allotted by  the 11-byte preamble
       field.     After  preamble  is  detected  in  the  data
       separator, PRDET  becomes true,  which reduces the loop
       gain so  that the band width is reduced.  Additionally,






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       the  PRDET   signal  is   sent   to   the   read   gate
       synchronization logic.   The  data standardizer  in the
       data separator  uses the recovered clock to decide if a
       +ENDATA pulse  has occurred in each window.  The window
       is nominally  50 nanoseconds  wide for  10 megabits per
       second NRZ  data rate.    The  data  standardizer  then
       resynchronizes +ENDATA  to the  recovered clock,  using
       the window  constraint, and  sends synchronous data and
       synchronization clock to the ENDEC.

       When -READ  GATE becomes  false, the  RDGAT to the data
       separator  is  delayed  for  about  seven  write  clock
       periods.   This ensures  that stopping the VCO does not
       interfere with the READ/REF clock switch over.  The VCO
       is stopped  and then restarted synchronously with write
       clock to  ensure minimal initial phase error.  The data
       separator locks  to the  write clock in phase/frequency
       mode and  wide band  width.   After power  up, the data
       separator is  initialized through U63 and the microwire
       bus (National  trade mark) on the data separator.  This
       establishes  the   window  centering   for   the   data
       standardizer in the data separator.


B    ENDEC, READ MODE

       After the  read gate  synchronization logic  receives a
       preamble-detected signal  from the PLL, along with READ
       GATE true,  it issues  RGATE to  the ENDEC.   The ENDEC
       then  switches  the  READ/REF  clock  output  from  the
       reference clock  (servo PLL  write clock)  to  the  PLL
       derived read clock, with no more than two clock periods
       missing, and  no glitches  allowed at  the switch  over
       point.   Additionally, the  read  gate  synchronization
       logic sends  EXPRCMP to  the ENDEC  after approximately
       500 nanoseconds  from the  leading edge  of RGATE.   At
       this point, the ENDEC has acquired code framing and can
       decode the (2,7) 1/2 encoded data to NRZ data.  The NRZ
       data at the MSOUT output on the ENDEC is then reclocked
       with the  data resynchronizer  before going to the line
       driver.   The RDR-FCK  output of the ENDEC is also sent
       to another  line driver  which then  goes to  the  ESDI
       interface.   When READ  GATE becomes  false, RGATE  and
       EXPRCMP to  the ENDEC  both become  false at  the  same
       time, but  RDGAT to  the data  separator is delayed for
       about seven  write clock  periods.   This is  to ensure
       that a  proper switch over occurs on the READ/REF clock
       output of  the ENDEC.   The  switch over  from the read
       clock to  the reference  clock (write  clock) occurs at
       the same  time that  -READ GATE (or RGATE at the ENDEC)
       becomes false.






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4.3.4     Write Path and Encoding

       Figure 413,  Write Path,  details the write path.  The
       ENDEC receives  NRZ data  from the  line receivers  and
       encodes it  to (2,7) 1/2 code according to the encoding
       rules, using write clock as the master clock.


                               

                         Figure 413
                          Write Path



A    SOFT SECTOR WRITE

       When the  drive is configured for soft sector operation
       (JP31 installed),  address marks  are  written  on  the
       drive through the -AME (address mark enable) line along
       with -WRITE  GATE.   An address  mark is  a  dc  erased
       portion of  the track  of 3 bytes.  When the controller
       initiates a  WRITE in soft sector mode, the -WRITE GATE
       input becomes  true and  -AME is enabled at the time an
       address mark is to be written.  The ENDEC does not send
       pulses out  on the  WDI lines  during this time so that
       the dc erased mark is written on the disk.


B    HARD SECTOR WRITE

       When the  drive is configured for hard sector operation
       (JP31 removed),  address marks  are not  written on the
       disk and  the start  of a  sector is  indicated by  the
       drive with  the sector  mark output.    The  number  of
       sectors per  track is  selected by  jumpers, or  can be
       configured  through  the  interface  if  the  drive  is
       jumpered for  this option.  -WRITE GATE again initiates
       a write operation.


C    ENCODING DATA

       The NRZ  WRITE DATA and WRITE CLOCK from the controller
       are received  by the  line receivers  on the drive, and
       are converted  to TTL  levels before  being sent to the
       ENDEC.   The ENDEC  then encodes  the NRZ data to (2,7)
       1/2 code  that is  sent out of the CODOUT output of the
       ENDEC.   This then  goes to  the WDI  input of the flex
       circuit.







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D    ENCODING RULES

       The ENDEC,  when in  WRITE mode,  encodes the NRZ write
       data using  (2, 7) 1/2 encoding rules.  The NRZ code is
       encoded to meet the desired run constraints of no fewer
       than two, and no more than seven, encoded zeros written
       between transitions.   By  doing this, any long runs of
       NRZ zeros are encoded such that transitions are present
       for  the   clock  regeneration   circuitry  (the   data
       separator PLL).

       If the code did not place a bound on the longest period
       between transitions,  as with  the NRZ  data, the  data
       separator would not have any data to lock to, resulting
       in the  data separator  losing synchronization  over  a
       period of  time.  Most importantly, the (2, 7) 1/2 code
       has properties  which improve  the performance  of  the
       read channel.

       The period  of time between transitions for various (2,
       7) 1/2 code lengths can be determined by the following:

          (N)       T = (Td/2) (N+1)  n = 2, 3, 4, 5, 6, 7

          Where:    N = n + 1
                    Td = NRZ data clock period

          10 Mbps
          Td = 100.00    nanoseconds

          (3)       T = 150   nanoseconds
          (4)       T = 200   nanoseconds
          (8)       T = 400   nanoseconds

       For the  (2, 7)  1/2 code, (3) T is the shortest period
       that can  be written,  also known as Tmin, and (8) T is
       the longest  period that  can be written, also known as
       Tmax.


4.3.5     Address Mark Detection

       When a  drive has  been formatted  in soft sector mode,
       address marks  are  used  to  establish  the  start  of
       sectors.   An address  mark is  a 3-byte  dc erased gap
       written on the track.  Interface signals tell the drive
       to search  for an  address mark  by making  -AME  true,
       along with -DRIVE SELECT.  These interface commands are
       then converted  to AME  and are sent to the ENDEC input
       AMENBL.   This starts an address mark search within the
       ENDEC.   When the  ENDEC detects  an address  mark,  it
       sends out  AMF (address  mark found).   This  signal is





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       then sent  out to the SLC which, in turn, sends it to a
       buffer and  then to  the interface as -AMF/SECTOR.  The
       SLC controls  which signal  is sent to the -AMF/SECTOR,
       depending on  whether the  drive is  jumpered for  soft
       sector (-AMF  is output)  or hard  sector  (-SECTOR  is
       output).

       After the  controller receives  the  -AMF  signal,  the
       controller sets  -AME to  false.    When  -AME  becomes
       false, the  AMF signal  to the  SLC becomes false.  The
       address mark has been detected and the controller turns
       on  -READ  GATE  to  the  interface.    -READ  GATE  is
       conditioned,  along   with  -DRIVE  SELECT  and  CMDCMP
       (command complete), before it is input to the read gate
       synchronizing block  as RDGT.   The  read process  then
       starts as described above.









































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5.0  FUNCTIONAL OPERATION


5.1  POWER UP SEQUENCE

       DC power  (+5 volt  and +12  volt) may  be supplied to the
       drive in  any order, but +12 volts DC is required to start
       the spindle  motor.   The motor  power up is controlled by
       the status  of jumper  JP6 on  the drive  electronics  PCB
       assembly.   (The location  and function of all PCB jumpers
       are shown  in Figure  81, Drive Jumper Options, and Table
       82, Jumper Selections.)

       If jumper  JP6 is open, the spindle power up sequencing is
       initiated by  the issuance  of  the  START  MOTOR  CONTROL
       command.

       When the  spindle reaches  full speed,  the actuator  lock
       automatically disengages and the heads then recalibrate to
       track zero.   Upon  a successful  recalibration, READY and
       COMMAND COMPLETE  status signals  are true.  The unit does
       not perform any read, write, or seek functions until READY
       is true.  (If after starting, 1,000 revolutions per minute
       is not  reached in  ten  seconds,  an  automatic  shutdown
       procedure is initiated; power to the spindle motor is shut
       off and the drive does not become READY.)


                                

                           Figure 51
               Power Up Sequence (Jumper JP6 Open)


       If  jumper   JP6  is   installed,  the  spindle  power  up
       sequencing is  initiated by  the application  of DC power.
       (When shipped, the JP6 jumper is installed.)


5.2  DISK DRIVE SELECTION

       Drive selection  occurs when  the  controller  places  the
       address of  the drive  to be  selected on  the three drive
       select lines.  See Figure 52, Drive Select Circuit.  Only
       the selected drive responds to the input signals, and only
       that  drive's   output  signals  are  then  gated  to  the
       controller.   The details  of setting  the drive selection
       jumper are  covered in  section 8.1,  Disk  Drive  Address
       Selection Jumper.








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                           Figure 52
                      Drive Select Circuit



                                

                            Table 51
                     Drive Selection Matrix



5.3  DISK DRIVE TERMINATION

       If more  than one  Maxtor drive  is used  in a system, the
       terminator packs  (RN13 and  RN14) must  be removed in all
       but the  last drive in the string.  Figure 81, Disk Drive
       Jumper Options, shows the location of RN13 and RN14.





































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6.0  ELECTRICAL INTERFACE

       The interface  to the  drive  can  be  divided  into  four
       separate  categories,   each  of   which   is   physically
       separated:

         control signals
         data signals
         DC power
         auxiliary signals

       All control  lines are digital (open collector transistor-
       transistor logic (TTL)), and either provide signals to the
       drive  (input)   or  signals  to  the  host  (output)  via
       interface connection J1/P1.  The data transfer signals are
       differential and  provide data  either to  (write) or from
       (read) the drive via J2/P2.

       Figure  61,  Control  Cable  J1/P1  Signals,  Table  61,
       Control Cable  J1/P1 Pin  Assignments,  Figure  62,  Data
       Cable J2/P2  Signals, and  Table 62, Data Cable J2/P2 Pin
       Assignments,   show    connector   pin   assignments   and
       interconnection of cabling between the host controller and
       drives.


                                

                           Figure 61
                   Control Cable J1/P1 Signals



                                

                            Table 61
               Control Cable J1/P1 Pin Assignments



                                

                           Figure 62
                    Data Cable J2/P2 Signals



                                

                            Table 62
                Data Cable J2/P2 Pin Assignments






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       Figure  63,   Typical   Auxiliary   Cable   and   Spindle
       Synchronization Connection, and Table 63, Auxiliary Cable
       (J6) Pin  Assignments, show connector pin assignments, and
       interconnection  of   cabling  between   drives,  for  the
       auxiliary signals.


                                

                           Figure 63
 Typical Auxiliary Cable and Spindle Synchronization Connection



                                

                            Table 63
              Auxiliary Cable (J6) Pin Assignments



                                

                           Figure 64
                  Typical Multidrive Connection



6.1  CONTROL INPUT LINES

       The control  input signals  are one of two types: those to
       be multiplexed  in a multidrive system, and those intended
       to do the multiplexing.  The signals to be multiplexed are
       WRITE GATE,  TRANSFER REQ,  and COMMAND DATA.  The signals
       which do the multiplexing are DRIVE SELECT 1, DRIVE SELECT
       2, and DRIVE SELECT 3.

       The   input    lines   have   the   following   electrical
       specifications   (see   Figure   65,   Control   Signals,
       Driver/Receiver Combination, for the recommended circuit):

          TRUE:  0.0 V DC to 0.4 V DC @ 1 = -48  mA (max)

          FALSE:   2.5 V  DC to  5.25 V  DC @  0 =  +250 A (open
       collector)


                                

                           Figure 65
          Control Signals, Driver/Receiver Combination






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6.1.1     HEAD SELECT 20, 21, 22, and 23

       The  four  HEAD  SELECT  lines  allow  selection  of  each
       individual read/write  head in  a binary  coded  sequence.
       HEAD SELECT  20 is the least significant line.  Data heads
       are numbered  and addressed continuously from zero through
       the maximum  head number.   When all HEAD SELECT lines are
       high (inactive), head zero is selected.

       Addressing more  heads than contained in the drive results
       in a  write fault  when  attempting  to  perform  a  write
       operation.

       A 150 ohm terminator pack allows for line termination.


6.1.2     WRITE GATE

       The active  state of  this signal,  or low  level, enables
       write data to be written on the disk.

       The HI  to LO  transition of  this signal  creates a write
       splice and  initiates the writing of the data phase-locked
       oscillator (PLO)  synchronization field by the drive.  See
       Figure 66,  Soft Sector  Address Mark,  WRITE  GATE,  PLO
       Synchronous Format  Timing.   When formatting,  WRITE GATE
       should be  deactivated for 2 bit times minimum between the
       address area  and the data area, to alert the drive to the
       beginning of the data PLO synchronization field.

       NOTE: The controller must send zeros during the writing of
       a PLO synchronization field.


                                

                           Figure 66
  Soft Sector Address Mark, WRITE GATE, PLO Synchronous Format
                             Timing


       An alternate  format timing in hard sector mode, using the
       ADDRESS MARK  ENABLE signal,  is shown in Figure 67, Hard
       Sector WRITE  GATE, PLO  Synchronous Format  Timing, Using
       ADDRESS MARK ENABLE.


                                

                           Figure 67
  Hard Sector WRITE GATE, PLO Synchronous Format Timing, Using
                       ADDRESS MARK ENABLE





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       This line  is protected  from  terminator  power  loss  by
       implementation of  the circuit  shown in Figure 68, WRITE
       GATE Termination.


                                

                           Figure 68
                     WRITE GATE Termination



                                

                           Figure 69
      Hard Sector WRITE GATE, PLO Synchronous Format Timing



6.1.3     READ GATE

       The active  state of  this signal,  or low  level, enables
       data to  be read  from the  disk.   This signal  should be
       activated only  during a  PLO synchronization field and at
       least 10  bytes prior  to the  ID, or data synchronization
       bytes.   The PLO  synchronization field length is 11 bytes
       and is  indicated by  the response to the REQUEST PLO SYNC
       FIELD LENGTH  command.  Read gate must be deactivated when
       passing over a write splice area.

       A 150 ohm terminator pack allows for line termination.


6.1.4     COMMAND DATA

       When presenting  a command,  sixteen information  bits  of
       serial data,  plus parity,  are presented  on  this  line.
       This data  is to  be controlled  by the handshake protocol
       with signals  TRANSFER REQ  and TRANSFER  ACK (see  Figure
       615, Typical  Serial Operation(s)).  Upon receipt of this
       serial data,  the drive performs the required function, as
       specified by  the bit  configuration. Data  is transmitted
       most significant  byte first.  See Table 64, COMMAND DATA
       Definition,  for   the  meaning   of   the   various   bit
       combinations. See  Figure 610, One Bit Transfer Timing-To
       Drive, for  timing.   Odd parity must be maintained.  (The
       number of  bits set to one in a command, including parity,
       must be odd.)

       No communications  should be  attempted unless the COMMAND
       COMPLETE line is true.

       Reading and  writing are inhibited during the execution of
       commands.



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       NOTE:   The COMMAND DATA line must be at a logic zero when
       not in use.

       A 150 ohm resistor pack allows for line termination.


                                

                            Table 64
                     COMMAND DATA Definition



                                

                           Figure 610
                One Bit Transfer Timing-To Drive


       See Figure  611,  COMMAND  DATA  Word  Structure,  for  a
       diagram of the COMMAND DATA bytes.


                                

                           Figure 611
                   COMMAND DATA Word Structure


       SEEK (0000):  This command causes the drive to seek to the
       cylinder indicated  in bits  eleven through  zero.  A SEEK
       command restores track offsets to zero.

       RECALIBRATE (0001):   This  command causes the actuator to
       return to  cylinder 0000.   A RECALIBRATE command restores
       track offsets to zero.

       REQUEST STATUS  (0010): This  command causes  the drive to
       send 16 bits (see Table 68, TRACK OFFSET Command Modifier
       Bits) of standard status information to the controller, as
       determined by the command modifier bits.

       When the  command modifier  bits  (11-8)  of  the  REQUEST
       STATUS command  are 0000,  the drive responds with 16 bits
       of  standard  status.    See  Table  65,  REQUEST  STATUS
       Modifier Bits.  Bits fifteen through twelve of this status
       are defined  as state bits which do not cause ATTENTION to
       be asserted.   Bits eleven through zero of this status are
       fault, or  change of  status, bits that cause ATTENTION to
       be asserted each time one is set.

       When the  command modifier  bits  (11-8)  of  the  REQUEST
       STATUS command  are 0001  through 0111, the drive responds
       with the  vendor unique  status.   The  number  of  vendor



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       unique status  words is  specified  by  the  configuration
       data.


                                

                            Table 65
                  REQUEST STATUS Modifier Bits

       REQUEST CONFIGURATION  (0011):   This command  causes  the
       drive to  send  16  bits  of  configuration  data  to  the
       controller.    The  specific  configuration  requested  is
       specified by  bits eleven through eight of the command, as
       shown in  Table 66,  REQUEST CONFIGURATION Modifier Bits.
       Furthermore,  the   drive  responds   to  the  subscripted
       command, REQUEST  FOR CONFIGURATION  with Are synchronized
       spindles configured?  (0011 0000 0000 0001).  The response
       is 1000 0000 0000 0000 (Yes) or 0000 0000 0000 0000 (No).


                                

                            Table 66
               REQUEST CONFIGURATION Modifier Bits


       CONTROL  (0101):     This   command  causes   the  control
       operations specified  by bits  eleven through  eight to be
       performed as  described  in  Table  67,  CONTROL  Command
       Modifier Bits.


                                

                            Table 67
                  CONTROL Command Modifier Bits


       TRACK OFFSET  (0111): This  command causes  the  drive  to
       perform  a  track  offset  in  the  direction  and  amount
       specified by  bits eleven  through eight,  as outlined  in
       Table 68,  TRACK OFFSET  Command  Modifier  Bits.    Each
       offset  value  is  5%  of  the  track  width.    SEEK  and
       RECALIBRATE commands restore track offsets to zero.


                                

                            Table 68
               TRACK OFFSET Command Modifier Bits







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       INITIATE DIAGNOSTICS  (1000):   This  command  causes  the
       drive to  perform 10,000 random seeks as a diagnostic aid.
       Successful completion  of the  diagnostics is indicated by
       COMMAND COMPLETE with no ATTENTION.

       SET UNFORMATTED  BYTES PER  SECTOR (1001):   This optional
       command causes  the drive to set the number of unformatted
       bytes per sector indicated in bits eleven through zero (if
       implemented).   This command is valid only if the drive is
       configured in  the hard  sectored mode  and jumper JP30 is
       installed.


6.1.5     TRANSFER REQ

       This line  functions as a handshake signal, in conjunction
       with TRANSFER ACK, during command and configuration/status
       transfers.   See Figure  610, One  Bit Transfer Timing-To
       Drive, and  Figure  612,  One  Bit  Transfer  Timing-From
       Drive,  for  timing.  The  transfer  speed  (one  complete
       handshake) takes  typically 11.76  microseconds  per  bit.
       Longer times  may be experienced depending on the overhead
       experienced at the controller.


                                

                           Figure 612
               One Bit Transfer Timing-From Drive



6.1.6     ADDRESS MARK ENABLE


A    SOFT SECTOR MODE ONLY

       This signal,  when  active  with  WRITE  GATE,  causes  an
       address mark to be written.  ADDRESS MARK ENABLE is active
       for 24  bit times.   See  Figure 613,  Write Address Mark
       Timing.

       ADDRESS MARK  ENABLE, when  active without  WRITE GATE  or
       READ GATE, causes a search for address marks.


                                

                           Figure 613
                    Write Address Mark Timing







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B    HARD AND SOFT SECTOR MODES

       If WRITE  GATE is  true,  the  LO  to  HI  transition,  or
       deassertion of  ADDRESS MARK  ENABLE, causes  the drive to
       begin writing  the ID  PLO  synchronization  field.    See
       Figure 66,  Soft Sector  Address Mark,  WRITE  GATE,  PLO
       Synchronous Format Timing.  The controller must send zeros
       during the writing of the PLO synchronization field.

       A 150 ohm terminator pack allows for line termination.


6.2  CONTROL OUTPUT LINES

       The  output  control  signals  are  driven  with  an  open
       collector output  stage capable of sinking a maximum of 48
       milliamps at  low  level,  or  true  state,  with  maximum
       voltage of  0.4 volts,  measured at  the driver.  When the
       line driver  is in  the high  level, or  false state,  the
       driver transistor  is off and collector leakage current is
       a maximum of 250 microamps.

       All J1  output lines  are  enabled  by  the  drive  select
       decoder.

       Figure 65,  Control Signals, Driver/Receiver Combination,
       shows the recommended circuit.


6.2.1     DRIVE SELECTED

       A status line is provided at the J2/P2 connector to inform
       the host system of the selection status of the drive.  The
       DRIVE SELECTED  line is  driven by  a TTL  open  collector
       driver,  as   shown  in   Figure  65,   Control  Signals,
       Driver/Receiver Combination.  This signal goes active only
       when the  drive is  selected, as  defined in  section 5.2,
       Disk Drive Selection.  The DRIVE SELECT lines at J1/Pl are
       activated by the host system.


6.2.2     READY

       This signal  indicates that  the spindle  is up  to speed.
       This interface  signal, when  true, together  with COMMAND
       COMPLETE, indicates  that the  drive  is  ready  to  read,
       write, or  seek.   When the line is false, all writing and
       seeking is inhibited.


6.2.3     CONFIG-STATUS DATA

       The drive  presents serial  data on this line upon request
       from the  controller.   See Figure  615,  Typical  Serial



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       Operation(s), for  typical operation. CONFIG-STATUS serial
       data is  presented to  the interface and transferred using
       the handshake  protocol  with  signals  TRANSFER  REQ  and
       TRANSFER  ACK;   see  Figure   612,  One   bit   Transfer
       Timing-From Drive.  Once initiated,  16 bits, plus parity,
       are transmitted,  most significant byte first.  Odd parity
       is maintained.


                                

                           Figure 614
                CONFIG-STATUS DATA Word Structure



                                

                           Figure 615
                   Typical Serial Operation(s)


       In response  to the  REQUEST STATUS  command, 16  bits  of
       status information  is returned  to  the  controller.  Odd
       parity is maintained.

       If the  command modifier  bits (eleven  through eight) are
       0000, the  standard status  information is  returned  (see
       Table 69, Standard Status Response Bits).


                                

                            Table 69
                  Standard Status Response Bits


       Bits fifteen  through twelve  of the status are defined as
       state bits,  which do  not cause ATTENTION to be asserted.
       Bits eleven  through zero  are fault, or change of status,
       bits which cause ATTENTION to be asserted.

       Conditions that can cause WRITE FAULT are:

         write current in a head without WRITE GATE active or no
          write current  with WRITE  GATE active  and  the  drive
          selected
         writing before a COMMAND COMPLETE signal is received
         writing while the head is off track
         having DC voltages grossly out of tolerance
         having WRITE GATE active to a write protected drive
         having nonzero  data during a PLO synchronization field
          write




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         simultaneously activating READ GATE and WRITE GATE

       If the  command modifier  bits (eleven  through eight) are
       used, the  vendor unique status information shown in Table
       610, Vendor Unique Status Response Bits.


                                

                           Table 610
               Vendor Unique Status Response Bits



                                

                           Table 611
                          Motor Status


       The SEEK  calibration error  portion of  word two  is only
       valid with  bit nine  of word one set.  With this bit set,
       the error  code is  interpreted as  in  Table  612,  SEEK
       Calibration Error Code.


                                

                           Table 612
                   SEEK Calibration Error Code



                                

                           Table 613
               General Configuration Response Bits


       The motor  status portion of word one of the vendor unique
       response  is   translated  as   in  Table  614,  Specific
       Configuration Response Bits.


                                

                           Table 614
              Specific Configuration Response Bits









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6.2.4     TRANSFER ACK

       This signal  functions as  a handshake  signal, along with
       TRANSFER  REQ,  during  command  and  configuration-status
       transfers.   See Figure  610, One  Bit Transfer Timing-To
       Drive, and  Figure  612,  One  Bit  Transfer  Timing-From
       Drive.


6.2.5     ATTENTION

       This  output   is  asserted   when  the  drive  wants  the
       controller to  request its  standard status.    Generally,
       this is  a result  of a  fault condition  or a  change  of
       status.   Writing is inhibited when ATTENTION is asserted.
       ATTENTION is  deactivated by the reset interface attention
       command modifier,  under the  CONTROL command (see section
       6.1.4, COMMAND DATA).


6.2.6     INDEX

       This pulse  is provided  by the drive once each revolution
       to indicate  the beginning  of a  track.   Normally,  this
       signal is high and makes the transition to low to indicate
       INDEX.   Only the  transition at  the leading  edge of the
       signal is  reciprocal of  the rotational speed (see Figure
       616, INDEX  Timing).   This signal  is available  on  the
       command cable  J1/P1 (gated)  and on  the data cable J2/P2
       (ungated).


                                

                           Figure 616
                          INDEX Timing



6.2.7     ADDRESS MARK FOUND (Soft Sector)

       This signal  indicates the  detection of  the  end  of  an
       address mark.   See  Figure 617, Read Address Mark Timing
       (Hard Sector), for timing.


                                

                           Figure 617
             Read Address Mark Timing (Hard Sector)







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6.2.8     SECTOR MARK (Hard Sector)

       This optional  interface signal  indicates the  start of a
       sector.   No short  sectors are allowed.  The leading edge
       of the  asserted sector  pulse is  the only  edge that  is
       accurately controlled.   The  INDEX pulse indicates sector
       zero.  See Figure 618, Sector Pulse Timing (Hard Sector).


                                

                           Figure 618
                Sector Pulse Timing (Hard Sector)



6.2.9     COMMAND COMPLETE

       COMMAND COMPLETE  is a  status line  provided at the J2/P2
       connector.   This is  an ungated  output from  the  drive,
       which allows  the host  to  monitor  the  drive's  COMMAND
       COMPLETE  status   during  overlapped   commands,  without
       selecting the  drive.   This signal line goes false in the
       following cases:

         a recalibration  sequence is initiated (by drive logic)
          at power  on if the read/write heads are not over track
          zero

         the signal  line goes  false upon  receipt of the first
          COMMAND DATA  bit.  COMMAND COMPLETE stays false during
          the entire command sequence

       This signal  is driven  by an  open collector  driver,  as
       shown in  Figure  65,  Control  Signals,  Driver/Receiver
       Combination.


6.3  SPINDLE SYNCHRONIZATION CONTROL OPTION

       This  feature   allows  up   to  forty-eight   drives   to
       synchronize the  angular position  of their  spindles such
       that  their   INDEX  signals   line  up   to  within   +20
       microseconds of  the leading  edge of  the INDEX signal on
       the master  drive.   In the absence of a MAPIN signal, the
       drive synchronizes  to its  internal  clock.    The  drive
       indexes lead the leading edge of MAPIN by 215 milliseconds
       (typical).   The MAPIN  signal is  derived from  either an
       external 60  hertz  signal,  or  from  the  MAPOUT  signal
       available on  J6 from  one drive  defined  as  the  master
       drive.

       MAPOUT is  a TTL  signal at 60 hertz with a pulse width of
       20 microseconds.



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       The light-emitting diode (LED) output on J6 is an optional
       drive selected signal that is available for use in systems
       that cannot use the LED on the faceplate.

       The remote  write protect  input allows  the drive  to  be
       write protected via the J6 connector.  The active state of
       this signal,  or low  level,  prohibits  data  from  being
       written to the drive.

       See  Figure  63,  Typical  Auxiliary  Cable  and  Spindle
       Synchronization Connection, for a typical configuration.


6.4  DATA TRANSFER LINES

       All lines associated with the transfer of data between the
       drive and  the host  system are  differential, and are not
       multiplexed.  These   lines  are  provided  at  the  J2/P2
       connectors on all drives.

       Four pairs  of balanced  signals are used for the transfer
       of data  and clock:  NRZ WRITE  DATA, NRZ READ DATA, WRITE
       CLOCK, and  READ/REFERENCE  CLOCK.  Figure 619, Data Line
       Driver/Receiver Combination,   illustrates the recommended
       driver/receiver circuit.


                                

                           Figure 619
              Data Line Driver/Receiver Combination



6.4.1     NRZ READ DATA

       The data  recovered by  reading  a  prerecorded  track  is
       transmitted to  the host  system via the differential pair
       of NRZ  READ DATA  lines. This data is clocked by the READ
       CLOCK  signal.   See  Figure  620,  NRZ  READ/WRITE  DATA
       Timings, for timing.  These lines are held at a zero level
       until PLO  synchronization has  been obtained  and data is
       valid.


6.4.2     NRZ WRITE DATA

       This is  a differential  pair that  defines the data to be
       written on  the track.  This data  is clocked by the WRITE
       CLOCK signal.    See  Figure  620,  NRZ  READ/WRITE  DATA
       Timings, for  timing. These  lines must  be held at a zero
       level during the writing of PLO synchronization.





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                           Figure 620
                   NRZ READ/WRITE DATA Timings



6.4.3     READ/REFERENCE CLOCK

       The timing diagram as shown in Figure 620, NRZ READ/WRITE
       DATA Timings,  depicts the  necessary sequence  of events,
       with associated timing restrictions, for proper read/write
       operation of  the drive.   The REFERENCE CLOCK signal from
       the  drive   determines  the  data  transfer  rate.    The
       transitions from  REFERENCE CLOCK  to READ  CLOCK must  be
       performed without  glitches.  Two missing clock cycles are
       permissible.

       The REFERENCE CLOCK rate is 10.0 + 0.10% megahertz.

       The READ CLOCK rate is 10.0 + 0.30% megahertz.


6.4.4     WRITE CLOCK

       WRITE CLOCK  is provided  by the controller and must be at
       the bit  data transfer  rate.   This  clock  frequency  is
       dictated by  the READ/REFERENCE  CLOCK  during  the  write
       operation.   See Figure 620, NRZ READ/WRITE DATA Timings,
       for timing.

       WRITE CLOCK  need not  be  continuously  supplied  to  the
       drive.   WRITE CLOCK should be supplied before beginning a
       write operation  and must  last for  the duration  of  the
       write operation.






















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7.0  PHYSICAL INTERFACE

       The electrical  interface between  the drive  and the host
       controller is via four connectors:

         J1 - control signals (multiplexed)
         J2 - read/write signals (radial)
         J3 - DC power input
         J4 - frame ground

       Jumper J6  is the spindle synchronization connector and is
       connected to the drives using this option.

       Refer  to   Figure  71,   Interface  Connector   Physical
       Location, for connector locations.


                                

                           Figure 71
              Interface Connector Physical Location



7.1  J1/P1 CONNECTOR

       Connection  to  J1  is  via  a  thirty-four-pin  PCB  edge
       connector.  The dimensions for this connector are shown in
       Figure  72,  J1  Connector  Dimensions.    The  pins  are
       numbered one  through  thirty-four,  with  the  even  pins
       located on  the component  side of  the PCB.   Pin  two is
       located on  the end of the PCB connector closest to the DC
       power connector  J3/P3.   A key  slot is  provided between
       pins four  and six.   The recommended mating connector for
       P1  is  AMP  ribbon  connector  part  number  88373-3,  or
       equivalent.


                                

                           Figure 72
                     J1 Connector Dimensions



7.2  J2/P2 CONNECTOR

       Connection of  J2 is  via a twenty-pin PCB edge connector.
       The dimensions  for the connector are shown in Figure 73,
       J2 Connector  Dimensions.    The  pins  are  numbered  one
       through  twenty,   with  the  even  pins  located  on  the
       component  side  of  the  PCB.    The  recommended  mating
       connector for  P2 is  AMP ribbon  connector,  part  number




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       88373-6.   A key  slot is  provided between  pins four and
       six.


                                

                           Figure 73
                     J2 Connector Dimensions



7.3  J3/P3 CONNECTOR

       The DC  power connector  (J3), Figure  74,  J3  Connector
       (Drive PCB,  Solder Side),  is a  four-pin AMP MATE-N-LOCK
       connector, part  number 350543-1,  mounted on  the  solder
       side of the PCB.  The recommended mating connector (P3) is
       AMP part  number 1-480424-0,  using AMP  pins part  number
       350078-4 (strip) or part number 61173-4 (loose piece).  J3
       pins are  numbered as shown in Figure 74.


                                

                           Figure 74
              J3 Connector (Drive PCB Solder Side)



                                

                            Table 71
                Power Connector (J3) Requirements



7.4  J4/P4 FRAME GROUND CONNECTOR

       The frame  ground connection  is a Faston-type connection,
       AMP part number 61761-2.  The recommended mating connector
       is AMP  62187-1. If  wire is  used, the  hole  in  J4  ac-
       commodates a wire size of 18 AWG maximum.


7.5  J6/P6 AUXILIARY CONNECTOR

       The  auxiliary  connector  is  a  Berg  68451-121  ten-pin
       connector.   The mating  connector is a 3M 3473-6010.  See
       Table 72,  J6 Auxiliary Signal Cable Pin Assignments, for
       pin assignments.







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                            Table 72
            J6 Auxiliary Signal Cable Pin Assignments





















































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8.0  PCB JUMPER OPTIONS


8.1  DISK DRIVE ADDRESS SELECTION JUMPER

       In multidrive configurations, it is necessary to configure
       each drive  with a  unique address.   A  maximum of  seven
       drives are  permitted per  single host  controller.    The
       address for  the drive  is determined  by  installing  the
       jumper plug  in the  appropriate jumper  location  (Figure
       81, Drive  Jumper Options).    Table  81,  Drive  Select
       Jumpers, shows  the drive  selection jumpers.   As shipped
       from the  factory, the drive is configured as logical unit
       number one.  Removing the jumper entirely is equivalent to
       a "no select."


                                

                            Table 81
                    Disk Drive Select Jumpers



                                

                           Figure 81
                    Disk Drive Jumper Options



                                

                            Table 82
                        Jumper Selections



8.2  DATA HEAD SELECTION JUMPERS (JP32-JP36)

       Jumpers have  been provided  to allow the number of usable
       data heads  to be  selected.   In order  for the  drive to
       respond correctly  to the  request configuration command -
       number of  heads, these  jumpers are set at the factory to
       correspond with  the model  of the drive.  Table 83, Data
       Head  Number   Selection  Jumpers,   shows   the   various
       configuration options.


                                

                            Table 83
               Data Head Number Selection Jumpers




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8.3  WRITE PROTECT SELECTION JUMPER (JP14)

       Jumper JP14  is the write protect jumper.  When the jumper
       is present  (installed), the  drive is write-protected and
       can only  be read;  no writing  may take place.  The drive
       does not  have this  jumper installed  when it  is shipped
       from the factory.


8.4  OPTION FOR SEQUENTIAL SPINDLE MOTOR SPINUP JUMPER (JP6)

       The spindle  motor spinup  jumper (JP6) allows a string of
       drives to be started sequentially by the controller.  When
       the jumper is present (installed), the drive automatically
       spins up  as soon as power is applied.  If JP6 is removed,
       the drive  is started  by issuing  the appropriate command
       from the  controller.  As shipped from the factory, jumper
       JP6 is installed.


8.5  TEST JUMPERS (JP1, JP41, JP42)

       These jumpers  provide access to certain test signals. The
       specific signals and the normal factory settings are shown
       in Table 84, Test Pin Jumpers.


                                

                            Table 84
                        Test Pin Jumpers



8.6  HARD SECTOR CONFIGURATION JUMPERS (JP16-29)

       Jumper JP31  selects the  mode of  operation.  Jumper JP31
       installed configures  the drive  as a  soft sector  drive;
       removed, it configures the drive as a hard sectored drive.

       Jumpers JP16  through JP29 allow the user to configure the
       drive's hard  sector size.  The sector size can range from
       a minimum  of 123 to a maximum of 10,470 bytes per sector,
       with 1 byte granularity.

       The hard  sector configuration  jumpers are  encoded in  a
       binary fashion,  with JP16  being  the  least  significant
       byte, and  JP29 being  the  most  significant  byte.    An
       installed jumper equates to a one.

       Jumper JP30, if installed, enables setting the hard sector
       size over the ESDI interface.





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                            Table 85
                   Customer Selectable Jumpers

                                



















































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9.0  DISK DRIVE INSTALLATION

       This  section   describes  the  mounting  and  shipping
       recommendations for the XT-4000E Family disk drives.


9.1  MOUNTING ORIENTATION

       The drive  may be  mounted in  any orientation.  In any
       final mounting configuration, insure that the operation
       of the  three shock  mounts,  which  isolate  the  base
       casting from  the frame  are not  restricted.   Certain
       switching power  supplies may  emanate electrical noise
       which degrades the specified read error rate.  For best
       results, it  is suggested that the drive be oriented so
       that the  PCB assembly  is not  adjacent to these noise
       sources.


9.2  MOUNTING HOLES

       Eight mounting  holes, four  on the  bottom and  two on
       each side,  are provided for mounting the drive into an
       enclosure.  The size and location of these holes, shown
       in Figure  91, Mechanical  Outline and  Mounting  Hole
       Locations, are  identical to  industry standard  floppy
       drives.   (See also  Figure  92,  Mechanical  Outline,
       Bottom and Side Views.)

       CAUTION:   The casting  is  very  close  to  the  frame
       mounting holes  in  some  locations.    Mounting  screw
       lengths must  be chosen  such that  no more  than 0.125
       inches of  the screw  is available  to enter  the frame
       mounting hole.   The  torque applied  to  the  mounting
       screws should  be at  least 9 inch-pounds; but to avoid
       stripping  the  threads,  the  maximum  torque  applied
       should not exceed 12 inch-pounds.


                               

                          Figure 91
        Mechanical Outline and Mounting Hole Locations



                               

                          Figure 92
          Mechanical Outline, Bottom and Side Views







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9.3  SHIPPING REQUIREMENTS

       At power  down the  heads are  automatically positioned
       over the  nondata, dedicated  landing zone on each disk
       surface.   The automatic shipping lock solenoid is also
       engaged at  this time.    Maxtor  ships  the  drive  in
       single- and multipack shipping containers.


9.4  REMOVABLE FACEPLATE

       The faceplate  may be  removed  in  installations  that
       require it.   Remove the two C-clips and unplug the LED
       cable  from   the  PCB.    See  Figure  93,  Removable
       Faceplate.


                               

                          Figure 93
                     Removable Faceplate




































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APPENDIX A:  MEDIUM DEFECTS AND ERRORS

       Defects on  the medium surface are identified on both a
       paper defect map and a defect map, written on the drive
       according to  the ESDI format rules.  These defect maps
       indicate the  head number,  track number, and number of
       bytes from index for each defect.

       The maximum  allowable number of defects per drive does
       not exceed  an  average  of  fifty  per  disk  surface.
       Cylinder zero is certified to be defect-free.

       The maximum  number of  encoded (NRZ) defects per drive
       is listed in Table A1, Maximum Number of Defects.


                               

                          Table A1
                  Maximum Number of Defects


       As shipped,  the disk  drive contains two copies of the
       defect map,  written  on  different  locations  on  the
       disks.

       One complete  defect list  resides on  sector  zero  of
       cylinder 1,223.  An identical copy is located on sector
       zero of  cylinder 1,215.   This  allows for  redundancy
       should an  error occur  on cylinder 1,223.  Sector zero
       of any  surface contains  the defects for that surface.
       The format  for the data field portion (see Figure A1,
       Defect List Format) of this sector is 256 bytes, with 2
       bytes of  cyclic redundancy check (CRC) (x16 + x12 + x5
       + 1).

       Defect locations are identified by fields 5 bytes long.
       Other byte  definitions are shown in Figure A1, Defect
       List Format.   Byte  count is  the number of bytes from
       INDEX.

       The location of the start of the actual defect may vary
       from the location specified on the defect list by up to
       + 1  byte due  to the rotational speed tolerance of the
       drive motor.

       The  end  of  the  defect  list  for  each  surface  is
       indicated by  5 bytes  of ones  in the  defect location
       field, or the end of the sector.








Doc 1011004, Rev C           98           Maxtor Corporation

    XT-4000E Product Specification & OEM Technical Manual


       The CRC  check bytes should be used, if that capability
       exists, but may be ignored if multiple reads are a more
       desirable approach.


                               

                          Figure A1
                      Defect List Format
















































Doc 1011004, Rev C           99           Maxtor Corporation

       
APPENDIX B:  UNITS OF MEASURE
          Abbreviation   Meaning
          

          A/m  amps per meter
          AWG  average wire gauge
          bpi  bits per inch
          dBA  decibel, a-weighted
          fci  flux changes per inch
          g    gram
          Gbyte     gigabyte
          Hz   hertz
          mA   milliamp
          A   microamp
          Mbit megabit
          Mbyte     megabyte
          m   micrometer
          msec millisecond
          sec microsecond
          nsec nanosecond
          Oe   oersted
          RH   relative humidity
          rpm  revolutions per minute
          tpi  tracks per inch
          xxb  binary values
          xxh  hexadecimal values
       
GLOSSARY

       3RDPTY.  Third party

       ACK.  Acknowledge

       ADR.  Address

       AGC.  Automatic gain control

       AM.  Address mark

       AM2.  Address mode two

       AME.  Address mark enable

       AMENBL.  Address mark enable (to U60)

       AMF.  Address mark found

       AMFD.  Address mark found (from U60)

       ANSC.  American National Standards Committee

       ANSI.  American National Standards Institute

       ASSERT.  A signal driven to the true state.

       ASYNC.  Asynchronous

       BIT.  Binary digit

       BYTE.  Eight consecutive binary digits

       CLK.  Clock

       CMD.  Command

       CMDCMP.  Command complete

       CODEIN.  Code input

       CODOUT.  Code output

       CRC.  Control register clock, or cyclic redundancy check

       CRD.  Control register data

       CRE.  Control register enable

       CSA.  Canadian Standards Association

       D/A.  Digital-to-analog
       DAC.  Digital analog converter

       DB (7-0,  P).   Eight data-bit  signals, plus a parity-bit
       signal, that form a DATA BUS.

       DC.  Direct current

       DEMOD.  Demodulator

       DET.  Determination

       DMA.  Direct memory access

       DTE.  Disable transfer on error

       DVSLTD.  Device select

       ECC.  Error correction code

       ECL.  Emitter-coupled logic

       EEC.  Enable early connection

       EIA.  Electrical Industry Association

       ENCRD.  Encoded read data

       ENDATA.  Encoded data

       ENDEC.  Encoder/decoder

       EPROM.  Erasable programmable read only memory

       ESDI.  Enhanced Small Device Interface

       EXPRCMP.  External preamble complete

       FCC.  Federal Communication Commission

       FIRMWARE.   Computer programs  encoded permanently  into a
       ROM

       FW.  Firmware

       G.  Constant of gravitation

       GND.  Ground

       HARD  ERROR.     An   error  due   to  faulty   equipment,
       transmission techniques, recording media, etc.

       HDA.  Head/disk assembly

       HEX.  Hexadecimal
       HNX, HNY.   Head  (zero through  five) input x, head (zero
       through five) input y

       HW.  Hardware

       I/O.  Input and/or output

       ISG.  Inter-sector gap

       ISO.  International Standardization Organization

       LBA.  Logical block address

       LED.  Light-emitting diode

       LSB.  Least significant bit

       MAP.  Master pulse

       MAPERR.  Master pulse error

       MAPIN.  Master pulse in

       MAPOUT.  Master pulse out

       C.  Microcomputer

       COMPUTER.  Microcomputer

       MSB.  Most significant bit

       MSIN.  Message in

       MTBF.  Mean time between failures

       MTTR.  Mean time to repair

       N.C.  No connection

       NEGATE.  A signal driven to the false state

       NOM.  Nominal

       NRZ.  Nonreturn to zero

       OEM.  Original equipment manufacturer

       ONE.  True signal value

       P/N.  Part number

       P-P.  Peak to peak
       PARITY.   A method  of checking  the  accuracy  of  binary
          numbers

       PC.  Polycarbonate

       PCB.  Printed-circuit board

       PCF.  Page control field

       PES.  Position error signal

       PLL.  Phase-locked loop

       PLO.  Phase-locked oscillator

       PM.  Preventive maintenance

       PMI.  Partial medium indicator

       POH.  Power On hours

       PRDET.  Preamble detected

       PREAMP.  Preamplifier

       PROM.  Programmable read only memory

       PTRN.  Pattern

       QUAL.  Qualification

       R/W.  Read and/or write (heads)

       RAM.  Random-access memory

       RD/REF CLK.  Read/reference clock

       RDGAT.  Read gate (to U262)

       RDGT.  Read gate

       RDRFCK.  Read/reference clock

       RDX,Y.  Read data x, read data y

       REF.  Reference

       RESERVED.   Bits, bytes,  fields and  code values that are
          set aside for future standardization.

       REVS.  Revolutions

       RFCLK.  Reference clock
       RGATE.  Read gate (to U60)

       RLL.  Run-length limited

       ROM.  Read-only memory

       RSRV.  Reserved

       SCSI.  Small Computer Systems Interface

       SLC.  Servo/logic chip

       SPEC.  Specification

       SRDX,Y.  Servo read data x, servo read data y

       STD.  Standard

       SVOCLK.  Servo clock

       SW.  Software

       SYNC.  Synchronization, synchronous

       SYNCLK.  Synchronized clock

       SYNCSP.  Synchronous spindle

       SYNDET.  Synchronized data

       TBD.   To be  determined.  Values which are not defined as
          of the date this manual is published.

       TLA.  Top level assembly

       TTL.  Transistor-transistor logic

       TYP.  Typical

       UL.  Underwriter's Laboratories, Inc.

       UNC.  Unified National Coarse

       UNF.  Unified National Fine

       UNSCODE.  Unsynchronized code

       VCO.  Voltage controlled oscillator

       VCOCLK.  VCO clock

       VDE.  Verband Deutscher Electrotechniker

       VEL.  Velocity
       VENDOR UNIQUE.   The bits, fields, or code values that are
          vendor specific.

       VREF.  Voltage reference

       WCLK.  Write clock (to U60 from interface)

       WCS.  Write current select

       WDI.  Write data input

       WGATE.  Write gate (to U60)

       WRITE*.  -WRITE to preamplifier chip

       WRT.  Write

       WRTCLK.  Write clock

       WUS.  Write unsafe output

       XFER.  Transfer

       ZERO.  False signal code

       
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