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vV2ui6`#6^#vVFuN6p#6n#vvFt  ~9&X&&e%PFPWƋFv 2PP ]	9&X& & V\2PP ]	
:&u9&X& & ˎ9&X&&k%PFPVǋFvW	3^_]UWVF ǆP  Ɔ{ ǆ8o%:ǆ<w%>ǆ@~%BǆD%FǆH%J+NL9&
&
vx~prt89
+&G&n9&9ptH9&9vt= PP9&6&6` %P9&6&6Z T 
%P|	T:& P 	FVpP 	FV+FF{{<vv~ uZ6`#6^#%P~V P~V"P~VJ]	y. However,
  we are prohibited from posting even the User's Manual due to technology
  export restrictions.

     The following is a copy of the original press release on XSPICE.  If
  anyone would like additional clarification beyond this, or if some
  aspects of the release are unclear, we can certainly take this as an
  opportunity to remedy the situation. Please note that at the current time
  there are many dozens of individuals who have obtained a copy of the
  tools; if they have any comments or observations to make, I'm sure they
  would be most welcome to other members of the user community.

                          XSPICE Press Release

                            January 2, 1993

                   Georgia Tech Research Corporation

  XSPICE, introduced at the 1992 International Symposium on Circuits and
  Systems (ISCAS), is an extended and enhanced version of the popular SPICE
  analog circuit simulation program originally developed at the University
  of California at Berkeley. XSPICE was developed at the Georgia Tech
  Research Institute (GTRI) as a tool for simulating circuits and systems
  at multiple levels of abstraction. XSPICE permits a user to simulate ana-
  log, digital, and even non-electronic designs from the circuit level
  through the system level in a single simulator.  A special Code Modeling
  feature allows users to add new models directly into the simulator exe-
  cutable for maximum simulation speed and accuracy. Code models are writ-
  ten in theecial Purpose Processor Development Group
          200 First St. S. W.
          Rochester, Minnesota 55905
          Telephone:  (507) 284-0840
          Telefax:    (507) 284-9171
          EMail:      tsmith@mayo.edu

          Point Of Contact For Acquiring General MOSIS Information
                          And Vitesse-specific Technology Information:

          Sam Reynolds
          The MOSIS Service
          USC/ISI
          4676 Admiralty Way
          Marina del Rey, CA  90292-6695
          Telephone:  (310) 822-1511 x172
          Telefax:    (310) 823-5624
          EMail:      sdreynolds@mosis.edu

50: XSPICE, extended version of Spice

  (from Jeff Murray <jm67@hydra.gatech.edu>)

     I am one of the developers of XSPICE, and at the risk of being deluged
  with requests for specific information on the tools, I can volunteer to
  answer at least some questions. Currently there is no ftp site for infor-
  mation; if there were, this posting would likely be unnecessar parameters:
     RC time constant evaluations are used to approximate real voltages by
     PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times
     for the circuit, but is also delivers an accurate representation for
     transient effects like spikes and races.

  Apart from electrical network elements like MOS transistors, resistors
  and capacitors, an SLS network may contain (i) gate primitives like
  inverters, nands, nors, etc. and (ii) user-defined function blocks like
  roms, shiftregisters, multipliers.  The behavior of function blocks is
  described by the user in the C programming language: it is specified by
  the user how the values of the output terminals and the state variables
  are computed from the values of the input terminals and the state vari-
  ables.

  For more information about SLS, see,

    "Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen,
    A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985,
    pp. 182-184

    "SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage
    waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989,
    pp. 79-88.

    "SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van
    Genderen, Delft University of Technology (available for ftp at the
    address below).

  Availability:

  SLS is written in C and runs under UNIX and X-windows.  It runs, among
  other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and
  PCs running Linux.  The program is available for free under the terms of
  the GNU General Public License.  It can be retrieved via anonymous ftp
  from the directory pub/sls on dutentb.et.tudelft.nl.

  It is also possible to obtain SLS as a part of the OCEAN system for the
  design of Sea-Of-Gates circuits.  This system can be obtained from the
  directory pub/ocean on donau.et.tudelft.nl.  The OCEAN system among other
  things contains a layout-to-circuit extractor that can extract large lay-
  outs and that stores the result directly in the database that is read by
  SLS.  Furthermore, SLS is available as a tool in the Nelsis CAD framework
  from the directory pub/nelsis on dutente.et.tudelft.nl.  The latest ver-
  sion of SLS can always be found on dutentb.et.tudelft.nl.

  For questions, remarks and bug reports, contact

    Arjan van Genderen
    Delft University of Technology
    Department of Electrical Engineering
    Mekelweg 4                          phone: 31-15-786258
    2628 CD  Delft                      fax: 31-15-623271
    The Netherlands                     email: arjan@dutentb.et.tudelft.nl

  55: OCEAN, a sea-of-gates design system

  (from Patrick Groeneveld <ocean@donau.et.tudelft.nl>)

          About OCEAN: the sea-of-gates design system
          -------------------------------------------

  OCEAN is a comprehensive chip design package which was developed at Delft
  University of Technology, the Netherlands. It includes a full set of
  powerful tools for the synthesis and verification of semi-custom sea-of-
  gates and gate-array chips.  OCEAN covers the back-end of the design tra-
  jectory: from circuit level, down to layout and a working chip. In a nut-
  shell, OCEAN has the following features:

          + Available for free, including all source code.
          + Short learning curve making it suitable for student design courses.
          + Hierarchical (full-custom-like) layout style on sea-of-gates.
          + Powerful tools for placement, routing, simulation and extraction.
          + Any combination of automatic and interactive manual layout.
          + OCEAN can handle even the largest designs.
          + Running on popular HP, Sun and 386/486 PC machines, easy
            installation.
          + Includes three sea-of-gates images with libraries and a
            200,000 transistor sea-of-gates chip.
          + Can be easily adapted to arbitrary images with any number of
layers.
          + Interface programs for other tools and systems (SIS, cadence, etc.)
          + Robust and 'combat-proven', used by hundreds of people.

   How to retrieve OCEAN and additional documentation?
   ---------------------------------------------------

  The entire OCEAN system is available for free via anonymous ftp, gopher
  or on tape. A powerful installation script is included, so you can get
  started very quickly without hacking up the code. You can retrieve OCEAN
  and additional documentation via:

          anonymous ftp: donau.et.tudelft.nl -  directory pub/ocean
          gopher:        olt.et.tudelft.nl (port 70) or use the path
                         World --> Europe --> Netherlands -->
                         Delft University of Technology Electronic Engineering
                         --> Research activities -->
                         The OCEAN sea-of-gates Design System

  We advise to retrieve first the documents with the user manual. (The file
  'ocean_docs.tar.gz').  If you have any questions, remarks or problems,
  just contact us:

          Patrick Groeneveld or Paul Stravers
          Electronic Engineering Group, Electrical Engineering Faculty
          Delft University of Technology
          Mekelweg 4, 2628 CD   Delft  The Netherlands
          Phone: +31-15786240  Fax: +31-15786190
          Email: ocean@donau.et.tudelft.nl

56: ALLIANCE, a CAD package and simulator for teaching digital VLSI design

  <from comp.lsi>

  A SPARC,LINUX and DEC version of the public domain ALLIANCE VLSI/CAD sys-
  tem is now available at:

          ftp.ibp.fr [132.227.60.2]           in /ibp/softs/masi/alliance
          ftp-masi.ibp.fr [132.227.64.26]     in /pub/cao-vlsi/alliance
          cao-vlsi.ibp.fr [132.227.60.20]     in /pub/alliance

  ALLIANCE is a complete set of CAD tools and portable libraries for teach-
  ing digital VLSI design in universities. It includes a VHDL compiler and
  simulator, logic synthesis tools, automatic place and route, etc...
  ALLIANCE is the result of a ten years effort at Universite Pierre et
  Marie Curie (PARIS 6, FRANCE)

  ALLIANCE is totally free, under the terms of the GNU General Public
  License.  It includes C source files and on-line english documentation
  (UNIX man)

  The two main improvements over the release 1.1 are:

  1) A hierarchical makefile allows to compile and install separately each
     ALLIANCE tool.
     The disk space required to compile and install the full ALLIANCE
     package is about 50 megs.
     The VHDL compiler and simulator ASIMUT requires only 3 megs.

     The source distribution is 32 Megs of which 14 Megs are sources.
     The rest is data files and documentations.
     Compiled on sparc (SunOS 4.1.1), this will give 9 megs of binaries.
     Compiled on dec (Ultrix 4.3), this will give 11 megs of binaries.
     Compiled on pc (linux-SLS 1.02), this will give 11 megs of binaries.

  2) The release 1.2 has been successfully compiled with the GNU gcc
     compiler. The full alliance package can now run on SPARC, LINUX
     and DEC architectures.

  ALLIANCE 1.2 release contains the same tools and portable libraries as
  the release 1.1, with few bugs fixed, thanks to several ALLIANCE users,
  not limited to:

    Gary Lipton (lipton@loki.ee.lafayette.edu)
    Esko Raty (Esko.Raty@vtt.fi)
    Jochen Schiller (schiller@t524e0.telematik.informatik.uni-karlsruhe.de)
    Karoubalis & vergos  KAROUBAL@GRPATVX1.BITNET
    Ludger Kunz (ludger.kunz@fernuni-hagen.de)
    Fritz Heinrichmeyer  (fritz.heinrichmeyer@fernuni-hagen.de)

  The ALLIANCE 1.2 release contains a complete tutorial: It allows to
  design the 4 bits AMD2901 processor, from the VHDL specification to the
  GDSII layout, using the ALLIANCE portable standard cell library.

  **************************************************************************

  The next release, ALLIANCE 2.0, will be distributed around december 93.

  ALLIANCE 2.0 will contains several new advanced tools and libraries:
  ALLIANCE 1.2 was dedicated to standard cell designs. ALLIANCE 2.0 will
  contains tools and libraries for high complexity, optimized circuits:

          * several parameterized CMOS generators:
              - RAGE static RAM generator
              - GROG high speed ROM generator
              - RSA  fast adder generator
              - BSG  barrel-shifter generator
              - AMG  pipelined multiplier generator
              - RFG  multi-ports register file generator

          * the data-path compiler FITPATH for high performance and high
density
            circuits (including a dedicated cell library)

          * The timing analyser EXTASE with MOTIF interface.

          * The procedural layout debugger GENVIEW allows to develop easily new
            portable generators or custom blocks.

          * The Finite State Machine Synthesiser SYF and the net-list optimizer
            NETOPTIM allow to design high complexity controllers.

          * The new, faster, symbolic layout editor GRAAL with MOTIF interface.

  The ALLIANCE 2.0 release will provide a more ambitious tutorial: The
  design of the 32 bits DLX microprocessor (PATTERSON & HENNESSY) from the
  VHDL specification to the GDSII layout, using the ALLIANCE data-path com-
  piler and logic synthesis tools.

57: ceBox EDIF Viewer

  <from comp.archives>

  A free demo version of the ceBox EDIF Viewer is now available on the
  ftp-server:

          ftp.Germany.EU.net      [192.76.144.75]

  In the directory:

          shop/concept-engineering/EDIF

  you find the following files:

          README.german                   (  2k  ASCII text)
          README.english                  (  2k  ASCII text)
          demo.edif.Z                     ( 10k  EDIF file)
          edif_viewer_demo.Z              (808k  SPARC executable)
          tutorial-demo-viewer.ps.Z       ( 31k  PostScript document)

  The  *ceBox EDIF Viewer*  displays schematic pages and symbols of any
  EDIF 200 (level 0) file. It is an easy-to-use tool to analyse EDIF
  schematic files.

  The  *ceBox EDIF Kit*  is a programming library to bundle C++ user func-
  tions to the Viewer and to build standalone EDIF processors.  The Kit's
  in-core data base allows to access/modify all EDIF data.

  For more information, please contact:

          Concept Engineering
          Burkheimer Str. 10
          D-79111 Freiburg
          Germany

          Tel: ..49-761-473099
          Fax: ..49-761-441063
          email: cebox@concept.de

58: Analog CMOS VLSI Design Educational Resource Kit

  (from MUG)

  UMass Dartmouth is pleased to announce the release of Version 1 of the
  Analog CMOS VLSI Design Educational Resource Kit.  Version 1 of the
  Resource Kit may be obtained via anonymous ftp at the site

          micron.ece.umassd.edu

  The release includes the following files and information:

  The CIF file for a 2 micron Mosis Tinychip using p-well technology; and
  manuals containing five tutorials based on the chip set.

  These circuits were used in an undergraduate course on analog VLSI design
  during the spring semester at the University of Massachusetts Dartmouth.
  They are also being currently used in a graduate level course in analog
  VLSI design.  The students in the undergraduate course had a single
  introductory digital VLSI design course as background, and were familiar
  with MAGIC, SPICE and CAzM, a SPICE-like circuit simulator.

  If you have any comments, corrections or suggestions regarding the
  release, or ideas for other circuits that you have found useful in your
  classes and that could be incorporated in later releases, please feel
  free to contact me.  Good luck!

          Robert H. Caverly, Ph.D.
          ECE Department
          University of Massachusetts Dartmouth
          N. Dartmouth, MA  02747
          caverly@micron.ece.umassd.edu
          (508) 999-8474

59: TDX Fault Simulation and Test Generation Software

  (from Dan Holt <dan@attest.com>)

  TDX Fault Simulation and Test Generation Software

  Free demo/student copies of Attest Software's fault simulation, Iddq,
  DFT, and automatic test pattern generation tools are available by
  anonymous ftp.

  This software is fully functional on any circuit with less than 1000
  gate-level primitives. It is also fully functional on the GL85 micropro-
  cessor circuit (about 3000 primitives) which is included with the suite
  of tools. General-use licenses can be provided free to accredited univer-
  sities for non-commercial, educational purposes.

  The software is built around a high-performance concurrent fault simula-
  tor that is accurate on a wide-range of state and timing sensitive cir-
  cuits. It supports synchronous and asynchronous designs containing logic
  gates, MOS transistors, tri-state buffers, flip-flops, single/multi-port
  RAMs, complex bus resolution functions, and Verilog User Defined Primi-
  tives (UDPs).  The software also supports the detailed pin timing and
  strobing features found on "tester-per-pin" automatic test equipment. The
  software supports Verilog and VHDL netlists.

  The GL85 microprocessor, which is a clone of the once-popular 8085
  microprocessor, is a fully functional model for which three views are
  provided: behavioral, RTL, and gate level.  Using this clone, a tutorial
  shows the user how to achieve improved controllability and/or observabil-
  ity for his or her circuit, resulting in improved fault coverage, some-
  times with very little additional time or effort expended in the design
  cycle. The tutorial was written by Dr. Alex Miczo.

  The software is available by ftp from netcom.netcom.com in directory
  /pub/attest. The README contains installation instructions, and identi-
  fies the location of the GL85 models and the postscript tutorial.

  For more information, please contact:

              Attest Software Inc.
              4677 Old Ironsides Drive, Suite 100
              Santa Clara CA 95054 USA

              (408) 982-0244  voice
              (408) 982-0248  fax

              info@attest.com

60: Nascent Technologies CDROM - magic and spice releases for Linux

  The Linux from Nascent CDROM, Version 1.0, is only $39.95 plus shipping
  and handling, and comes with an 30-day unconditional money-back guaran-
  tee.  If you aren't completely satisfied, return the package with your
  receipt within 30 days and the purchase price, excluding shipping and
  handling, will be refunded to you.

  In addition, Nascent offers the Linux from Nascent Plus package for only
  $89.95, which includeds six months of email support and a 30% discount
  off a future release of the CDROM with your CDROM purchase.

          Nascent Technology
          811 Haverhill Drive
          Sunnyvale CA 94087 USA
          Tel: (408) 737-9500
          Fax: (408) 241-9390
          Email: nascent@netcom.com

  Linux is a freely distributable Unix(R) compatible operating system for
  the IBM(R) 386/486 PC and compatibles written by Linus Torvalds from the
  University of Helsinki, Finland.  It was developed by a unique world-wide
  collaboration of programmers over the internet, and is covered by the GNU
  General Public License.  Linux is a modern, high performance network
  operating system, much like ones used for years on engineering and pro-
  fessional workstations.

  The Linux from Nascent CDROM is an entirely new distribution of the Linux
  operating system, and includes over 400 mbytes of source code, binaries,
  and documentation for Linux and applications.  The Linux from Nascent
  distribution features:

          * 52 page User Guide
          * automated root, swap, and package installation from CDROM
          * simple user account and network administration scripts
          * Linux 0.99.14 plus net-2 networking
          * extensive online documentation and manuals
          * network printer support
          * X Window System(TM)
          * OpenLook(TM) 3d window manager
          * SCSI disk and tape support
          * TeX(TM) and ghostscript word processor and viewer
          * Ingres database management
          * GNU C compiler and utilities
          * GNU emacs, vi clone text editors
          * sound and graphics support
          * Over 100 high resolution images translated from Kodak PhotoCD(TM)
          * magic and spice electronic design tools
          * GNU Chess, Shogi, pooltable, xpilot, flight simulator, ...

61: Time Crafter 1.0, a timing diagram documentation tool

  (from Rick Burgett <burgett@csips1.nrlssc.navy.mil>)

  I have uploaded to the SimTel Software Repository (available by anonymous
  ftp from the primary mirror site OAK.Oakland.Edu and its mirrors):

          pub/msdos/electric/
          timecrft.zip    WIN3: Electronic ckt timing diagram generator

  Time Crafter Version 1.0 is a timing diagram documentation tool.  A tim-
  ing diagram is used by electrical engineers and technicians to document
  the way a circuit or system operates or should operate.  This type of
  documentation is crucial to good design and debugging but up to now one
  could only use paper and pencil (with a good eraser) or an expensive CAD
  package costing $1000 or more to produce these diagrams on a PC.  Time
  Crafter has features that make it easy to document and update a circuit
  design of any complexity.

  Time Crafter is Microsoft Windows based to provide a simple yet powerful
  user interface which is device independent.

  Special requirements: Windows 3.x

