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%P|	T:& P 	FVpP 	FV+FF{{<vv~ uZ6`#6^#%P~V P~V"P~VJ]	Tools:

  (From John Lazzaro <lazzaro@boom.CS.Berkeley.EDU>)

                     Caltech VLSI CAD Tool Distribution

  We are offering to the Internet community a new revision of the Caltech
  electronic CAD system for analog VLSI neural networks.  This distribution
  contains tools for schematic capture, netlist creation, and analog and
  digital simulation (log), IC mask layout, extraction, and DRC (wol), sim-
  ple chip compilation (wolcomp), MOSIS fabrication request generation
  (mosis), netlist comparison (netcmp), data plotting (view) and postscript
  graphics editing (until). These tools were used exclusively for the
  design and test of all the integrated circuits described in Carver Mead's
  book "Analog VLSI and Neural Systems".  Until was used as the primary
  tool for figure creation for the book.  The distribution also contains an
  example of an analog VLSI chip that was designed and fabricated with
  these tools, and an example of an Actel field-programmable gate array
  design that was simulated and converted to Actel format with these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  Highlights of the new revision includes:

          * Ports to new platforms (Supported platforms now include: Sun SPARC,
            Sun 3, HP Series 300/400/700/800, DEC MIPS-based Ultrix, Apple
AU/X,
            linux, and IBM RS/6000 support).

          * Support for black and white displays, and resource database support
            for user preferences for sizing and placement of windows. New
            display modes in analog to support small screens.

          * Direct generation of SPICE netlists in analog, and new models
            for floating-well FET's, two-terminal devices with arbitrary i-v
            curves, and quantum-well tunnel diodes.

          * Many bug fixes for analog, wol, view, and until, and new features
            for view.

          If you are interested in some or all of these tools,

          1) ftp to hobiecat.pcmp.caltech.edu on the Internet,
          2) log in as anonymous and use your username as the password
          3) cd pub/chipmunk
          4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

  A small but rather important bug was found in the "analog" program of the
  new Chipmunk distribution announced several weeks ago -- a key MOS
  transistor parameter was off by an order of magnitude! The current copies
  of the distribution on hobiecat.caltech.edu and ifi.uio.no have this bug
  corrected; however, if you've already picked up and installed the distri-
  bution since the new release (early april), here are the directions for
  patching your current installation w/o bringing over and rebuilding the
  whole package:

          1) anonymous ftp to hobiecat.pcmp.caltech.edu, cd to pub/chipmunk
          2) get the file models.cnf
          3) in your distribution, use this file to replace log/lib/models.cnf

    That's it! Sorry for the inconvenience ...

36: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.

37: Test Software based on Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  mb@poisson.usc.edu.

38: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: 703-231-4942
             FAX: 703-231-3362
             dsha@vtvm1.cc.vt.edu

39:or DECStation and Sparcstation, although we are running it quite suc-
  cessfully at YSU under the CMS operation system on an Amdahl mainframe.

    Two new and helpful manuals are available for the simulator.  They
  should be available at the Youngstown State University Bookstore, Youngs-
  town, OHio 44555:  Their approximate cost should be $7 each:

          "WATAND Users Manual," by Dr. Phil Munro, Youngstown State
          University, April 1992, 233 pages, 10 chapters, 4 appendices,
          index.

          "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown
          State Unversity, June 1992, 204 pages, 12 chapters, index.

    Watand does *not* include digital simulation at this time, nor does it
  have any transmission-line elements.  A self-heating BJT model has been
  developed and is proving useful.  Monte Carlo statistical simulation is
  possible with dc and ac analyses using macro based analyses which have
  been developed at YSU.

35: Caltech VLSI CAD AD, connect to "eceserv0.ece.wisc.edu" using FTP.  Log
  in as "anonymous" with password "guest".  Galaxy is in directory
  "pub/galaxy".  The file "README" in that directory gives further instruc-
  tions.  Please register as a user by sending e-mail to
  "beetem@engr.wisc.edu".

  John F. Beetem
  ECE Department
  University of Wisconsin - Madison
  Madison, WI  53706
  USA
  (608) 262-6229
  beetem@engr.wisc.edu

43: WireC graphical/procedural system for schematic information

  (From Larry McMurchie <larry@cs.washington.edu>)

  WireC is a graphical specification language that combines schematics with
  procedural constructs for describing complex microelectronic systems.
  WireC allows the designer to choose the appropriate representation,
  either graphical or procedural, at a fine-grain level depending on the
  characteristics of the circuit being designed.  Drawing traditional
  schematic symbols and their interconnections provides fast intuitive
  interaction with a circuit design while procedural constructs give the
  power and flexibility to describe circuit structures algorithmically and
  allow single descriptions to represent whole families of devices.

  The procedural capability of WireC allows other CAD tools to be incor-
  porated into the design system.  For example, we have defined an inter-
  face to the SIS logic synthesis system wherein the designer can represent
  part of the system behaviorally.  WireC invokes logic synthesis on these
  components to produce a structural description that can be incorporated
  into the rest of the design.

  Libraries of devices defining a particular netlist output format may be
  defined by the user. The libraries currently distributed with WireC
  include a default CMOS gate library whose output is the SIM format.  This
  format can be simulated with COSMOS or IRSIM and compared against a cir-
  cuit extracted from layout.  This library also includes devices that
  allow a behavioral description to be synthesized and mapped using MIS or
  SIS and incorporated into a larger circuit.

  Another library is the xnf library for designing systems with Xilinx
  FPGAs.  Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
  this library contains devices specific to the 2000 and 3000 series Xilinx
  LCA's.  In addition to drawing the devices explicitly, one can represent
  parts of a circuit with equations and have these synthesized automati-
  cally.

  Currently in progress is a library of CMOS gates for Cascade Design
  Automation's ChipCrafter product.  WireC provides a mixed
  schematic/procedural design frontend for ChipCrafter, which uses module
  generation, timing analysis and place and route software to create a phy-
  sical layout from the WireC design specification.

  WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
  Tellman.  We are interested in any libraries you may develop and will
  provide a limited degree of support.

  WireC requires an X-Windows compatible environment and a C++ compiler
  such as Gnu G++ and AT&T CC.  WireC is available via ftp on the Internet.
  For details send mail to

  larry@cs.washington.edu ebeling@cs.washington.edu

44: LateX circuit symbols for schematic generation

  (From Adrian Johnstone <adrian@cs.rhbnc.ac.uk>)

  A set of circuit schematic symbols are available for use in LaTeX picture
  mode. The set includes all basic logic gates in four orientations, FETs,
  power supply pins, transmission gates, capacitors, resistors and wiring
  T-junctions. All pins are on a 1mm grid and the symbols are designed to
  be easily used with Georg Horn's TeXcad program: we even supply you with
  a palette picture file that displays all 52 symbols in a compact grid
  that you can cut and paste from within TeXcad. Each symbol lives in its
  own .mac file and is defined as a 'savebox' so as to reduce memory con-
  sumption. You must add the [bezier] option to your 'documentstyle' com-
  mand. A small manual is provided in both Postscript and .dvi forms.

  The files lcircuit.zip and lcircuit.tar are available for anonymous ftp
  from cscx.cs.rhbnc.ac.uk (134.219.200.45) in directory pub/lcircuit. I
  will also be uploading them to various ftp servers in the coming week.

45: Tanner Research Tools (Ledit and LVS)

  (From Bhusan Gupta <bgupta@micro.caltech.edu>)

  Low cost, yet very powerful commercial ASIC design tools are available
  from Tanner Research, Inc. in Pasadena, CA.  These products are used by
  industry and universities alike.  Tanner's products are nominally priced
  at $995 per program, with a combined package named L-Edit Pro available
  for $3,495 on the PC.  Universities are offered a 75% discount.  Here is
  a list of their current programs:

  L-EditTM :      A full-custom layout editor with CIF and GDSII
                  input/output.  Features a 32-bit coordinate space,
                  all-angle geometry, unlimited hierarchy and number
                  of layers.  The L-Edit Pro package includes L-Edit/DRC
                  for design rule checking, L-Edit/SPR for automatic
                  standard cell placement and routing, L-Edit/Extract
                  for extracting transistors, capacitors, resistors and
                  generic devices for SPICE-level simulation or comparison
                  to a schematic and LVS ,a netlist comparison tool for
                  topological and parametrical verification.  Optional
                  layout libraries are also available.

  T-Spice:        Circuit level simulator (See item 41 for detail

  GateSimTM :     Gate-level simulator.  A full array of technology mapping
                  libraries are also available.

  Products are available for the PC, Macintosh, Sun and Hp UNIX platforms.
  For more information contact Bhushan Mudbhary at Tanner Research (bhushan
  @ tanner.com), phone 818-792-3000 and fax 818-792-0300.

46: SIMIC, a full-featured logic verification simulator.

  (From comp.archives.msdos.announce)

  SIMIC is a full-featured logic verification simulator.  It has been
  demonstrated that SIMIC can uncover a number of critical design errors
  that other simulators miss.  SIMIC has shown superior accuracy and
  throughput when compared to competitive products.  Here are some of
  SIMIC's important features:

  -  Mixed-mode simulation allows the free intermixture of true
     bilateral switches (ideal and resistive), gate, plus functional level
     built-in and user defined primitives.

  -  A wide variety of output, whose detail, content and format are, to
     large extent, user defined.

  -  A large repetoire of simulation options and controls that can be
     applied interactively, or in batch operation, and simplify
     trouble-shooting of your design.

  -  Automated Test equipment emulation, allows debugging test programs
     using SIMIC troubleshooting techniques.

  -  Sophisticated hazard analysis including:  Spike, Pulse, Conflict,
     Oscillation, Setup, Hold, Pulse-width, Near (what-if)
     detection, among others.  Hazard propagation is also supported.

  The student version of SIMIC is limited to a maximum of 500 elements
  (parts).  In all other respects it is the same program as the commercial
  offering.  The PC student version requires a 386 or better and at least 2
  Meg of memory.  Both a DPMI and a VCPI version are included in the pack-
  age.  Both versions require EMS *NOT* be disabled.  SIMIC is also avail-
  able on Sun and other platforms.

  The latest version is 1.02.00. The changes from revision 1.00.04 are:

          Bug Fixes:
               - Rams properly handled by circuit compiler.
               - BTG (Ideal switches) compiled correctly with dynamic delays.
               - By-name pin connections accepted by circuit compiler.
               - JK Flip-flop timing checks can now be disabled.
          Enhancements:
               - Reduction in storage requirements for small RAMS.
               - Fault Sensitization analysis added.
               - Fault Simulation and grading added.

  This revision can be taken from oak.oakland.edu in pub/msdos/electrical,
  or wuarchive.wustl.edu in mirrors/msdos/electrical. The files in question
  are sim120bn.zip (Simic logic and fault simulator plus examples) and
  sim120dc.zip (Simic Engineering and User's Guides).

47: LASI CAD System, IC and device layout for IBM compatibles

  (from Mike Fitsimmons <mikef@hendrix.ece.uiuc.edu>)

  On behalf of the author I have uploaded to WSMR-SIMTEL20.Army.Mil:

  pd1:<msdos.cad> LASI41A.ZIP     LASI v4.1 IC layout CAD prgm: unzip in
  LASI41B.ZIP     LASI v4.1 IC layout CAD prgm: unzip in LASI41C.ZIP
  LASI v4.1 IC layout CAD prgm: unzip in LASIDEMO.ZIP    LASI v4.1 DEMO
  drawing: unzip in

  The LASI CAD System has been developed to do integrated circuit and dev-
  ice layout on almost any IBM compatable personal computer.

  LASIDEMO is a small IC layout to be used as a demonstration when first
  learning to use LASI.

  I offered to pay the author for some sort of site license for this pro-
  gram, but he refused, saying that he actually wants educational institu-
  tions to use it for free.  What a guy!

48: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles

  (from <pcc@minster.york.ac.uk>)

  I have uploaded to WSMR-SIMTEL20.Army.Mil:

  pd1:<msdos.graphics> EEDRAW24.ZIP    Electrical Engineering drawing (with
  layers)

  This is the 2.4 release of EEDRAW, an electrical/electronic diagramming
  tool for the IBM PC.

  pd1:<msdos.graphics> EEDSRC24.ZIP    C sources for EEDRAW24.ZIP program.
  TC/BC++

  This is the source of the EEdraw 2.4 program. Please read the readme file
  in the primary archive for information on other source programs needed
  such as the Libary files.

49: MagiCAD, GaAs Gate Array Design through MOSIS

  (from Tom Smith <tsmith@mayo.edu>)

  The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system is a
  package which provides a comprehensive design environment for the
  development of digital systems, from initial concept to post-layout
  verification of integrated circuits (ICs).  MagiCAD focuses on the
  development of high-speed Gallium Arsenide (GaAs) gate array designs.
  Specialized electromagnetic simulation tools are provided to address high
  clock rate issues such as crosstalk and reflections, which become more
  important as clock rates exceed several hundred MHz or signal edge rates
  become less than 500 pico- seconds. MagiCAD provides all the necessary
  tools for high clock rate GaAs IC design, and is also integrated with
  non-Mayo circuit, logic, and fault simulators.

  MagiCAD provides a lower risk approach than full-custom design for
  universities wishing to perform digital GaAs design through MOSIS.  This
  is done by providing a gate array design environment where low-level
  transistor design and layout issues have already been solved and
  abstracted into a technology library of pre-defined cells. This frees the
  student or researcher to solve the still challenging tasks of system and
  gate-level design and layout to get high clock rate chips fabricated
  through MOSIS that meet all specifications.

  MagiCAD supports hierarchical, top-down, middle-out, or bottom-up
  development styles. MagiCAD has been used in the design of many GaAs
  chips that have been successfully fabricated. The MagiCAD electromagnetic
  modeling tools have been used in the analysis of many actual packages,
  multi-chip modules (MCMs), and printed circuit boards (PCBs), uncovering
  and avoiding problems that are commonly associated with high-frequency,
  fast edge-rate designs. The Vitesse Fury (TM) GaAs VSC2K gate array is
  provided as a MagiCAD technology library, and has been used for both gra-
  duate and undergraduate student chip designs.

  Functionality that has been integrated into MagiCAD includes:

            o  Vitesse VSC2K GaAs gate array technology library
            o  Database which integrates all tools
            o  Schematic entry through a general purpose graphics editor
            o  Circuit simulator
            o  Logic and timing simulators
            o  Fault analysis
            o  Place and route tools
            o  Layout verification tools
            o  Retargeting from generic design to specific technology
            o  Output to standard GDSII format for mask creation
            o  Electromagnetic analysis
               -  Cross section entry with graphics editor
               -  Multilayer multiconductor transmission line (MMTL) modeling
               -  Network tool for solving cases with many transmission line
                  components
               -  Lossy and non-lossy cases
               -  Frequency and time domain result displays
               -  Used for analyzing complex design paths, through chip, MCM,
                  and PCB

          The Vitesse VSC2K has the following characteristics:

            o  HGaAs-2 (TM) process                    o  2700 available gates
            o  Enhancement/depletion MESFET process    o  80 signal pads
            o  2 GHz flip-flop toggle rates            o  40 power, ground pads
            o  280 psec loaded gate delays             o  2.4 watts maximum
            o  170 mils x 135 mils                     o  ECL or TTL I/O
            o  132 pin LDCC package available          o  2 routing layers

