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:&uvv` 	t|]	u	t 	3P(	-* ui%PvV
vV2ui6`#6^#vVFuN6p#6n#vvFt  ~9&X&&e%PFPWƋFv 2PP ]	9&X& & V\2PP ]	
:&u9&X& & ˎ9&X&&k%PFPVǋFvW	3^_]UWVF ǆP  Ɔ{ ǆ8o%:ǆ<w%>ǆ@~%BǆD%FǆH%J+NL9&
&
vx~prt89
+&G&n9&9ptH9&9vt= PP9&6&6` %P9&6&6Z T 
%P|	T:& P 	FVpP 	FV+FF{{<vv~ uZ6`#6^#%P~V P~V"P~VJ]	tesla.ee.cornell.edu in /pub/cad/pplot.tar.Z. It only generates PS files
  (including color PS), and there's no support for EPS files.  It is lim-
  ited in its support of cif commands.  (Wire, roundflash, and delete are
  not supported.)  It only supports manhattan geometry (Polygons and rota-
  tions may only be in 90 degree multiples.)

  vic:

  Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad
  Tool Release (previously UW/NW VLSI Consortium).  Does postscript and HP
  pen plotters.  Only available as part of the package.

  CIF/Magic -> EPS -> groff/latex

  Currently no prgram here directly generates EPS files.  It is possible to
  add an EPS bounding box (%% BoundingBox: l t b r) to the output from
  these programs to get an EPS file.  Alternatively, ps2eps or ps2epsf may
  be used.

6: What tools are used to layout verification?

  Gemini:

  Gemini is a graph isomorphism tool for comparing circuit wirelists.  The
  latest version of Gemini is 2.7 and is now available by FTP from
  shrimp.cs.washington.edu (128.95.1.99).  Note: Gemini is not available by
  anonymous FTP.  Send email to Larry McMurchie (larry@cs.washington.edu)
  if you need the FTP login and password for Gemini.

  Version 2.7 includes a new SIM file format to support four-terminal MOS
  transistors.  This format is called 'LBL' and was inspired by Mario
  Aranha at Lawrence Berkeley Labs.  Also some minor bugs have been fixed
  concerning portability.  The user guide 'gemuser.ps' has been updated to
  reflect the changes to the code.

  Gemini compiles and runs on a wide variety of architectures, including
  Sparc, Mips, DEC AXP, HP, KSR, Intel i860, MC 68020 and VAX, under both
  Classic C and ANSI C compliant compilers.  As the number of architectures
  continues to expand, new portability problems are revealed.  Please keep
  us informed if you encounter any portability problems or bugs.

  Contact:

          Larry McMurchie
          Computer Science Department, FR-35
          University of Washington
          Seattle, WA  98195
          larry@cs.washington.edu

  Tanner LVS:

  This is a relatively inexpensive commercial product, see the section on
  Tanner tools.

  Wellchecker:

  (from MUG) ftp ftp.mosis.edu (128.9.0.32)

  netcmp:

  Part of the caltech tools (see the "Caltech VLSI CAD Tools" section)

7: EDIF data exchange format.

  (From Nigel Whitaker <nigelw@computer-science.manchester.ac.uk>)

  A draft version of EDIF Version 3.0.0 was announed/released at the Design
  Automation Conference (DAC) at Dallas, Texas, 16/6/93.

  New Reference Manuals and EXPRESS information models for this new version
  of EDIF are available from the EIA:

  Electronic Industries Association Standard Sales Department (Attn:
  Cecelia Fleming) 2001 Pennsylvania Avenue, N.W.  Washington D.C. 20006,
  USA

  An electronic copy of the BNF, together with other EDIF related informa-
  tion such as tests files and EDIF documents can be obtained by anonymous
  ftp from edif.cs.man.ac.uk in subdirectories of /pub/edif. However, an
  electronic copy of the BNF for version 3.0.0 is not available via
  anonymous ftp.  A copy can be obtained on a floppy directly from the EIA.
  The BNF of earlier versions of EDIF are available.  You can get the offi-
  cial line on this by mailing edif-support@cs.man.ac.uk

  An ftpmail server is provided for those without ftp access.  Send an
  empty email message to: ftpmail@cs.man.ac.uk ; a message describing the
  commands which can be used in further email messages to retreive files
  will be sent to you.

  An electonic mailing list is available to people interested in EDIF and
  for EDIF developers/programmers.  Send email to edif-users-
  request@cs.man.ac.uk to be added.

  EDIF version 2.0.0 is the standard in use; version 3.0.0 is still under-
  going changes.

  The EDIF Technical Centre (based at the University of Manchester and
  funded by the CEC as part of ESPRIT 2072 -- ECIP) can be contacted by the
  following means:

  EDIF Technical Centre, Depeartment of Computer Science University of Man-
  chester, Manchester, M13 9PL, UK

  Tel: +44 61 275 6289 FAX: +44 61 275 6280 e-mail: edif-
  support@cs.man.ac.uk

8: What layout examples are available?

  From MUG:

  Analog neural network library of cells, 66-bit Manchester carry-skip
  adder, static ram fabricated at 2-micron, an analog op amp, ftp
  ftp.mosis.edu (128.9.0.32) Located in pub/mug.

9: How can I get my lsi design fabbed and how much will it cost?

  See section on mosis fabrication services as well.

  (From chiang@m2c.org <Rit Chiang>) M2C can also provide low-cost, low-
  volume prototyping fab services.  The current technology available to the
  public is the  2um NWell single-poly double-metal process.

  For pricing information and fab schedule, please send e-mail to
  hotline@m2c.org.

  Unfortunately, the fab line is currently inactive.  We have no informa-
  tion as to when the fab will be back up.

  (From MUG 20 George Lewicki of Orbit Semiconductor)

  Orbit Semiconductor operates an integrated circuit prototyping service
  that accepts designs each week for all of its processes.  The service is
  available to both U.S. and non-U.S. designers. In- quiries about the
  FORESIGHT prototyping service should be ad- dressed to George Lewicki.
  Designs can now be submitted directly via email.

              Orbit Semiconductor, Inc.
              1215 Bordeaux Drive
              Sunnyvale, CA 94089
              TEL: (408)-744-1800
              FAX: (408)-747-1263
              Email: foresight@orbsemi.com

  (Contributed by Don Bouldin of the University of Tennessee)

  Recently, I contacted several foundries to determine  which  com- panies
  are  interested  in fabricating small to moderate lots of wafers for cus-
  tom CMOS designs.  I believe many of the readers of this  column are
  designers who wish to have fabricated only 1,000 to 20,000 parts per
  year.  There are currently several  prototyp- ing  services  (e.g. MOSIS
  and Orbit) that can produce fewer than 100 parts for about $100 each and
  there are  also  several  foun- dries  which  are willing to produce
  100,000 custom parts for $5- $20 each (depending on the die size and
  yield).  My  purpose  was to  identify  those companies filling the large
  gap between these two services.

  The prices in the table below are a result of averaging the  data sup-
  plied by four foundries.  The raw data varied by more than +/- 40% so the
  information should be used only in the early stages of budgetary  plan-
  ning.   Once  the design specifications are fairly well known, the
  designer should contact one or more foundries  to obtain  specific
  budgetary  quotes.  As the design nears comple- tion, binding quotes can
  then be obtained.

  The following assumptions were made by the foundries:

  All designs will require custom CMOS wafer  fabrication  using  a
  double-metal, single-poly process with a feature size between 2.0 and 1.2
  microns.  The designs may contain some  analog  circuitry and  some  RAM
  so the yield has been calculated pessimistically.  The dies will be pack-
  aged and tested at 1  MHz  using  a  Sentry- type digital tester for 5-10
  seconds per part.  The customer will furnish the test vectors.

          Piece Price includes Wafer Fabrication+Die Packaging+Part Testing
          Size        Package                      Quantity

                                 |1,000 | 5,000 | 10,000 | 20,000  |100,000
          -----------------------------------------------------------------
          2 mm x 2 mm; 84 PLCC:  | $ 27 | $  6  |  $  5  |  $  4   | $  3 |
          5 mm x 5 mm; 84 PLCC:  | $ 31 | $ 12  |  $  8  |  $  7   | $  6 |
          5 mm x 5 mm; 132 PGA:  | $ 49 | $ 30  |  $ 25  |  $ 22   | $ 18 |
          7 mm x 7 mm; 132 PGA:  | $ 65 | $ 44  |  $ 36  |  $ 31   | $ 27 |

          Lithography charges:  $ 20,000 - $ 40,000
          Preferred Formats:  GDS-II or  CIF Tapes
          Additional charges for Second-Poly:  $ 5,000

  (This is from MUG 19, there is also a list of foundries that these prices
  were derived from.  In the interested of saving space, I have ommitted
  the list.  The list is available from MUG's ftp site included in MUG
  newsletter #19.)

10: Mosis fabrication services.

  (From Mosis) Information is available from mosis for pricing and fab
  schedules through an automatic email system:

  Mail to mosis@mosis.edu with the message body as follows:

          REQUEST: INFORMATION
          TOPIC: TOPICS
          REQUEST: END

  for general information and a list of available topics.

  If you need to contact a person at mosis, you may mail to mosis@mosis.edu
  with REQUEST: ATTENTION.

  Also anonymous ftp is available. ftp to ftp.mosis.edu.  This is a dupli-
  cation of all files that are available from the mail server.

  (From MUG 20 Contributed by Don Bouldin of the University of Tennessee)

  Multi-proje.eng.ohio-state.edu> and Harry
  Langenbacher <harry@neuronz.Jpl.Nasa.Gov>, for feedback here.)

  CIF:

  CIF stands for CalTech Intermediate Form. It's a graphics language which
  can be used to describe integrated circuit layouts.

  cif2ps  version 2 (Gordon W. Ross, MITRE):

  A much better version of cif2ps, extending the code of cif2ps (Marc
  Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace
  Corp).  It features command line options for depth and formatting.  Can
  extend one plot over several pages (up to 5 by 5, or 25 pages). By
  default, uses a mixture of postscript gray fill and cross-hatching.
  Options include rotating the image, selecting the hierarchy depth to
  plot, and plotting style customization.  Plots are in B/W only.

  It was posted to comp.sources.misc, and is available by ftp from
  uunet.uu.net(192.48.96.2) as: comp.sources.misc/volume8/cif2ps.Z.

  cifplot:

  Cifplot plots CIF format files on a screen, printer or plotter.  Cifplot
  reads the .cif file, generates a b/w or color raster dump, and sends it
  to the printer.  Plots can be scaled, clipped, or rotated.  Hierarchy
  depth is selectable, as well as the choice of colormap or fill pattern.
  An option exists which will compress raster data to reduce the required
  disk space.  For those plotting to a Versatec plotter, there is also a
  printer filter/driver available called vdmp.

  cifplot (m2c version, from chiang@m2c.org <Rit Chiang>):

  The cifplot program from M2C is not in public domain.  However, we do
  provide P.D. CAD tools to university for a fee of $2500/year to cover our
  cost on distribution, telephone hotline support, documentation and
  tutorials, etc., under our CUME (Clearinghouse for Undergraduate
  Microelectronics Education) program.  This program, in the past, was sub-
  sidized by NSF.

  The cifplot program was modified by M2C to support plotting for B&W
  PostScript and color PostScript printers, besides the versatec plotters.
  We also provide plotting services for people who sent us a cif file.  The
  cost is $20/per 24" color versatec plot for University and $50 for oth-
  ers.

  For more information on the CUME program or the plotting service, please
  send e-mail to hotline@m2c.org.

  oct2ps (available as part of the octtools distribution):

  It is possible to convert your .mag file to octtools, and then you may
  use oct2ps to print it.

  Both cif2ps and oct2ps work well for conversion to postscript.  They do
  look slightly different, so pick your favorite.  Note that cif2ps can be
  converted to adobe encapsulated postscript easily by adding a bounding
  box comment.  oct2ps does convert to color postscript, which can be a
  plus for those of you with color postscript printers.

  Flea:

  Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot
  magic and cif design files to various output devices. Parameters are
  passed to flea through the flags and flag data or through .flearc files
  and tech files.  Supports: HP7580 plotter, HP7550 hpgl file output,
  HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out-
  put, Versatec versaplot random output.  Options include: Does line draw-
  ings with crosshatching for postscript, versatec, and hp plotters.  Many
  options (depth, label depth, scale, path, format...)

  Available by ftp from zeus.ee.msstate.edu in pub/flea.tar.Z.

  pplot:

  Can output color PostScript from CIF files. The source is available from:
  gest circulation daily in the U.K.) ...

  Time, Newsweek, U.S. News & World Report ...

  Business Week, Forbes, Fortune, The Economist (London), Nikkei Weekly
  (Tokyo), Asian Wall Street Journal (Hong Kong) ...

  over 50 trade magazines, including Computerworld, InfoWorld, Datamation,
  PC Week, Dr. Dobb's Journal, LAN Times, Communications Week, Electronic
  Engineering Times, New Media, VAR Business, Midrange Systems, Byte ...

  over 50 research journals, including ALL publications of the IEEE Com-
  puter and Communications Societies, plus technical journals published by
  AT&T, IBM, Hewlett Packard, Fujitsu, Sharp, NTT, Siemens, Philips, GEC
  ...

  over 100 Internet mailing lists & USENET discussion groups, plus ...

  listings of forthcoming & recently published technical books and forth-
  coming trade shows & technical conferences

  BONUS:

  Exclusive interviews with technology pioneers ... the next issue features
  an interview with Mark Weiser, head of Xerox PARC's Computer Science Lab.

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13: Simulation programs tips/tricks/bugs

  Berkeley spice:

  Pspice:

  Hspice:

  If your simulation won't converge for a given DC input, you can ramp the
  input and print the DC operating point and then set the nodes that way
  for future simulations.

  A number of documents are available for information on BSIM model parame-
  ters: (from Mark Johnson, as posted to comp.lsi <mjohnson@netcom.com>)

  1. The very best written description I have seen is in a software manual.
     The good news is that this manual is free; the bad news is that you
     have to buy the multi-thousand-dollar program in order to get the free
     manual.  The program is HSPICE from Meta-Software Inc (Campbell,
     Calif., USA).  The HSPICE User's Manual, chapter 7, gives all the
     details you'd ever want to know regarding BSIM parameters.

  2. The second best description I have seen of BSIM is in, strangely
     enough, a manual for BSIM2 (!).  It is available from the University
     of California at Berkeley.  Telephone (510)-643-6687 and they will
     give you instructions on how to buy the manual.  (They'll probably
     suggest that you might want to buy some software too).

             J.S. Duster, M.C. Jeng, P.K. Ko, and C. Hu, "Users
             Guide for the BSIM2 Parameter Extraction Program and
             the SPICE3 with BSIM Implementation"

  3. You can learn some things about BSIM parameters by reading about pro-
     grams which extract the parameters from measured data.  UC Berkeley
     offers several programs and manuals for this.  The one that I person-
     ally prefer is

             M.C. Jeng, B.J. Sheu, and P.K. Ko: "BSIM Parameter
             Extraction - Algorithms and User's Guide," Memo
             No. UCB/ERL M85/79, 7 October 1985.

  4. Next, look at Sheu's Ph.D. thesis.  He is the guy who combined the
     Bell Labs CSIM model with a bunch of other published equations, and
     formulated BSIM.  It's available from the same phone number.

             B.J. Sheu, "MOS Transistor Modelling and Characterization
             for Circuit Simulation", Memo No. UCB/ERL M85/85,
             26 October 1985

  5. The worst description (in +my+ opinion of course) is unfortunately in
     the most-accessible publication.  To save space in the journal they
     left out some parameter discussions and (again in my opinion) produced
     a disjointed, not-fully- informative paper.  Others may have different
     views, naturally.

             B.J. Sheu, D.L. Scharfetter, P-K Ko, M-C Jeng, "BSIM:
             Berkeley Short-Channel IGFET Model for MOS Transistors,"
             IEEE Journal of Solid-State Circuits, Vol SC-22, No. 4,
             August 1987, pp. 558-565.

14: Getting the latest version of the FAQ:

  Mail to clcfaq@eecs.ucdavis.edu with the subject "send faq".

  If you wish to be added to the FAQ mailing list, send a note to
  clcfaq@eecs.ucdavis.edu with subject heading 'Subscribe'. You will then
  have the FAQ regularly emailed to the return address of the note. Like-
  wise, use the subject heading 'Unsubscribe' to be removed from the list.

  This FAQ is now cross-posted to news.answers and comp.answers. This news-
  group is archived periodically on rtfm.mit.edu [18.70.0.209].  Postings
  are located in the anonymous ftp directory /pub/usenet/news.answers, and
  are archived as "lsi-cad-faq/part1" through "lsi-cad-faq/part4".

  (from Thomas A. Fine <fine@cis.ohio-state.edu>)

  WWW I maintain an "archive" of news.answers available via WWW.  As a
  matter of fact, I used WWW to read through your posting just last week.
  I found it very informative; thanks much.  Advertise the following refer-
  ence to get to the archive in general:
    http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/FAQ-List.html

  or to get to your particular FAQ, give out this reference:
    http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/lsi-cad-
  faq/top.html

  Gopher The news.answers introduction (which I pulled up in WWW ;-) lists
  the following gopher sites for the FAQs:

              cc1.kuleuven.ac.be port 70
              jupiter.sun.csd.unb.ca port 70
              gopher.univ-lyon1.fr, port 70
              ftp.win.tue.nl, port 70
              gopher.win.tue.nl, port 70

  WAIS

  I pulled this straight out of the news.answers Introduction:

  Note that the periodic posting archives on rtfm.mit.edu are also accessi-
  ble via WAIS (the database name is "usenet" on port 210).  If you don't
  know what WAIS is, don't worry about it, although you can look in
