QuickLogic adds Fastest VHDL Synthesis to QuickWorks FPGA Tools

- QuickWorks users now have both VHDL and Verilog -

SANTA CLARA, Calif. - September 11, 1995 - QuickLogic Corporation, the FPGA
(Field Programmable Gate Array) technology and design tool leader, today
announced support for VHDL with the production release of the new 5.1
version of its successful QuickWorks development software suite.

VHDL and Verilog are new technologies for most programmable logic
designers, so QuickLogic has focused on productivity for that new user,
while providing experienced users a level of sophistication not available
elsewhere. By adding IEEE 1076 VHDL support to its current OVI 2.0 Verilog
path, the windows-based QuickWorks development environment is unmatched in
capability or value at just $2995.

QuickLogic is the first FPGA vendor to offer the designer the choice of
either VHDL or Verilog by including support for both in a single tool
suite. Synthesis results comparable to the performance and silicon use of
a typical schematic are produced in minutes after a few mouse clicks in
the simple user interface of Synplify-Lite from synthesis partner
Synplicity, Inc. Module generation targeted for the QuickLogic
architecture plays a key role in the efficiency of the synthesis path.

"We haven't yet found a design where the quality of the synthesis result is
better from any other tool, regardless of its price or platform " said
John Birkner, vice president of CAE at QuickLogic. He continued with "The
key to quality synthesis in the future, and a requirement for the vendor
independence HDLs promise, will be optimized silicon vendor supplied
libraries of functions such as counters, adders, multiplexors, and
comparators. QuickLogic is taking the lead by bundling the ability to
generate LPM modules (Libraries of Parameterized Modules), and accept LPM
netlists from third party tools with every development toolkit we sell."

The improved QuickTools module of the tool suite continues a commitment to
third party interoperability with support for VITAL, the VHDL simulation
standard. Back annotation of guaranteed accurate timing values is made in
the standard .SDF format to simulators such as Model Technology's V-System
and Synopsys' VSS. QuickTools' technology mapper and multiple levels of
optimization remove inefficiencies remaining after design entry and
synthesis. This includes an automatic, optimal buffer insertion capability
which improves the performance of paths with high signal loading without
the manual intervention required by other manufacturers of FPGAs. The
ability to always route a design, with all logic cells utilized and
pre-assigned pin-outs, continues to be a key benefit for QuickLogic
users.

A Verilog Simulation Environment with a Source-Level Debug mode is a first
for any vendor's programmable logic tools. Sophisticated capabilities like
executing single Verilog commands at a time and setting breakpoints are
complimented with state of the art "Drag and Drop" capabilities for signal
monitoring. Clicking on a signal name in the Verilog source code window,
then dragging it to either the waveform display or signal watch windows
produces the simulation results for that signal. A hierarchical browser
provides a visual representation of the hierarchy of a design's functional
modules and dependencies allowing easier navigation through the design as
debug progresses. These capabilities come through the integration of
SimuCAD's fast SILOS III simulator which also supports full interactive
cross-probing between simulation waveforms and the schematic.

Users new to VHDL and Verilog will find QuickLogic's language sensitive
editor's templates invaluable for design entry productivity as statements
are automatically completed, then configured with the appropriate
parameter fields after being triggered by the first few letters of a
command. Automatic real-time syntax checking, color coding of key words
and parameter fields, and the appropriate indenting of statements are all
features of the language editor. Syntax errors found during behavioral
simulation are automatically color highlighted in the edit window. A VHDL
or Verilog test bench can then be automatically generated, greatly
expediting the simulation process.

An enhanced user interface with toolbar icons has been added to the fully
integrated QuickWorks schematic entry package (Data I/O's Synario Capture
System). The best design entry choice can be made by logical function
since modules of VHDL or Verilog code can be embedded into a schematic
drawing. These mixed mode designs are fully supported by the synthesis,
place & route and simulation tools which all protect the hierarchy of the
design regardless of its' entry technique.

"The integration of capabilities like language entry templates, high
quality 'push-button' synthesis and full featured source-level debug and
simulation environments, coupled with full communication between open tool
windows lets QuickLogic guarantee the highest design productivity." said
Ed Smith QuickLogic's director of marketing. "Higher capacity programmable
logic devices have driven design methodologies toward HDL synthesis and
simulation, both of which are effectively addressed by QuickWorks alone,
or in tandem with a customers' third party environment." added Tom Hart,
QuickLogic's president and CEO. "Our leadership role in FPGA design
productivity coupled with our device architectures and technologies allow
us to state that QuickLogic is "Leading the Revolution in FPGAs".

PRICE & AVAILABILITY

The QuickWorks 5.1 package is priced at $2995 ($3995 with device
programmer), and is available through any of QuickLogic's sales
representatives or distributors. Current QuickWorks customers still under
software warranty or software maintenance will be upgraded in September at
no charge.

ABOUT QUICKLOGIC

QuickLogic Corporation designs, manufactures and markets the industry's
fastest FPGAs (Field Programmable Gate Arrays) and high-productivity
design tools. Proprietary strengths in device architectures, metal-
to-metal antifuse technology (ViaLink), and leading-edge QuickWorks&#153;
design software, combined

with QuickLogic's pASIC 1 family of 0.65 micron FPGAs result in the
industry's fastest time-to-market solution. By solving the problems of
using traditional FPGAs, QuickLogic is leading the revolution in FPGAs
with fully routable devices, predictable/consistent timing, pin-out
maintainability, and quality HDL synthesis with cost-effective devices.
QuickLogic is located at 2933 Bunker Hill Lane, Santa Clara, CA 95054.
Phone: (408) 987-2000; fax: (408) 987-2012.

The toll-free line for literature is (800) 842-3742.
 
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