.lb:12 ========================================================================== BOOK 1 ...FUTURE SYSTEMS by MARK T. NADIR ... PAGE $$$ ========================================================================== CHAPTER 10 THE TIMING CHAIN SYNCHRONIZING SYSTEM, CLOCK, AND MODEM INTRODUCTION 1 In order to comprehend the operation of PTM SysTems on a non-theoret ical basis, the physical operation of the uniplexer must be first un derstood. ˙If YOU believe you have ˙no interest in the mechanical (or hardware) implementation then you can skip this chapter. So, proceed at your own risk. (ha-ha) 2 Timing chains and ˙the synchronizing systems are the sole topics ˙of this ˙chapter. ˙The timing chains and synchonizing circuits have been mentioned several times in the preceding chapters but were not close ly ˙examined. ˙We will do so now. ˙Since the timing chains for the ˙B Modes are not the same as the timing chains for the A Modes they will be ˙explained and compared. ˙Their differences are important and will continue ˙to grow in the same direction (i.e. increase) as we go from Beta to Gamma Modes to Delta Modes, etc. 3 Two block diagrams of the timing chains for the B Modes are shown in figures 20A and 20B. ˙Figure 20A is the block the timing chain of the basic timing chain whereas in figure 20B a more complete timing chain for B Mode SysTems is shown. ˙The feedback path required for synchon ization is included. ˙The same pair of timing chains for A Modes sys tems are shown in figures 21A and 21B for comparision. 4 The complete timing chain for the B Mode SysTems are comprised of the following blocks [1] The Marker Detector, [2] the Address Bits-Count er, [3] The Address Counter, [4] The Data Nest Counter, [5] the char acter-set Counter, [6] the Q Counter, ˙and [7] the Read-Only-Memory. These are shown the in figures of 20. ˙The rest of the uniplexer cir cuits are not shown. 5 The timing chain for the Alpha Modes has only five of the seven tim ing chain blocks required for the Beta Modes timing chains. The Alpha timing chain ˙is ˙comprised of only the following blocks: ˙˙[1] ˙The Marker Detector, [2] the Address Bits-Counter, ˙[3] the Character-set Counter, [4] the "Q" Counter, and [5] the Read-Only-Memory (ROM). 6 The Marker Detector* is really part of the synchronizing (sync) sub- system. We must come back to it. ˙The function of the Marker Detector is to detect the Marker Signal and to start the timing chain when the Marker signal has been correctly detected. (In code systems the Mark er is called ˙the "synchronizing signal" ˙or just the "sync" signal.) When the ˙Marker is detected it indicates (to the hardware) ˙that the timing chain must ˙be started because the timing signal has been cor rectly ˙received. ˙˙The normal sequence of events is then allowed ˙to proceed as usual. (˙The Marker Detector also ˙drives ˙the "SYNC HUNT" circuits which are discussed later.) 7 If one or more extraneous bits gets onto the transmission path (which is usually due to noise) ˙the Marker (sync) can get "lost" (i.e. lost track ˙of). ˙The same effect occurs when noise wipes out one or ˙more bits. ˙In either ˙case ˙the result is that the Marker signal's timing will be thrown off and arrive at the wrong time. When this occurs the Marker is said to be "lost" ˙or "lost track of". ˙Also, if the timing chain momentarily fails, ˙the Marker will be lost. In either case the Marker is lost and correct timing must be restored somehow. ˙The Sync Hunt ˙circuits ˙are now called upon to "find" ˙(i.e re-locate) ˙˙the "missing" ˙˙sync signal (really the missed sync signal.) ˙When it ˙is "found" ˙the timing is "restored". ˙The circuits that actually locate and/or re-locate the Marker signal are described below. 8 When a Marker signal is correctly detected a "Start Pulse" ˙is gener ated ˙by ˙the Marker Detector. ˙That pulse starts ˙the ˙timing ˙chain (which ˙will normally come to a stop if not re-started periodically). The Start pulse ˙from ˙the Marker Detector ˙also signals all the uni plexer circuits (via the timing chain) when the time is correct start for entering various item ˙of ˙data into ˙the ˙SysTem ˙(via the shift register) ˙and/or to begin looking for its own (local) address in the shift register. (The start pulse ˙from the ˙Marker ˙Detector directly triggers the Address Bits-Counter into action). ˙In brief, this pulse starts the Timing Chain and enables the main body of the uniplexer to become active. 9 The Address Bits-Counter* ˙determines the size of the Address nest(s) (measured in bits) which must have the same number of bits as the Ad dresse(s) that are to be entered therein. ˙(The ultimate ˙determinant of size of the Address is, ˙of course, ˙the number of subscribers ˙to the SysTem.) The Address Bits-Counter determines the physical size of the Address Nests by counting to b bits (which in this case is ˙equal to the number of bits in the address) ˙and then re-sets itself. ˙Upon resetting itself it generates a RESET PULSE. ˙It is this Reset Pulse that drives the Address Counter. By counting to the number of bits in an address and resetting itself at this count it triggers the Address Counter whenever the correct number of bits have been entered into an an Address Nest. 10 The Address Counter counts to "J" where "J" ˙is the number of ˙Addess Nests (determined by the designer to be) in one Address Section. Upon reaching the count of "J" the Address Nest Counter resets itself and stops. Upon resetting this counter, also, generates a reset pulse. In B (and higher) Mode systems that pulse starts another counter. 11 The Data Nest Counter* is not employed in A Modes SysTems since these modes only have an Address Section. ˙But the Data Nest Counter is em ployed in B and all higher mode systems. The Data Nest Counter counts to the number of ˙Data Nests in one character-set and then re-sets itself. In Beta Mode SysTems the Data ˙Nests are one bit long so each bit in the Data Section is also a Data Nest. (The last is not true in higher ˙modes (such as the Gamma Modes ˙because their Data Nests ˙are comprised of more than one bit). In higher mode systems an additional counter is required to determine ˙the number of ˙bits in a Data ˙Nest just as the Address ˙Bits-Counter determines the number of bits in an Address Nest. 12 When there is only one character-set in a Data Section the output of the Data Nest Counter (the binary count) drives the Read-only-Memory directly. Since this is not the common case the reset pulse from the Data Nest Counter more commonly drives the "Q" Counter (which counts the number of character-set in that section). 13 As a general rule there are a multiplicity ("Q") of character-sets in each ˙Data ˙Section. ˙The maximum number of times a character-set can occurs in ˙a Data Section is determined by another counter called the "Q" Counter. When ˙it ˙is presnt in a uniplexer, ˙it is driven by the reset ˙pulse from ˙the Data Nest Counter. ˙The "Q" ˙Counter counts to some preset number and stops. ˙On stopping it puts out a TIMING CHAIN STOPPED" pulse. ˙The Timing Chain Stopped pulse is used to reset many circuit elements, including the Marker Detector. 14 The timing chain has other functions besides dividing the data stream into segments whose totality comprise a ForMat. ˙The pulses from ˙the various ˙counters serve for controlling the various timing ˙functions in the uniplexer. Some of these functions have been mentioned. 15 To illustrate the above statement: When the its "Q" Counter generates a Timing Chain Stopped pulse, the ForMat should be complete, i.e have reached its end. The "stop" ˙pulse from the "Q"Counter is, therefore, employed to activates the Marker Detector. ˙(When the "Q" Counter ˙is not ˙present then the "Timing Chain Stopped" ˙pulse is obtained ˙from the Data Nest Counter instead.) ˙It is ˙in this way that the uniplex er's circuit "knows" ˙when the ForMat starts and ends. ˙When it fails the "SYNC HUNT SYSTEM" becomes active and searches for the Marker. 16 The Sync Hunt Circuit is a standard circuit which can be found in any standard systems text ˙book. ˙Rather than make you hunt for this cir cuit ˙the basics will be explained in considerable detail. ˙For ˙more details a reference manual is suggested. ˙A block diagram of the cir cuit is shown in figure 22. ˙The explanation which follows ˙refers to this figure. 17 Figure 22 is a block diagram of A "SYNC HUNT CIRCUIT*". The operation of this circuit is very simple:- The way the timing chain is designed the ˙Marker (signal) ˙should ˙occur just after the timing ˙chain ˙has stopped. ˙An "end of count" pulse is fed to the Marker Detector (from the Timing Chain) ˙immediately before the Marker (signal) occurs, ˙as noted ˙in the paragraphs above. ˙This prepares the Marker Detector to receive the ˙Marker signal immediately thereafter. ˙This pulse primes the Marker Detector to put out a "start pulse" immediately ˙after the Marker is sensed. ˙The "start pulse" ˙indicats to the equipment that the Marker ˙has been ˙correctly received. ˙However, if the Marker has not ˙been received then the ˙Marker Detector puts out a "no pulse de tected" ˙pulse. Both of these pulses go to the Number Detector. ˙Note that either a "start pulse" is put out OR a "no pulse detected" pulse is put out; there must be either one or the other. 18 When a "no pulse detected" ˙pulse is fed to the UP/DOWN COUNTER* ˙an integer is subtracted from the Up/Down Counter's count. ˙If this hap pens "X" times the Up/Down Counter's count becomes zero. On the other hand when ˙a "start pulse" ˙is fed to the Up/Down Counter the counter increments its count by one (up to some number X). ˙When the count in the Up/Down Counter becomes zero the output changes from a one to a zero. This inhibits Sync Hunt Gate so that no "start pulses can pass through. The uniplexer stops receiving and transmitting until this signal is restored. The uniplexer must wait until it is re-enabled by the ˙UP/DOWN ˙Counter. ˙It is re-enabled when the ˙UP/DOWN ˙counter's counts reaches the ˙number ˙"X" ˙again. ˙For this to occur Marker De tecter ˙must put out "X" ˙pulses to indicate that the Marker is being properly received.This means (to the uniplexer) that the "Marker" has been found so the uniplexer is again enabled. Note that the operation of the shift register is in no way effected by all of the above. 19 What happens is this: each "not detected pulse subtracts "one" from the Up/Down Counter. Each detected pulse adds one to the Up/Down Counter. When the Up/Down Counter reads zero the uniplexer is inhibited. The Marker has been lost. ˙When the Marker signal is found a one is added to the the UP/DOWN Counter's count. ˙When the count reaches "X" ˙the uniplexer is re-enabled. (After reaching "X" the Up/Down Counter does not increment its count further.) 20 When a stray ˙Marker signal or two is lost the uniplexer is not dis abled. On the other hand a stray correct Marker type signal will not restart the timing ˙chain ˙because it takes x correct signals in suc cession to restart the timing chain. 21 The above circuitry is required because the Marker signal is not uni que. ˙Other signals can (and do) ˙have the same bit configuraion and can be misidentified. ˙˙What distinguishes the Marker from other sig nals is its periodicity. ˙˙The above circuit uses THAT characteristic to pick out ˙the Marker from all other identical Tags which might ex ist on the Transmission path. 22 Figure 22 ˙is a basic circuit. There are bells and whistles which can be added to make it fancier. ˙Generally these are not needed, especi ally if the Marker is a relatively long word (4 ˙- 5 bits plus). This is usually the case. 23 Each uniplexer needs a LOCAL CLOCK*. ˙This clock is usually some kind of oscillator which provides the basic timing for the uniplexer. ˙The data ˙on ˙the transmission path cannot be used directly since ˙it ˙is comprised of more or ˙less random ones and ˙zeros. ˙It therefore con tains many harmonics and subharmonics which ˙make it unfit for use as a clock. It has an average frequency, but not a steady frequency. The uniplexer must have a rock steady frequency. ˙That is where the clock comes in. There are two approaches to this problem, (1) a local clock and (2) a derived clock. We'll look at both. 24 A ˙local clock is frequently an oscillator locked to a fixed carrier frequency. This frequency might be˙a fixed frequency just outside the top ˙of ˙the transmission path's bandwidth. ˙It uses little bandwidth since it ˙is a single frequency. ˙This "inexpensive" ˙solution ˙poses cost ˙problems since the carrier frequency will not pass through ˙the shift registers unless that frequency is digital. Then other problems arise:- ˙˙how to pass ˙both the digital carrier and the ˙transmission path data without confusion, complex circuitry, etc. This solution is unsatisfactory. 25 An better solution is to employ a local temperature controlled cry stal oscillator. ˙This is a relatively expensive and well known solu tion. ˙It work well. ˙However, It is undesirable because of its cost. It is not a perfect cure because there is still a slow PHASE. "drift" 26 A preferred solution is to used a derived clock. ˙This is an oscilla tor that is both stable ˙and ˙locked ˙to the transmission path frequ ency. ˙"Locking" ˙is accomplished by injecting a little of the trans mission path's frequency into ˙the oscillator. ˙This is easily accom plished ˙by ˙(very) ˙loosely coupling the digital data stream ˙to the oscillator. This requires either (A) a ˙very stable design or (B) ˙an oscillator such as the one described in the SHEETS, witch see. 27 Some degree of "locking" is mandatory. The phase of the oscillator is not ˙arbitrary ˙but must be fixed with respect to ˙the ˙digital ˙data stream. ˙This is not just a nicety but is essential to the proper op eration of any digital system. (The uniplexer is no exception to this "law".) 28 The system requires a modem when a digital transmission path ˙is not available and an "standard" ˙telephone line is employed as the trans mission ˙path. ˙˙Analogue type lines introduce serious ˙phase ˙shifts which must be taken into account. They are to be avoided. 29 The distance between uniplexers is usually short. Under that condit ion a simple modem* ˙acts satisfactorily. ˙(Such a modem is described below.) If the ˙distance between one uniplexer and the next uniplexer is ˙great a more elaborate modem might be required for ˙that pair ˙of subscribers. This last is the exceptional case. 31 The nice thing about short fiber optic lines is that digital data can be ˙directly entered on to them. ˙And the hardware is simple and ˙the bandwidth ample. 31 Figure 23 is a block diagram of a simple and effective modem suitable for use overshort distances. ˙Its operation is as follows. The output of the uniplexer (which is the shift register) ˙puts out either a one or a zero at any one moment. This output goes to the "Bit State De tector" ˙which is a circuit that detects if the output ˙is a one or a zero. This ciruit has two outputs. ˙One circuit is enables if the bit is ˙a "one", ˙and the other circuit is enabled if the bit is a "zero" the other is enabled. ˙Each goes to a gate. ˙Gate 1 is enabled by a one bit. The second input to Gate 1 is (a none phase-shifted) input from the oscillator. ˙The output is also ˙unphase-shifted cycle. The input to Gate 2 is enabled if the bit is a "zero". Its second input is a 180 ˙degree phase shifted signal ˙from ˙the oscillator. ˙Its output (when enabled) ˙is likewise a 180 degree phase shifted signal. Each of these two outputs is a single cycle of the oscillator. These two out puts are added together to give the output signal. 32 The output signal has only two phases and these are easily accurately detected ˙over ˙the short distances which this modem is designed for. Over ˙long ˙distances the ˙phase shift caused by the ˙lines ˙and ˙the filters cause problems. ˙The ˙circuit is not intended for ˙such ˙use. The ˙circuit is ˙simple ˙enough to be incorporated into the uniplexer when needed.