Am7990 - LANCE (Local Area Network Controller for Ethernet)

FUNCTIONAL DESCRIPTION
======================

Done by:      Patrick J.D. Weichmann
   
$Id: LC_func_descr.txt,v 0.2 1994/05/24 16:25:54 root Exp root $

Description: This file is a shorcut out of the Am7990 data-sheet

(contains only the important points, fully described in the AM7990 data
 sheet)

--------------------------------------------------------------------------

	Contents:

	 1 LANCE initialize

	 2 Control and status registers (CSRs)

	 3 CPU<-> LANCE communication

	 4 Interrupts

	 5 Basic Operations

	 6 Addressing

	 7 Collision Detection and Implementation

	 8 Error Reporting and Diagnostics

	 9 Buffer Management

	10 LANCE Interface


1 LANCE initialize
------------------

During initialization, the CPU loads the starting address of the 
"initialization block" into two internal control registers.

------------------------------------------------------------------

2 Control and status registers (CSRs)
-------------------------------------

The LANCE has four internal control and status registers (CSR0-3)
which are used for various functions, such as the loading of the 
initialization block address, different programming modes and status 
conditions.

------------------------------------------------------------------

3 CPU <-> LANCE communication
-----------------------------

The host processor communicates with the LANCE during:

	- initialization phase
	- for demand transmission
	- and periodically to read the status bits following interrupts.

All other transfers to and from the memory are automatically handled.

------------------------------------------------------------------

4 Interrupts
------------

Interrupts to the microprocessor are generated by the LANCE upon:

	- completion of its initialization routine
	- the reception of a packet
	- the transmission of a packet
	- transmitter time-out error
	- a missed packet
	- memory error

The cause of the interrupt is ascertained by reading CSR0.
Bit (06) of CSR0, (INEA), enables or disables interrupts to the 
microprocessor. In Systems where polling is used in place of interrupts,
bit (07) of CSR0, (INTR), indicates an interrupt condition.

------------------------------------------------------------------

5 Basic Operations
------------------

The basic operation of the LANCE consists of two distinct modes:

	- transmit
	- receive

Transmit
++++++++

In the transmit mode, the LANCE chip directly accesses data (in a 
transmit buffer) in memory. It prefaces the data with a preamble, sync
pattern, and calculates and appends a 32-bit CRC. This packet is then 
ready for transmission to the Am7992B SIA. On transmission, the first
byte of data loads into the 48-byte FIFO. The LANCE then begins to
transmit preamble while simultaneously loading the rest of the packet
into FIFO for transmission.

Receive
+++++++

In the receive mode, packets are sent via the SIA to the LANCE. The
packets are loaded into the 48-byte FIFO for preparation of automatic
downloading into buffer memory. A CRC is calculated and compared with the
CRC appended to the data packet. If the calculated CRC checksum doesn't
agree with the packet CRC, an error bit is set.

------------------------------------------------------------------

6 Addressing
------------

Packets can be received using 3 different destination addressing schemes:

	- physical
	- logical
	- promiscuous

physical
++++++++

full comparison of the 48-bit destination address in the packet with the
node address that was programmed into the LANCE during an initialization
cycle.

logical
+++++++

	- group type mask
        - broadcast

group type mask
~~~~~~~~~~~~~~~

the 48-bit address in the packet is put through a hash filter to map
the 48-bit physical addresses into 1 of 64 logical groups. If any of
these 64 groups have been preselected as the logical address, then the
48-bit address is stored in main memory.
At this time, a look up is performed comparing the 48-bit incoming address
with the pre-stored 48-bit logical address. 

broadcast
~~~~~~~~~

The second logical address is a broadcast address where all nodes on the
network receive the packet.

promiscuous
+++++++++++

the last receive mode is promiscuous mode in which a node will accept all
packets on the coax regardless of their destination address.

------------------------------------------------------------------

7 Collision Detection and Implementation
----------------------------------------

The Ethernet CSMA/CD network access algorithm is implemented completely 
within the LANCE.      

(Up to 16 attempts to access the network are made by the LANCE before
 reporting back an error due to excessive collisions.)

------------------------------------------------------------------

8 Error Reporting and Diagnostics
---------------------------------

Error conditions reported relate either to the network as a whole or to
data packets.

Network-related errors are recorded as flags in the CSRs and are examined
by the CPU following interrupt.

Packet-related errors are written into descriptor entries corresponding   
to the packet.

System errors include:
	
	- Babbling Transmitter
		Transmitter attempting to transmit more than 1518
		data bytes

	- Collision
		Collision detection circuitry nonfunctional

	- Missed packet
		Insufficient buffer space

	- Memory time-out
		Memory response failure

Packet-related errors:

	- CRC
		Invalid data
	
	- Framing
		Packet did not end on a byte boundary

	- Overflow/Underflow
		Indicates abnormal latency in servicing a DMA request

	- Buffer
		Insufficient buffer space available

The LANCE performs several diagnostic routines:           


	- CRC check

        - two loop back modes (internal/external)
         
        - Time Domain Reflectometer is incorporated into the LANCE	   

------------------------------------------------------------------

9 Buffer Management                      
-------------------

The basic organization of the buffer management is a circular queue
of tasks in memory called descriptor rings. There are separate descriptor
rings to describe transmit and receive operations. Up to 128 tasks may
be queued up on a descriptor ring awaiting execution by the LANCE.

Each entry in a descriptor ring holds a pointer to a data memory buffer
and an entry for the length of the data buffer. Data buffers can be
chained or cascaded to handle a long packet in multiple data buffer areas.

The LANCE searches the descriptor rings in a "lookahead" manner to
determine the next empty buffer in order to chain buffers together or to
handle back-to-back packets.

As each buffer is filled, an "own" bit is reset, allowing the host    
processor to process the data in the buffer.


------------------------------------------------------------------

10 LANCE Interface
------------------


CSR bits such as ACON, BCON and BSWP are used for programming the pin
functions used for different interfacing schemes.

**********************************************************************
$Log: LC_func_descr.txt,v $
# Revision 0.2  1994/05/24  16:25:54  root
# changed header
#
# Revision 0.1  1994/05/20  05:41:38  root
# checked in
#
**********************************************************************
