/***
 *** configuration defines SVGATextMode
 *** Written by Koen Gadeyne (kmg@barco.be)
 ***
 ***/

#ifndef _CONFDEFS_H
#define _CONFDEFS_H


/*
 * Supported Chipsets
 */

#define NUM_CHIPSETS      14
#define CS_NONE       -1
#define CS_VGA        0
#define CS_S3         1
#define CS_CIRRUS     2
#define CS_ET4000     3
#define CS_TVGA8900   4
#define CS_TVGA9000   5
#define CS_PVGA1      6
#define CS_WDC90C0X   7
#define CS_WDC90C1X   8
#define CS_WDC90C2X   9
#define CS_WDC90C3X   10
#define CS_ATI        11
#define CS_ATIMACH32  12
#define CS_VIDEO7     13

#define CHIPSET_STRINGS   { "VGA",\
                            "S3" , "CLGD542x", "ET4000" , "TVGA8900" , "TVGA9000" ,\
                            "PVGA1" , "WDC90C0X" , "WDC90C1X" , "WDC90C2X" , "WDC90C3X" ,\
                            "ATI" , "ATIMACH32" , "VIDEO7" }

/*
 * Supported Register Sets
 */
 
#define RT_INDEX         1
#define RT_MEMMAP        2

#define NUM_REGSETS      8
enum t_regset            { REGSET_CRTC = 0 , REGSET_SEQ = 1 , REGSET_ATRCTL = 2, REGSET_GRCTL = 3, REGSET_MISC = 4,\
                           REGSET_DAC_STATUS, REGSET_DAC_MASK, REGSET_DAC };
#define REGSET_STRINGS   { "CRTC" , "SEQ" , "ATRCTL" , "GRCTL", "MISC" ,"DAC_STATUS", "DAC_MASK", "DAC" }
#define REGSET_TYPE      { RT_INDEX, RT_INDEX, RT_INDEX, RT_INDEX, RT_MEMMAP, RT_MEMMAP, RT_MEMMAP, RT_INDEX }



#endif

