/* SVGAlib, Copyright 1993 Harm Hanemaayer */
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */

/* Internal definitions. */

#ifndef _LIBVGA_H
#define _LIBVGA_H

/* --------------------- Macro definitions shared by library modules */

/* VGA index register ports */
#define CRT_IC  0x3D4   /* CRT Controller Index - color emulation */
#define CRT_IM  0x3B4   /* CRT Controller Index - mono emulation */
#define ATT_IW  0x3C0   /* Attribute Controller Index & Data Write Register */
#define GRA_I   0x3CE   /* Graphics Controller Index */
#define SEQ_I   0x3C4   /* Sequencer Index */
#define PEL_IW  0x3C8   /* PEL Write Index */
#define PEL_IR  0x3C7   /* PEL Read Index */

#define CRT_DC  0x3D5		/* CRT Controller Data Register - color emulation */
#define CRT_DM  0x3B5		/* CRT Controller Data Register - mono emulation */
#define ATT_R   0x3C1		/* Attribute Controller Data Read Register */
#define GRA_D   0x3CF		/* Graphics Controller Data Register */
#define SEQ_D   0x3C5		/* Sequencer Data Register */
#define MIS_R   0x3CC		/* Misc Output Read Register */
#define MIS_W   0x3C2		/* Misc Output Write Register */
#define IS0_R   0x3C2		/* Input Status Register 0 */
#define IS1_RC  0x3DA		/* Input Status Register 1 - color emulation */
#define IS1_RM  0x3BA		/* Input Status Register 1 - mono emulation */
#define PEL_D   0x3C9		/* PEL Data Register */
#define FCR_R   0x3CA		/* Feature Control Read */
#define FCR_WM  0x3BA		/* Feature Control Write Mono */
#define FCR_WC  0x3DA		/* Feature Control Write Color */
#define PEL_M   0x3C6		/* Palette MASK                */
#define GR1_P   0x3CC		/* Graphics 1                  */
#define GR2_P   0x3CA		/* Graphics 2                  */

/* 8514/MACH regs we need outside of the mach32 driver.. */
#define PEL8514_D	0x2ED
#define PEL8514_IW	0x2EC
#define PEL8514_IR	0x2EB
#define PEL8514_MSK	0x2EA

/* EGA-specific registers */

#define GRA_E0	0x3CC	/* Graphics enable processor 0 */
#define GRA_E1	0x3CA	/* Graphics enable processor 1 */

/* VGA indexes max counts */
#define CRT_C   24		/* 24 CRT Controller Registers */
#define ATT_C   21		/* 21 Attribute Controller Registers */
#define GRA_C   9		/* 9  Graphics Controller Registers */
#define SEQ_C   5		/* 5  Sequencer Registers */
#define MIS_C   1		/* 1  Misc Output Register */
#define ISR1_C  1		/* 1  ISR reg */
#define GRAI_C  1		/* 1  GRAphic Index */
#define CRTI_C  1		/* 1  CRT Index */
#define SEQI_C  1		/* 1  SEQ Index */
#define FCR_C   1		/* 1  Feature Control Register */
#define ISR0_C  1		/* 1  Input Status Register 0  */
#define PELIR_C 1		/* 1  Pallette Read Index */
#define PELIW_C 1		/* 1  Pallette Write Index */
#define PELM_C  1		/* 1  Pallette MASK        */
#define GR1P_C  1		/* 1  Pallette MASK        */
#define GR2P_C  1		/* 1  Pallette MASK        */

/* VGA registers saving indexes */
#define CRT     0		/* CRT Controller Registers start */
#define ATT     CRT+CRT_C	/* Attribute Controller Registers start */
#define GRA     ATT+ATT_C	/* Graphics Controller Registers start */
#define SEQ     GRA+GRA_C	/* Sequencer Registers */
#define MIS     SEQ+SEQ_C	/* General Registers */
#define ISR1    MIS+MIS_C	/* SVGA Extended Registers */
#define GRAI    ISR1+ISR1_C	/* SVGA Extended Registers */
#define CRTI    GRAI+GRAI_C
#define SEQI    CRTI+CRTI_C
#define FCR     SEQI+SEQI_C
#define ISR0    FCR+FCR_C
#define PELIR   ISR0+ISR0_C
#define PELIW   PELIR+PELIR_C
#define PELM    PELIW+PELIW_C
#define GR1P    PELM+PELM_C
#define GR2P    GR1P+GR1P_C
#define EXT     GR2P+GR2P_C

#define MAX_S_REGS    71
#define MAX_X_REGS    65
#define MAX_X16_REGS  10

typedef struct
{
  Bit16u   regs[MAX_S_REGS];        /* standard vga registers */
  Bit16u   xregs[MAX_X_REGS];       /* extended vga registers */
  Bit16u   xregs16[MAX_X16_REGS];   /* 16-bit extended vga registers */
  Bit8u    palette[3*256];          /* saved palette */
  caddr_t  mem;                     /* holds memory in graphics modes */
  Bit32u   mem_size;                /* size of saved memory in Kbytes */
  Bit8u    page_count;              /* number of pages of video memory */
  Bit8u    page_size;               /* size of a page in Kbytes */
  Bit8u    video_mode;              /* video mode */
} vga_info_struct;

typedef struct {
	const char *name;
	void (*saveregs)(Bit16u *xregs);
	void (*restoreregs)(const Bit16u *xregs);
	Boolean (*test)(void);
	Boolean (*init)(void);
	void (*setpage)(int);
	void (*get_perm)(void);
	void (*release_perm)(void);
	Bit8u (*ext_inb)(Bit32u port);
	void (*ext_outb)(Bit32u port, Bit8u byte);
} DriverSpecs;

extern DriverSpecs ark_driverspecs;
extern DriverSpecs ati_driverspecs;
extern DriverSpecs cirrus_driverspecs;
extern DriverSpecs ega_driverspecs;
extern DriverSpecs et3000_driverspecs;
extern DriverSpecs et4000_driverspecs;
extern DriverSpecs gvga6400_driverspecs;
extern DriverSpecs mach32_driverspecs;
extern DriverSpecs oak_driverspecs;
extern DriverSpecs paradise_driverspecs;
extern DriverSpecs s3_driverspecs;
extern DriverSpecs trident_driverspecs;
extern DriverSpecs vga_driverspecs;

extern Bit16u     CRT_I, CRT_D, IS1_R, FCR_W;
extern Boolean    isr_read;
extern Bit8u      att_d_index;
extern vga_info_struct  dosemu_regs, linux_regs;

#define outw(p,w)  port_out_w(w,p)
#define outb(p,b)  port_out(b,p)
#define inw(p)     port_in_w(p)
#define inb(p)     port_in(p)

extern void __vga_delay(void);

#endif
