      ******************************************************
      *  ANNOUNCEMENT OF ALLIANCE RELEASE 3.0  May 10th 95 *
      ******************************************************
The release 3.0 of the public domain  ALLIANCE VLSI/CAD system is
now available at:

ftp.ibp.fr      [132.227.60.2]        in /ibp/softs/masi/alliance

CONTENT

ALLIANCE is a complete set of CAD tools  and  portable  libraries
for  research and education in digital VLSI design.  The ALLIANCE
CAD  system has been developed at the MASI laboratory (Universite
Pierre et Marie Curie, Paris France). It includes a VHDL compiler
and simulator, logic synthesis tools, automatic place and  route,
DRC,  extractor,  functional  abstraction  and formal proof tools
etc...  All the ALLIANCE cell libraries  use  a  symbolic  layout
approach in  order  to provide process independence: Cmos process
from 1.6 micron to 0.8 micron have been successfully targetted.

Several new  tools have been introduced into release 3.0, (...and
several bugs have been fixed)

1) FPGA synthesis
The logic synthesis tool ALLIGATOR is dedicated to fast prototyp-
ing  on  XILINX  FPGAs.  The input description uses the same VHDL
subset as the ASIMUT VHDL simulator.


2) Floor-plan router
The high performance floor-plan router CHEOPS, developped by BULL
is  part of this release. This toll uses the same symbolic layout
approach as all the ALLIANCE portable libraries. It as been  used
for  multi-millions  transistors  circuits.  Only the binary code
for SPARC is available.

3) Timing analysis
The ALLIANCE design-flow separates functionnal verification  (us-
ing  zero  delay  VHDL  models) and the timing verification.  The
timing analyser TAS takes an extracted, transistor level net-list
(ALLIANCE  or  SPICE  format) as input, and provides all relevant
timing information.

INSTALLATION

ALLIANCE is totally free, under the terms of the GNU General Pub-
lic  License.  It includes C source files and on-line English do-
cumentation (UNIX man)

1) A hierarchical makefile allows each ALLIANCE tool to  be  com-
   piled and  installed separately.  The disk  space  required to
   compile  and  install  the full  ALLIANCE package is about 150
   megs.

2) The release 3.0 has been successfully compiled with K&R cc and
   GNU gcc compilers. The full alliance package can  now  run  on
   SPARC, LINUX and DEC architectures.

TUTORIALS

The release ALLIANCE 3.0 contains six separate tutorials:

1/ ADDACCU
   The  design  of a  very simple chip (adder/accumulator) to get
   started with the ALLIANCE tools (about 500 transistors).

2/ AMD2901
   The design of the 4 bits AMD2901 processor, from the VHDL spe-
   cification  to the  GDSII  layout, using the ALLIANCE portable
   standard cell library (about 3000 transistors).

3/ DLX
   The  design of the 32 bits DLX microprocessor (HENNESSY & PAT-
   TERSON) from the VHDL specification to the GDSII layout, using
   the  ALLIANCE  data-path  compiler  and  logic synthesis tools
   (about 30000 transistors).

4/ FPGA
   The synthesis of a simple circuit on Xilinx  FPGA (Field Prog-
   rammable Gate Array). The produced cirucit uses 20 CLBs.

5/ Synthesis Tools
   Different  levels of synthesis  and optimization (Finite State
   Machine synthesis, logic synthesis, logic and net-list optimi-
   zations) are covered by this tutorial.

6/ Data Path
   Building simple data paths  using the data path compiler FPGEN
   and the data path router DPR.
