[ These are my notes on the register bits affecting the status change
interrupt.  pcmciad will eventually act on that interrupt. ]

	Card Status Change (CSC), p. 23

These bits indicate which of the possible interrupt sources actually
have an interrupt pending.  They are only actually set when the
corrsponding bits in the CSCIC are set.  When an interrupt actually
occurs, the host must check each of these bits to determine which
interrupt event(s) actually occured; more than one bit can be set.

The bits should either be read and acknowledged one at a time (if
Explicit Write Back Acknowledge is enabled) or the entire register
should be read and handled at once (if not).  The bits are:

o GPI -- ?
o Card Detect Change -- change of either CD1 or CD2.
o Ready Change -- for memory, ready for xfer; zero for I/O
o Battery Warning -- for memory, low battery; zero for I/O
o Battery Dead -- for memory, battery dead; for I/O, ring single pulled
low

	Card Detect and General Control (CDGC), p. 28

o SW Card Detect Interrupt -- writing 1 to this bit causes a card
dtect card status change interrupt, if the corresponding CSCIC enable
bit is set.

o Card Detect Resume Enable -- allows Resume software to notice that a
card change has taken place, and frob, without an actual hardware
interrupt being generated; then, the resume software generates an
interrupt using the previous bit.

o GPI Transition Control -- If the GPI Enable bit (next bit) is 1,
then a card status change interrupt is generated  when the /GPI input
goes high to low (this bit low) or low to high (this bit high).
Somehow this bit can be tied to card ejection/insertion pending
events, XXX how?

o GPI Enable -- If 1, enables a card status change interrupt based on
the GPI Transition Control bit.

o Configuration Reset Enable -- If 1, causes virtually all registers
to be reset when both /CD[12] go high (see p. 30).  Has some special
requirement when used in an interrupt handler.

	Interrupt and General Control (IGC), p. 31

o Ring Indicate Enable -- If 1, the PC Card ring indicator signal is
passed through the PCIC, presumably so the host can auto-resume.  If
0, the ring indicator signal is used as the status change signal,
which can be read from the IS and somehow configured as the source of
the card status change interrupt (XXX how?).

o /INTR enable -- If 0, the card status change interrupt is routed to
the /INTR signal.  If 1, the interrupt is steared to the IRQ line
selected by the IRQ bits in the CSCIC (*not* the IRQ bits in this
register).

o IRQ[3210] -- XXX What are these for??  

	Card Status Change Interrupt Configuration (CSCIC), p. 33

o IRQ[3210] -- selects IRQ to steer the card status change interrupt
to when /INTR enable is 1.  IRQs 1, 2, 6, 8, and 13 cannot be
selected, and 0 disables the interrupt.

o Card Detect Enable -- enables interrupt on change of /CD[12].

o Ready Enable -- enables interrupt when memory ready for xfer;
ignored for I/O.

o Battery Warning Enable -- enables interrupt when battery warning
detected; ignored for I/O.

o Battery Dead Enable -- for memory, enables interrupt when battery
dead detected.  For I/O, enables interrupt when ring indicated by PC
card, if the corresponding enable bit in IGC is 0, and is ignored if
enable bit in IGC is 1; disables interrupt (XXX all, or just this
one?) if zero.


