From piziali!andy@sulaco.cox.smu.edu Sun Dec 19 17:11:39 1993 Return-Path: Received: from tidmmpl.csc.ti.com by sun_97d1 (4.1/SMI-4.1) id AA06325; Sun, 19 Dec 93 17:11:39 CST Received: by tidmmpl.csc.ti.com ( 5.52 (84)/5.17) id AA13951; Sun, 19 Dec 93 17:08:00 CST Received: from lobby.ti.com (ti.com) by tilde.csc.ti.com id AA05771; Sun, 19 Dec 1993 17:09:38 -0600 Received: from sulaco.dia.com (sulaco.cox.smu.edu) by lobby.ti.com with SMTP (5.65c/LAI-3.2) id AA08509; Sun, 19 Dec 1993 17:10:13 -0600 Received: from piziali by sulaco.dia.com with uucp (Smail3.1.28.1 #1) id m0pBXFj-00013mC; Sun, 19 Dec 93 17:09 CST Received: by piziali.lonestar.org (Smail3.1.28.1 #6) id m0pBVQS-0005NfC; Sun, 19 Dec 93 15:12 CST Message-Id: From: andy@piziali.lonestar.org (Andrew J. Piziali) Subject: /dos/transfer/p9000ch7.txt To: andy@tidmmpl.csc.ti.com (Andrew J. Piziali) Date: Sun, 19 Dec 1993 15:12:28 -0600 (CST) X-Mailer: ELM [version 2.4 PL21] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 15345 Status: RO POWER 9000 USER INTERFACE CONTROLLER October 1992 Chapter 7. Specifications 7.1. DC Specifications 7.1.1. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Supply Voltage -0.5 to +7.0 Volts Input Voltage -0.5 to Vcc Volts Output Voltage -0.5 to Vcc Volts Storage Temperature Range -65 to + 150 x C Lead Temperature (~ 10 seconds) 250 x C Junction Temperature 155 x C Figure 136. Absolute maximum ratings 7.1.2. RECOMMENDED OPERATING CONDITIONS 7.1.3. PIN CAPACITANCE Parameter Minimum Nominal Maximum Value Value Value Supply Voltage 4.75 VDC 5.0 VDC 5.25 VDC (vcc) Operating Case Temperature 00 C 85x C (Tc~sE) Figure 137. Recommended operating conditions Parameter Description Value C~N Input capacitance 12 pF (typical) CouT Output capacitance 12 pF (typical) Bidirectional capacitance 15 pF (typical) CcL~ Clock capacitance 12 pF (typical) Figure 138. Pin capacitance (Capacitance not tested, TA = 25 C, f = 1 MHz, VCC = 5 VDC) 7.1.4. DC CHARACTERISTICS Parameter Description Test Conditions Minimum Maximum V~H High-level input voltage Vcc = MAX 2.0 VDC V~Hc High-level input voltage for clock signals Vcc = MAX 2.4 VDC V~LN~Lc Low-level input voltage Vcc = MIN 0.8 VDC Vou High-level output voltage Vcc = MIN, loll = - 1.0 mA 2.8 VDC VOL Low-level output voltage Vcc = MIN. 1Ok = 4.0 mA 0.4 VDC Output leakage current Vcc = MAX, VouT= 0 to Vcc -10 uA +10 uA lu Input leakage current Vcc = MAX, V~N = 0 to Vcc -10 uA +10 uA Icc Standby current Vcc = MAX, f = 1 MHz 150 mA IDD Switching current Vcc = MAX, f = 25 Mhz 400 mA IOHD HD[31 ..0] drive current -8 mA +8 mA 1OLD HD[31 ..0] drive current -8 mA +8 mA Figure 139. DC characteristics over the operating range 141 7.2. AC Specifications Reference ~25/25 MHz MHz MHz I MHz Unit Loading Param. Description Signal MIN MAX MIN I MAX Host Bus latedace THBcKH HBCK clock high 12 12 ns THBcKL HBCK clock low 12 12 ns THBcKcY HBCK clock period 30 60 30 60 ns THeR HBCK rise time1 3 3 ns THBF HBCK fall time1 3 3 ns THDS HD[31 ..0] setup time SYSCLK5 5 ns THoH HD[31 ..0] hold time SYSCLK5 3 ns THDD HD[31 ..0] output delay time2 SYSCLK3 20 3 20 ns 100 pF THDz HD[31 ..0] output enable time2 HDRIVE-3 20 3 20 ns 100 pF TH^As HA[21 ..2] setup time3 CLK5 5 ns THAAH HA[21 ..2] hold timea CLK5 3 ns TH^s HA[1 ..0], HSIZE[1 ..0] setup time SYSCLK5 5 ns THAH HA[1 ..0], HSIZE[1 ..0] hold time SYSCLK5 3 ns TRQs HREQ- setup time SYSCLK5 5 ns HREQ- hold time SYSCLK3 3 ns TRos HREAD setup time SYSCLK5 5 ns TRDH HREAD hold time SYSCLK3 3 ns THAEs HAEN- setup time HBCK5 5 ns TH^EH HAEN- hold time HBCK3 3 ns THv HRDY- output delay time SYSCLK3 20 3 15 ns 50 pF T~N INTR-output delay time" SYSCLK3 30 3 30 ns 160 pF TcH SYSCLK clock high time 17 12 ns TcL SYSCLK clock low time 17 12 ns Tcy SYSCLK clock period 40 60 30 60 ns TR SYSCLK rise time 3 3 ns TF SYSCLK fail time 3 3 ns TRsT RESET-low time~ 50 50 clocks Video Controller TDcL DDOTCLK clock low time 12 12 ns TDcH DDOTCLK clock high time 12 12 ns TDcy DDOTCLK clock period 30 30 ns 1. Not tastad, but guaranteed by design. 2. Meets VESA local bus requiremnt of +8 mA drive. 3. CLK is HBCK when using a multiplexed bus; otherwise, CLK is SYSCLK. pull-up resister is used for this open-drain output pin. Figure 140. Switching characteristics over the operating range 142 POWER 9000 USER INTERFACE CONTROLLER October 1992 7.2. AC Specifications, continued Reference /25 125133 133 I I MHz MHz MHz MHz Unit Loading Parann. Description SIgnal MIN MAX MIN MAX Video Controller, continued TDR DDOTCLK nse time1 3 3 ns TDF DDOTCLK fail time1 3 3 ns TNsD HSYNC- output delay time DDOTCLK 3 20 3 20 ns 50 pF Tvso VSYNC- output delay time DDOTCLK 3 20 3 20 ns 50 pF 'CSYNC/HBLNK- output delay time DDOTCLK 3 20 3 20 ns 50 pF TvsD CBLNKA/BLNK- output delay time DDOTCLK 3 20 3 20 ns 50 pF T.ss HSYNC- setup time DDOTCLK 10 10 ns THsH HSYNC- hold time DDOTCLK 5 5 ns Tvss VSYNC- setup time DDOTCLK 10 10 ns TvsH VSYNC- hold time DDOTCLK 5 5 ns VRAM Interface PLL clock lock time at 25 MHz after reset for 25 Tpt.k MHz part or 33 MHz after reset for 33 MHz 250 250 clocks part~ TAA Access time from column address 55 40 ns TAR Column address hold time RAS- 70 55 ns T^sc Column address setup time CAS- 0 0 ns T^sR Row address setup time1 RAS- 0 0 ns Tc^c Access time from CAS-~ 30 25 ns TcAN Column address hold time CAS- 15 15 ns Tc^s CAS- pulse width 30 30 ns TCFH DSF to CAS- hold time~ 20 20 ns TCHR CAS- hold time dunng refresh~ 30 30 ns Tcp CAS- precharge time during page mode 10 10 ns Tcp^ Access time from CAS- precharge 55 40 ns TcpN CAS- precharge time~ 15 15 ns TcRp CAS- to RAS- precharge time~ 10 10 ns TcsH CAS- hold time RAS- 100 75 ns TcsR CAS- setup time during refresh~ 10 10 ns Tcv~. Write command to CAS-lead time~ 25 25 ns ToN Data input hold time CAS- 15 15 ns TDNR Data input hold time RAS- 70 70 ns Tos Data input setup time CAS- 0 0 ns TFHR DSF hold time~ RAS- 70 55 ns TFsc DSF setup time CAS- 0 0 ns TFs, DSF setup time~ RAS- 0 0 ns 1. Not tested, but guaranteed by design. Figure 140, continued. Switching characteristics over the operating range 143 7.2. AC Specifications, continued Reference 125 ~25 133 ~33'I I MHz Mhz Mhz MHz Unit Loading Peram. Description SIgnal MIN MAX MIN MAX VRAM Interface, continued Mask data to RAS- hold time~ 15 15 ns Tk, s Mask data to RAS- setup time1 0 0 ns ToE~, To~ Access time from OE-1 25 20 ns ToEz Output disable time OE- 25 20 ns ToFF Output buffer tum-off delay from CAS-~ 20 20 ns Tpc CAS- page mode cycle time 60 50 ns TF~kc Access time from RAS-~ 100 80 ns T,~ RAS- to column address delay time~ 20 20 ns TFL~. Row address hold time~ 15 15 ns T,~c Column address to RAS-lead time~ 55 45 ns TRAS RAS- pulse width~ 100 80 ns Tp~sp RAS- pulse width during page mode~ 100 80 ns RAS- random cycle time 190 150 ns T,co RAS- to CAS- delay time~ 25 25 ns Read command hold time~ CAS- 0 0 ns T,cs Read command setup time~ CAS- 0 0 ns DSF hold time~ RAS- 15 15 ns T,oH RAS- hold time OE- 20 20 ns RAS- precharge time 70 55 ns T,pc RAS- to CAS- precharge time~ 0 0 ns Read command hold time~ RAS- 0 0 ns H RAS- hold time~ 30 30 ns TRwH WEE- tO RAS- hold time~ 15 15 ns TRwL. Write command to RAS-lead time~ 25 25 ns TTco Transfer command to CAS- delay time~ 15 15 ns TTCL Transfer command to CAS-lead time~ 10 10 ns TTHH, TyH OF::- high hold time~ 15 15 ns TT.S, Tys OE- high setup time~ 0 0 ns TTu~ OE- low hold time from RAS-~ 15 15 ns T-n.s OE-low setup time to RAS-~ 0 0 ns TTp OE- precharge time~ 30 30 ns TTRD Transfer command to RAS- delay time~ 15 15 ns TTRL Transfer command to RAS- lead time~ 10 10 ns OE- to RAS- precharge time~ 90 90 ns 1. Not tested, but guaranteed by design. Figurel40, continued. Switchingcharacteristicsovertheoperatingrange 144 POWER 9000 USER INTERFACE CONTROLLER October 1992 7.2. AC Specifications, continued Ii Reference 125 12s [33 ~33 I I MHz MHz MHz MHz Unit Loading Pareto. Description Signal MIN MAX MIN MAX VRAM Interface, continued Twc. Write command hold time1 CAS- 20 20 ns Twc, Write command hold time~ RAS- 75 75 ns Twcs Write command setup time~ CAS- 0 0 ns Twp Write command pulse width~ 20 20 ns Tws, WE- to RAS- setup time~ 0 0 ns Not tested, but guaranteed by design. Figure 140, continued. Switching characteristics over the operating range Pin SIgnal Description Loading FBDATA[31 ..0] Frame buffer data bus 50 pF RAS[1 ..0]- Row address strobe 80 pF CAS[1 ..0]- Column address strobe 80 pF WEO[3..O]- Write enable 50 pF WEl[3..O]- FA[8..O] Frame buffer address bus 150 pF OE- Output enable 150 pF DSF Special function control 150 pF DACCE- RAMDAC chip enable 50 pl= A 33f2 damping resistor is used in test load for the VRAM and RAMDAC controller signals. For memory configuration 5, 256Kx8 VRAMs are required to achieve proper loading. Figure 141. VRAM and RAMDAC controllers loading 145