-------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 Chapter 2. Host, Video, and Frame Buffer Interfaces This chapter is the hardware design reference for the WEI- TEK Power 9000 User Interface Controller chip. Topics covered in this section include: Interfacing the Power 9000 to a host bus Connecting VRAMs and RAMDACs to the Pow- er 9000 Setting video timing parameters Initializing the Power 9000 chip A sample integrated design Board design considerations 2.1. Host Bus Interface The host bus interface allows the Power 9000 to communi- cate with the host bus. It is a synchronous, generic inter- face that connects easily with minimal glue logic. You can interface the Power 9000 to either a synchronous (to SYSGkK) or an asynchronous (to SYSGLK) host bus. White the design requirements for connecting to an asynchronous host bus are more extensive than those for a synchronous bus, they are not complex (see section 2.1.8). 2.1.1. HOST REQUESTS The host initiates requests via HREQ-. HREAD indicates whether the host is requesting a read or a write. To initiate a read operation, the host asserts both HREAD and HREQ-. To initiate a write, the host deasserts HREAD and asserts HREQ-. Figure 15 shows host bus interface address and data paths. 15 -------------------------------------------------------------------------------- 2.1. Host Bus Interface, continued 2.1.2. HOST ADDRESSING The host addressing method uses a 22-bit host address bus (HA[2l ..0]). The Power 9000 uses the two lowest host ad- dress bits, HA[l] and HA[O], in conjunction with host size (HgIZE[l..O]) only during dumb frame buffer writes. These special bits determine which bytes to transfer. The encoding of these bits is defined in figure 5. Note: The HSIZE[1 ..0] and HA[1 ..0] bits used to generate the write enables are not latched internally to the Power 9000. When you are implementing a host interface for a multiplexed bus where the write-enable information could be lost before the write is actually implemented within the Power 9000, latch HSIZE[1 ..0] and HA[1 ..0] externally. 2.1.3. DATA TRANSFER The HDRIVE- signal drives data from the Power 9000 onto the host data bus (HD[31 ..0]). 2.1.4. CLOCKS The host bus clock, HBGK, clocks the host address into the host address register. When designing a system on which the Power 9000 runs synchronously with the host inter- face, tie HBGK to the Power 9000's system clock (~YSGLK), and to the system clock running on the host bus to ensure synchronous clocking of addresses. On a syn- chronous, non-multiplexed bus, tie HBCK to ground and tie HAFN- to ground. This internally ties HBGK to SYSGLK, thus reducing loading on SYSGLK. 2.1.5. INTERRUPTS When the Power 9000 requests an interrupt, it forces INTR-low and holds it low indefinitely. INTR- is an open- collector signal. The host must recognize the interrupt, handle the interrupt condition as appropriate, and call a software routine to clear the Power 9000 interrupt register to deassert the INTR- signal. Because the Power 9000 holds the interrupt until it is recognized and cleared by the host, there is no danger of missing a Power 9000 interrupt. 2.1.6. MULTIPLEXED HOST BUS DESIGN To control address and data transfer on a multiplexed host bus, the host address enable (HAl=N-) signal enables data transfer to the host address register. HAl=N- holds the ad- dress during a bus write cycle while the data is transferred to the data register. In the usual sequence of events, the host: 1. Asserts HAEN-. 2. Issues the address. 3. Deasserts HAEN-. (The Power 9000 holds the ad- dress.) 4. Loads the data. (The data is held until the host ac- knowledges that the write is complete to the bus con- troller; no separate clock is required to load the data.) 2.1.7. NON-MULTIPLEXED HOST BUS DESIGN With a non-multiplexed host bus, tie HAl=N- to ground; this signal is required only with a multiplexed host bus. 2.1.8. ASYNCHRONOUS HOST BUS DESIGN When interfacing the Power 9000 to an asynchronous host bus, it is up to the system designer to ensure that host re- quests synchronize with SYSGLK. You can use HBGK to clock in the address registen The Power 9000 does not sup- port synchronizing automatically; it samples host requests relative to SYSCLK, and uses HBGK only to clock in the address. On an asynchronous bus, if it is not possible to clock the address register separately from SYSGLK, then it may be necessary to supply external registers to ensure that the system samples the address when it is valid. 16 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.1. Host Bus Interface, continued 2.1.9. HOST BUS INTERFACE STATE MACHINE HREQ & HF[EAD / / WRITE ACK HRDY is HIGH ~ DONE ~ "'ERSET IDLE HRDYisLOW HREQ READ ACK HREC HREAD READ WAIT HRDY is HIGHy DONE HRDY is LOW Data will be valid in the next cycle and stay valid until another read is processed, HDRIVE- controls whether or not the data is driven onto the bus. Figure 16. Host bus state diagram 2.1.10. HOST BUS READ OPERATIONS If a request is made when the Power 9000 is busy (HRDY- 3. is deasserted), the Power 9000 ignores the request and does not perform the operation. The basic sequence for a read 4. operation is: 5. 1. The host asserts HREAD for a read operation. The host places the address on the address bus and as- 6. serts HAEN-. The host asserts HREQ- to initiate a host request. 2. The Power 9000 deasserts HRDY- to indicate that it is busy. The host sees that FIRDY-is deasserted and, therefore, releases the address bus and deasserts HREQ-. The host waits for the Power 9000 to reassert HRDY-. The Power 9000 asserts HRDY- to indicate that it is ready to accept another request. When the valid data is available (one clock cycle after the assertion of HRDY-), the host asserts HDRIVIE- to drive the read results onto the host bus and performs the required host-specific functions to transfer the data to the bus controller. 17 -------------------------------------------------------------------------------- 2.1. Host Bus Interface, continued HREQ- N HREAD / HRDY- N / k~ HA[31..O] X VALID X HAEN- k\ / HDRIVE HD[31..O] < INVA~D!X VALID Figure 17. Host bus read cycle (0 wait stare ,I HBCK HREQ- HREAD HRDY- HA[31 ..0] HAEN- HDRIVE HD[31 ..0] I / X VALID Figure 18. Host bus read cycle (1 wait state' ,i ,I 18 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 i 2.1. Host Bus Interface, continued HREQ- HREAD HRDY- HAEN- HDRIVE- HA[21 ..2]. HD[31 ..0] D HA[1 ..0] VALID HSIZE[1 ..0] i Figure 19. Multiplexed host bus read cycle (no wait states) 19 -------------------------------------------------------------------------------- 2.1. Host Bus Interface, continued 2.1.11. HOST BUS WRITE OPERATIONS Before issuing a write request, the host must be certain that the Power 9000 is ready to accept a request; if not ready (HilDY- is high), the Power 9000 ignores the request and does norperform the operation. The basic sequence for a non-multiplexed write operation is: 1. (The host has driven the host data and host address buses.) The Power 9000 asserts HilDY- to indicate that it is ready for a transfer. The host places the address on HA[21 ..0]. The host places the data on HD[3l ..0]. The host deasserts HilI:AD. The host asserts HREQ-. 2. The Power 9000 deasserts HRDY- to indicate that it has accepted the write and the host deasserts Hill:O-. The basic sequence for a multiplexed write operation is: 1. The host asserts HA[21 ..0] and HAl:N-. 2. The Power 9000 asserts HilDY- to indicate that it is ready for a transfer. The host deasserts HA[21 ..0] and HAl:N-. The host asserts HD[31 ..0]. The host deasserts Hill:AD. The host asserts Hill:C}-. 3. The Power 9000 deasserts HilDY- to indicate that it has accepted the write. 4. The host deasserts Hill:C}-. HBCK 0 1 HREAD ~ HRDY- ~ // HA[21:0] . X VALID HAEN- ~ / / HD[31:0] X VALID i Figure 20. Host bus write operation (0 wait state) 20 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.1. Host Bus Interface, continued HBCK HREQ- HREAD HRDY- HA[21:2] HAEN- HD[31:0] HA[1..0], HSIZE[1 ..0] 1 X VALID X X VALID X VALID Figure 21. Host bus write operation (1 wait state) SYSCLK, HBCK HREQ- HREAD HRDY- HAEN- HDRIVE- HA[21 ..2], HD[31 ..0] HA[1 ..0] HSIZE[1..0] T VALID T I F Notice that, before the command is accepted, the address is latched into the Power 9000 before it sees the host reques~ (HREQ-I. Figure 22. Multiplexed host bus write cycle (no wait states) 21 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.2. Video Control, continued Register Description/Function vrtc Vertical counter. Read only. Specifies the current line position along a vertical sweep; the Power 9000 increments this counter upon each occurrence of HSYNC-. The value occupies the lower 12 bits of the register, which is set by the Power 9000. vrtt Vertical length. Read/write. Specifies the number of lines in a vertical sweep. The value occupies the lower 12 bits of the register, which is set by the host. The Power 9000 compares the current vrtc value (the current line position) to this val- ue to determine when to wrap around. vrtsr Vertical sync rising edge. Read/write. Specifies the location along a vertical sweep which defines the vertical sync ns- ing edge. The value occupies the lower 12 bits of the register, which is set by the host. Register DescriptioNFunction vrtbr Vertical blank rising edge. Read/write. Specifies the location along a vertical sweep which defines the vertical blank rising edge. The value occupies the lower 12 bits of the register, which is set by the host. vrtbf Vertical blank falling edge. Read/write. Specifies the location along a vertical sweep which defines the vertical blank failing edge. The value occupies the lower 12 bits of the register, which is set by the host. prevrtc Vertical counter preload value. Read/ write. Specifies the value with which to preload vrtc upon receipt of an internal or extemal VSYNC-; allows synchronization of the Power 9000 with external video sources, whatever the combination of in- ternal or external delays. The value occu- pies the lower 12 bits of the register, which is set by the host. Set this register to zero when using only internal syncs. Figure 24. Video control registers: vertical timing Register DescriptioNFunction sraddr Screen repaint address. Read only. Speci- fies the next VRAM address to be loaded into the SAM. The address corresponds to bits 21-10 of the linear address (the lower bits of the address are always zero and are not stored). The value occupies the lower 12 bits of the register, which is set by the host or the Power 9000. This regis- ter is automatically set to zero or the start- ing address of the current display buffer (zero for single buffer) by assertion of the VBLNK- signal. Register DescriptioNFunction srtctl Screen refresh timing control. Read/write. Specifies controls for screen refresh, as set by the host. Figure 83 defines this register. qsfcounter QSF counter. Read only. Used to determine when to generate a shift register load opera- tion. It is a duplicate of the QSF signal from the VRAMs. It keeps track of which part of the SAM is being shifted out. It is loaded with a zero after every read transfer and incremented by DDOTCLK. Figure 25. Video control registers: screen repaint 23 -------------------------------------------------------------------------------- 2.2. Video Control, continued 2.2.3. VIDEO TIMING The video signals and registers work together to drive the signals that control the monitor. HORIZONTAL VIDEO TIMING Figure 26 presents the timing sequence for horizontal vid- eo control. All of the horizontal timing registers are loaded with counts derived from DDOTGI_K which may represent multiple pixels. Each of the values stored in the horizontal timing registers represents the total count minus one to al- low for zero in the count sequence. In the horizontal timing sequence: The hrzt register defines the number of DDOTGLKs from the failing edge of HSYNG- to the falling edge of the next HSYNC-. hrzc counts from zero to hrzt and then repeats. hrzsr specifies the HSYNC- active low count. hrzbrspecifies the distance from HSYNC-low to the rising edge of HBLINK-. htzbf specifies the distance from HSYNC- low to the fall- ing edge of HBkINK-. The programmer must satisfy the following condition: hrzsr < hrzbr < hrzbf < hrzt VERTICAL VIDEO TIMING Figure 27 presents the timing diagram for vertical video timing control. All of the vertical timing registers are loaded with counts that represent horizontal scan lines. Also, each number loaded into a vertical timing register represents the total count in the count sequence. In the vertical timing sequence, vrH defines the number of horizontal lines from the falling edge of VSYNC- to the failing edge of the next VSYNG- (the number of horizontal lines in a complete vertical scan cycle). The vrle register counts from zero to vrtt-l and then repeats. vrtsr specifies the VSYNC- active low count. The rising and failing transitions of VSYNC- should match those of HSYNC-. vrtbr specifies the distance from VSYNC- low to the rising edge of VBLNK-. vrI:bf specifies the distance from VSYNC-low to the falling edge of VBLNK-. The programmer must satisfy the following condition: vrtsr < vrlbr < vrtbf < vrtt hblnk- hsync- ! hrzsr + 1 hrzbr + 1 hrzbf + 1 hrzt+ 1 All horizontal times are in terms of ddotclk Figure 26. Power 9000 horizontal video timing parameters 24 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.2. Video Control, continued Scan line Top of screen Bottom of screen ! vrtsr --~ vrtbr vrtbf vsync- vrtt Allverticaltimesareintermsofhorizontalscanlines Figure 27. Power 9000 vertical video timing parameters 25 -------------------------------------------------------------------------------- 2.2. Video Control, continued 2.2.4. PROGRAMMING THE VIDE~OCONTROLLER Figure 28 is an example of how to program the Power 9000 sheet. Some of the horizontal times are given in microsec- video controller. Figure 28 shows a monitor specification onds. HORIZONTAL I HBL I HAD I VERTICAL HSPIHBP HFPI I 1H I I VBL I VAD I VSP I VBP VFPI I .~ 1V I Item Abbreviation Monitor Rating Pixel frequency fc 64 MHz Honzontal frequency fH 48.19 kHz Line Time total 1 H 20.75 gsec Horizontal active display HAD 16 lisec Horizontal blanking HBL 2.75 Ilsec Horizontal sync pulse HSP 1 p. sec Horizontal back porch HBP 2.75 gsec Vertical frequency fV 60 Hz Frame time total 1 V 803 scan lines Vertical active display VAD 768 scan lines Vertical blanking VBL 28 scan lines Vertical sync pulse VSP 4 scan lines Vertical back porch VBP 28 scan lines Figure 28. 1024x768 monitor specification (60 Hz refresh rate) 26 -------------------------------------------------------------------------------- 2.2. Video Control, continued The horizontal timings should be converted from microse- conds to dots by multiplying the time in/as by the frequen- cy in MHz. For example: Line time total [dots] : Line time total [~.sec] * Pixel frequency [MHz] : 20.75 gsec * 64 MHz 1328 dots POWER 9000 USER INTERFACE CONTROLLER October 1992 The results of the conversion are shown in figure 29. Only the values needed to program the Power 9000 are shown. To compute the values that are programmed into the Pow- er 9000, just plug the numbers in as in figure 30. Item Abbreviation Monitor Rating Line Time total 1 H 1328 dots Horizontal active display HAD 1024 dots Horizontal sync pulse HSP 64 dots Horizontal back porch HBP 176 dots Frame time total 1 V 803 scan lines Vertical active display VAD 768 scan lines Vertical sync pulse VSP 4 scan lines Vertical back porch VBP 28 scan lines Figure 29. 1024x768 monitor specification (60 Hz refresh rate) after conversion Horizontal Calculation hrzsr = HSP -1 - 64 -1 = 15 4 4 hrzbr = HSP + HBP -1 - 64 + 176 -1 = 240 -1 = 59 4 4 4 hrzbf _ HSP + HBP + HAD -1 - 64 + 176 + 1024 -1 1264 4 4 4 hrzt = 1H -1 - 1328-1 = 331 4 4 Vertical Calculation vrtsr = VSP = 4 vrtbr = VSP + VBP = 4 + 28 = 32 vrtbf = VSP + VBP + VAD = 4 + 28 + 768 = 800 vrtt = 1 V = 803 -1 = 315 Figure 30. Horizontal and vertical timing calculations 27 -------------------------------------------------------------------------------- 2.2. Video Control, continued 2.2.5. EXTERNAL SYNCHRONIZATION The VSYNC- and HSYNC- pins can be defined as inputs to provide synchronization from an external source. This allows merging of Power 9000 video with video generated by an external source. With values programmed into prehrzc and prevrtc, the Power 9000 can synchronize ex- actly with the external source, regardless of internal and external delays in the system. There are two standard modes for implementation of ex- ternal sync timing: external VSYNG- only and external VSYNG- and HSYNG-. With external VSYNC- only, the Power 9000 preloads both the horizontal and vertical counters (hrzc and vrtc) on the falling edge of an external VSYNC- pulse. This syn- chronizes both HSYNG- and VSYNC- to the external source. With external VSYNC- and HSYNC-, the Power 9000 preloads the hrzc counter on the failing edge of an external HSYNC- and preloads the vrtc counter on the falling edge of an external VSYNC-. HSYNC- and VSYNC-input pulses must be at least one DDOTGLK wide, but must also be shorter than the hori- zontal sync rising edge defined in the hrzsr register. 2.2.6. SCREEN REPAINT CONTROL Screen repaint is a generic descriptor for the functions used by the frame buffer memory to provide pixel information to the "back-end" of the video subsystem to display stored information on the monitor. The Power 9000 provides two basic methods to ensure that the shift registers of the VRAMs always contain the correct data to be shifted onto the screen. These two methods are controlled by the setting of the hblnk_reload bit in the srtctl register (see figure 83). NORMAL (SPLIT shift MODE) For normal operation, the hblnk_reload bit in the srtctl register is zero. During a vertical retrace operation (VBLNK- asserted), the Power 9000 reloads the entire shift register inside the VRAMs and then performs a split shift register reload whenever the VRAM output shift registers are more than half empty, based on the internally gener- ated QSF signal. The Power 9000 does not intervene between scan lines (during HBLNK-), this method requires that each scan line of the image be located in sequential linear memory and that the VRAM shift clock be inhibited during H BLNK-in- tervals. The physical scan line width of the monitor must exactly match the logical scan line width loaded into the drawing engine. This requires that there be no extra pixels between scan lines in memory. The initial scan-line increment after VBLNK- equals one row of VRAM addresses and subse- quent increments equal one-half row. RESTRICTED (HBLNK- RELOAD MODE) For restricted operation, the hblnk_reload bit in the s.ctl register is one. The entire VRAM shift register is reloaded for every scan line (HBLNK- asserted). In this mode, every scan line in the VRAM must be entirely contained within a single shift register. This constrains scan line length to be less than one whole, one half, or one quarter of the entire shift register length. When using this mode, the available screen resolutions are restricted, as defined in figure 31. VIRTUAL SCREEN SIZES (Restricted Mode) Maximum Config- Screen Resolution Scan Double uration Horizontal Vertical Increment Buffering 1 and 2 1024 1024 1/2 row No 3 2048 1024 1/2 row No 4 1024 1024 1/4 row Yes 5 2048 1024 1/4 row Yes Figure 31. Screen resolutions in restricted mode 28 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER 2.3. Frame Buffer Design Notes This section presents information necessary to select, con- figure, and connect VRAMs. 2.3.1. MEMORY CONFIGURATIONS The Power 9000 supports five basic frame buffer memory configurations, illustrated in figures 32 through 36. The designer's choice depends primarily on what resolution monitor is to be supported, the speed desired, and how much board space can be comfortably allotted to the memory system. The memory configuration diagrams presented in this sec- tion define five alternative frame buffer subsystem designs. Considerable leeway is available to the designer as long as the operating specifications for the VRAM and RAMDAC components are observed. The Power 9000 supports double buffering of the frame buffer. To implement double buffering, the frame buffer is divided into two screen-sized sections of memory, arbi- trarily numbered buffer 0 and buffer 1. The Power 9000 performs frame buffer operations on only one buffer at a time. Buffer selection is controlled by two bits in the sys- config register, and one bit each in the draw_mode and srte~ registers. In the syseonIig register (see section 3.4.1 ), the pixel bur read and pixel. bur write bits select the buffer for pixel reads and writes. In the draw_mode regis- ter (see section 3.4.3), the dest_buffer bit selects the desti- nation buffer for drawing operations. In the srtctl register (see section 3.4.3), the display_buffer bit selects the buffer for display. MEMORY CONFIG URATION I Memory configuration 1 (see figure 32) is the most basic, lowest performance configuration. Interleaved writes are not possible with this configuration. All writes to the frame buffer take at least two cycles. However, you can achieve a small footprint for this memory system. All signals connect directly to Power 9000 signals. BUFFER 20 19 LOGICAL ADDRESS I ' ' I ' 19 IGNORED PHYSICAL ADDRESS LINEAR 11 10 ROW COLUMN 0 2 1 0 BYTE BANK 0 RAS[OI- CAS[O]- WEO[Ol- FBDATA[31..241 ~: OE- RAS[O]-~'~- OE- RAS[O]-~"~ OE- RAS[O]-~- OE- -- DSF CAS[O]---~ I' DSF CAS[O]-~- DSF CAS[O]-~ l' DSF FA[8..O] WEO[1]-~ I' FA[8..O] WEO[2]--I J-- FA[8..O] WEO[3]-~ I' FA[8..O] FBDATA[23..16] ~ FBDATA[15..8] %__. FBDATA[7..O] 'L Byte 0 Byte 1 Byte 2 Byte 3 (2 Chips) (2 Chips) (2 Chips) (2 Chips) Figure 32. Memory configuration 1. Single-buffered, single-bank, 1 megapixel frame buffer using eight 256Kx4 VRAMs (or four 256Kx8 VRAMs) 29 -------------------------------------------------------------------------------- 2.3. Frame Buffer Design Notes, continued MEMORY CONFIGURATION 2 Memory configuration 2 (see figure 33) is also a IM pixel configuration, but it also allows single-cycle writes. With this memory configuration, the two memory banks con- nect to different RAS-, GAS-, and WE- signals; all other signals are shared in common. MEMORY CONFIGURATION 3 Memory configuration 3 (see figure 34) is a 2M pixel ar- rangement that connects to the Power 9000 in the same way as memory configuration 2 (with the two memory banks connected to different RAS-, GAS-, and WE- sig- nals and all other signals shared in common). This configu- ration can support one 2M pixel display or a double-buffered IM pixel display. This configuration is identical to memory configuration 4, with the single excep- tion that configuration 3 ignores all double buffer infor- mation inside the Power 9000. BUFFER 20 19 LOGICAL ADDRESS ' I ' LINEAR 19 11 10 3 2 1 IGNORED PHYSICAL ADDRESS ROW COLUMN BANK BYTE BANK 0 RAS[O]- ~ OE- RAS[O]- C"' OE- RAS[01- ~_- OE- RAS[O]- ~[~__-- GAS[O]-- DSF CAS[O]- DSF CAS[O]- DSF CAS[O]- WEO[O}- FA[8..0] WEO[1 ]- FA[8..O] WEO[2]- FA[8..O] WEO[3]- FBDATA[31 ..24] FBDATA[23.. 16] FBDATA[15..8] FBDATA[7..O] BANK 1 RAS[1]- ~']-- OE- RAS[1]- ~I: OE- RAS[lI- ~.- OE- RAS[1]- Ii GAS[1]"1 I' DSF GAS[1]- - DSF CAS[1]- DSF CAS[1]- WEl[O]- 'I i-- FA[8..O] WEll1]- FA[8..O] WEll2]- - FA[8..O] WEl[3]- FBDATA[31..24]~____J FBDATA[23..16] FBDATA[15..8] *~[__3 FBDATA[7..O] Byte 0 Byte 1 Byte 2 Byte OI:_ DsF FA[8..O] OE- DSF FA[8..O] Figure 33. Memory configuration 2. Single-buffer, double-bank, 1 megapixel frame buffer using eight 128Kx8 VRAMs BUFFER LOGICAL ADDRESS I ' 1 IGNORED PHYSICAL ADDRESS BANK 0 20 20 ROW LINEAR 12 11 3 2 COLUMN BANK 0 1 0 BYTE RAS[O]- ~'1' OE- RAS[O}--~'~- CAS[Ol- 'I I' DSF CAS[O]- '1 WEO[O]- ~ i-- FA[8..O] WEO[1]- ~ l' FBDATA[31..24] ~ FBDATA[23.. 16] ~ BANK 1 RAS[1]---F'I-- OE- RAS[1]--{"~- CAS[1]"'I I' DSF CAS[1]---I WEl[O]"i I' FA[8..O] WEl[1]-~ FBDATA[31 ..24] ~ FBDATA[23..16] ~ Byte 0 Byte 1 (2 Chips) (2 Chips) OE- RAS[O]- ~2~: OE- RAS[O]- ~E~: OE- DSF CAS[O]- ~ DSF CAS[O]- - DSF FA[8..0] WEO[2]- FA[8..O] WEO[3]- FA[8..O] FBDATA[15..8] FBDATA[7..O] OE- RAS[1]- ~"~- OE- RAS[1}- ~'1' OE- DSF CAS[1]- -l ]~ DSF CAS[1]- '1 i' DSF FA[8..O] WEl[2]-~ I' FA[8..O] WEl[3]-~ i' FA[8..O] FBDATA[15..8] ~ FBDATA[7..O] ~ Byte 2 Byte 3 (2 Chips) (2 Chips) Figure 34. Memory configuration 3. Single-buffer, double-bank, 2 megapixel frame buffer using sixteen 256Kx4 VRAMs (or eight 256Kx8 VRAMs) 30 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER 2.3. Frame Buffer Design Notes, continued MEMORY CONFIGURATION 4 Memory configuration 4 (see figure 35) is identical to configuration 3, with the exception that this configuration uses the Power 9000 double buffer registers to control how addresses are generated to the VRAM. The five Power 9000 double buffer registers allow control of which buffer is displayed, which buffer the host writes into, and which buffer the drawing engine writes into. They also allow you to set up reads and writes in different buffers. BUFFER 20 19 LOGICAL ADDRESS ' 'I LINEAR ~B 19 12 11 3 2 PHYSICAL ADDRESS IGNORED . ROW COLUMN BANK 1 BYTE BANK 0 RAS[O]- 'f'V' OE- RAS[O]-~4~_--' OE- RAS[O]--~'~- OE- RAS[01-~1' OE- GAS[O]- --1 J" DSF GAS[O]- DSF CAS[O]-~I- DSF GAS[O]-~J- DSF WEO[O]-~ i-- FA[8..O] WEO[1]- FA[8..O] WEO[2]-~- FA[8..O] WEO[3]-~I" FA[8..O] FBDATA[31..24] ~ FBDATA[23..161 FBDATA[15..8] ~ FBDATA[7..O] BANK 1 RAS[1]-~_ OE- RAS[1]-~'~- OE- RAS[1]-~"1-- OE- RAS[1]-~'~-- OE- GAS[1]- -- DSF CAS[1]"I I' DSF CAS[1]-~ ]- DSF CAS[1]-~ I' DSF WEI[O]- FA[8.,O] WEI[1]--/ 1' FA[8..O] WEI[2]-'J I' FA[8..O] WEI[3]-~ I' FA[8..O] FBDATA[31 ..24] FBDATA[23..16] ~ FBDATA[15..81 ~ FBDATA[7..O] ~ Byte 0 Byte 1 Byte 2 Byte 3 (2 Chips) (2 Chips) (2 Chips) (2 Chips) Figure 35. Memory configuration 4. Double-buffer, double-bank, 2 megapixel frame buffer using sixteen 256Kx4 VRAMs (or eight 256Kx8 VRAMs) 31 -------------------------------------------------------------------------------- 2.3. Frame Buffer Design Notes, continued MEMORY CONFIGURATION 5 Memory configuration 5 (see figure 36) supports double buffering of 2M pixel display data. This configuration does not run as fast as the other configurations because the load on all buses is doubled. Thus, the AC specifications for this configuration are different from those for the other configurations, although they were not available at press time. BUFFER 20 LOGICAL ADDRESS [ B 20 PHYSICAL ADDRESS ~ ROW 0 LINEAR ] 13 12 4 3 2 1 0 COLUMN BANK ] BYTE BANK 0 RAS[O]- CAS[O]- WEO[O]- FBDATA[31..24] ~__OE- RAS[O]- '1'~' OE- RASrOl- DSF CAS[O]- ~ J* DSF CAS[01- ~ FA[8..O] WEO[1 ]- ~ I' FA[8, .0] WEO[2]- ~ I' FBDATA[23..16]~ FBDATA[15..8] ~ OE- RAS[O]- I l" OE- DSF CAS[01- DSF FA[8.,OJ WEO[3]- -- FA[8..O] FBDATA[7..0] __j BANK 1 RAS[1]- CAS[~I- WEt [OF FBDATA[31..24] ~OE- RAS[1]---~'}- OE- RAS[~]--~"1- OE- RAS[1]-~- OE- DSF CAS[1]---~ 1-- DSF CAS[1]-~-- DSF CAS[1]--~ I' DSF FA[8..O] WEI[1]--1 ~-- FA[8..O] WEI[2]-~I-- FA[8..O] WEI[3]---/ ~-- FA[8..O] FBDATA[23..16] 't__J FBDATA[15..8] ~ FBDATA[7..O] ~ BANK2RAS[O}- ~-: OE- RAS[01-~: OE- RAS[O]-~1~' OE- RAS[01-~ ~ OE- CAS[2}- -- DSF CAS[2]- -- DSF CAS[2]- DSF CAS[2]-~ DSF WEO[O}- FA[8..O] WEO[1]- FA[8..O] WEO[2]- FA[8..O] WEO[3]- ~ j-- FA[8..O] FBDATA[31..24] FBDATA[23..16] FBDATA[15..8] FBDATA[7..O] ~__ BANK 3hAS[11_ CAS[3]- WEIIOl- FBDATA[31 ..24] ~_-OE- RAS[1]- DSF CAS[3]- ~ FA[8..01 WE I[1 ]- ~ 1' FBDATA[23.. 16] Byte 0 Byte 1 OE- RAS[1]- ~V~: OE- RAS[1]- ~_ OE- DSF CAS[3]- - DSF CAS[3]- DSF FA[8..O] WEI[2]- FA[8..O] WEI[3]- FA[8..O] FBDATA[15..8] FBDATA[7..O] Byte 2 Byte 3 Figure 36. Memory configuration 5. Double-buffer, double-bank, 2 megapixel frame buffer using sixteen 256KxgVRAMs 32 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER 2.3. Frame Buffer Design Notes, continued 2.3.2. SYSTEM INTEGRATION OF VRAMS The major steps required to connect the VRAMs are: 1. Connect the signals as summarized in the figures in section 2.3.1. The FBDATA[~l ..0], FA[8..O], nAS[l..01-, CAS[a..01-, WEO[3..01-, OE-, and DSF lines require 33 fl external damping re- sistors; the VRAM does not function properly if these resistors are not provided. The self-timing load pin, STLOAD, must be connected to an external capacitor equal in value to the capacitance of the most heavily loaded FA line. 2. Implement and connect external logic to generate seri- al clocks to the VRAMs to control shifting out of the shift registers and to generate serial enables (output enables) for the shift register data. These functions can be controlled by logic designed to match the VRAM configuration being implemented; the serial clock must be based upon the sync and blank signals coming from the Power 9000 in combination with the number of banks of memory. October 1992 3. Connect the serial data bus from the VRAMs to the RAMDAC. The VRAMs provide added system support via their built- in shift registers, which can be configured in two halves for split-shift mode VRAMs. The following restrictions apply: 1. The Power 9000 requires VRAMs that support the split-shift transfer mode. 2. VRAMs which include the extended data out mode (a new mode introduced with some VRAMs) do not work with the Power 9000. 2.3.3. FRAME BUFFER TIMING DIAGRAMS All VRAM accesses can be described as sequences of the VRAM timing templates shown in figures 37 through 42. FA[8..0] RAS[1 ..01- OE- CAS[3..01- WEO[3..O]- WEl[3..O]- FBDATA[31 ..0] DSF Figure 37. Row miss template 33 -------------------------------------------------------------------------------- 2.3. Frame Buffer Design Notes, continued FA[8..01 RAS[1 ..Ol- OE- CAS[Ol- WEO[3..O]- CAS[3..1]- WEl[3..O]- COLUMN ADDRESS ACTIVE' BANK IN,~CTIVE' BANK(S) DSF * Assumes bank 0 is active Figure 38. Read template 34 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.3. Frame Buffer Design Notes, continued SYSCLK FA[8..0] RAS[1 ..01- OE- CAS[O]- WEO[3..01- CAS[3..1]- WEI[3..O]- FBDATA[31 ..0] DSF HOLD HOLD WRITE * Assumes bank 0 is active ACTIVE BANK* INACTIVE BANK FINISH WRITE Figure 39. Write ternplate 35 -------------------------------------------------------------------------------- 2.3. Frame Buffer Design Notes, continued FA[8..o] RAS[1 ..O]- CAS[3..O]- OE- WEO[3..O]- WEll3..O]- FBDATA DSF DSF Figure 40. Read transfer and split transfer templates 36 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October1992 2.3. Frame Buffer Design Notes, continued SYSCLK t FA[8..0] RAS[1..O]- CAS[3..O]- OE- WEO[3..O]- WEl[3..O]- F B D ATA[31.. 0 ]! ;!~;~ ~ ;!i;i~!i~!ii!i Figure 41. Refresh templates FA[8..O] E~ i RAS[1 ..01- CAS[3..O]- OE- WEO[3..01- WE l[3..O]- FBDATA Figure 42. Idle templates 37 -------------------------------------------------------------------------------- 2.4. RAMDACs While the Power 9000 design is not specific to any RAM- DAC, connection to the Brooktree 458 or 459 is particu- larly simple. With either of the Brooktree RAMDACs, the Power 9000's frame buffer controller handles the interface to the RAMDAC without supplemental system design. Operation of either of these RAMDACs employs the RAMDAC address format (see section 3.2.4); the host places the RAMDAC control bits in bits 2 and 3 of the ad- dress and place the data to send to the RAMDAC in the lower byte position on the data bus. All host reads and writes of the RAMDAC go through the Power 9000, which handles the interface functions. For PC systems on which the Power 9000 and a VGA con- troller (such as the W5186) share a RAMDAC, the RAM- DAC may be controlled by ISA bus I/0 accesses, leaving the Power 9000 RAMDAC control lines unused. Figures 43 and 44 present the tempIates used by the VRAM controller to perform RAMDAC reads and writes. SYSCLK FA[8..O] WE~ r~ ..Ol- (DAC CNTL) RAS[1 ..O]- CAS[3..O]- OE- WEO[3..O]- DACCE- wE ~ [21- (DAC ~ Figure 43. RAMDAC read 38 -------------------------------------------------------------------------------- POWER 9000 USER INTERFACE CONTROLLER October 1992 2.4. RAMDACs, continued WE1 [1..O]- (DAC CNTL) RAS[1..O]- CAS[3..O]- OE- WEO[3..O]- WEll3]- DACCE- WE 1 [2]- (DAC RW) Figure 44. RAMDAC write 39 --------------------------------------------------------------------------------