From piziali!andy@sulaco.lonestar.org Mon Oct 25 19:45:41 1993 From: andy@piziali.lonestar.org (Andrew J. Piziali) Subject: Trial OCR Run Weitek's Power9000 User Interface Controller Data Book, Oct. 1992 ======================================================================== front cover: POWER 9000 USER INTERFACE CONTROLLER Contents 1. Overview 1 2. Host, Video, and Frame Buffer Interfaces 15 3. Instruction and Register Formats41 4. Drawing Operation 73 5. Sample Programs 99 6. Pseudo-code for Definition of the Power 9000 123 7. Specifications 141 Documentation Request Form 163 Sales Offices back cover ======================================================================== inside front cover: Power9000 User Interface Controller Data Book October 1992 Copyright (c) WEITEK Corporation 1992 All rights reserved WEITEK Corporation 1060 East Arques Avenue Sunnyvale, California 94086 Telephone (408) 738-8400 WEITEK and WEITEK Power are trademarks of WEITEK Corporation. Brooktree is a registered trademark of Brooktree Corporation. Display PostScript Systems is a trademark of Adobe Systems, Inc. Microsoft Windows graphical environment version 3.0 is a trademark of Microsoft Corporation. SunView is a trademark of Sun Microsystems, Inc. Microsoft Windows is a registered trademark and Windows is a trademark of Microsoft Corporation. AutoCAD is a registered trademark of Autodesk, Inc. WEITEK Corporation assumes no responsibility for errors in this document, and retains the right to make changes at any time, without notice. Please contact your sales office to obtain the latest specifications before placing your order. Written by D.R. Sevedge and Robert Plamondon Additional writing by Gerry Gras and Tovye Kanter-Henderson Edited by Robert Plamondon Illustrations by Emie Duran, Keith Evans. Suzanne Foster. Tovye Kanter-Henderson. Mary Kantor, Robert Plarnondon, D.R. Sevedge, and Paul Woodside Programs by Terry Thomas Additional programming by Gilad Golan. Frank Palazzolo, Ed Semplinski. and D.R. Sevedge Production by Suzanne Foster, Mary Kantor, Tricia Machado, Robert Plamondon. D.R. Sevedge, and Paul Woodside Printed in the United States of America 9392 654321 DOC 9211 4710-9211-00 Rev. C ======================================================================== page i: POWER 9000 USER INTERFACE CONTROLLER October 1992 Contents Chapter 1. Overview, 1 1.1. Description, 1 1.2. Block Diagram, 2 1.3. Architecture, 3 1.3.1. Parameter Engine, 3 1.3.2. Drawing Engine, 3 1.3.3. Host Interface, 3 1.3.4. Frame Buffer Controller, 3 1.3.5. Video Controller, 4 1.4. Signal Description, 5 1.4.1. Host Bus Interface Signals, 5 1.4.2. System Signals, 7 1.4.3. Video Display Signals, 7 1.4.4. Frame Buffer Signals, 7 1.4.5. RAMDAC Control Signals, 8 1.5. Graphics Operation, 9 1.5.1. The Graphics Pipeline, 9 1.5.2. Drawing Quadrilaterals, 9 1.5.3. Drawing Bit Maps, 10 1.5.4. Bit Block Transfer, 10 1.5.5. Color Selection, 10 1.6. Performance, 11 1.7. Controller Examples, 12 1.8. Software and Development Tools, 14 1.9. Specifications, 14 1.9.1. Package, 14 1.9.2. Speed, 14 1.9.3. Frame Size, 14 1.9.4. Monitor Refresh Rates, 14 1.9.5. Monitor Types, 14 1.10. Related Documents, 14 Chapter 2. Host, Video, and Frame Buffer Interfaces, 15 2.1. Host Bus Interface, 15 2.1.1. Host Requests, 15 2.1.2. Host Addressing, 16 2.1.3. Data Transfer, 16 2.1.4. Clocks, 16 2.1.5. Interrupts, 16 2.1.6. Multiplexed Host Bus Design, 16 2.1.7. Non-multiplexed Host Bus Design, 2.1.8. Asynchronous Host Bus Design, 16 2.1.9. Host Bus Interface State Machine, 17 2.1.10. Host Bus Read Operations, 17 2.1.11. Host Bus Write Operations, 20 2.2. Video Control, 22 2.2.1. Video Signals, 22 2.2.2. Video Control Registers, 22 2.2.3. Video Timing, 24 2.2.4. Programming The Video Controller, 26 2.2.5. External Synchronization, 28 2.2.6. Screen Repaint Control, 28 2.3. Frame Buffer Design Notes, 29 2.3.1. Memory Configurations, 29 2.3.2. System Integration of VRAMs, 33 2.3.3. Frame Buffer Timing Diagrams, 33 2.4. RAMDACs, 38 i ======================================================================== page ii: Chapter 3. Instruction and Register Formats, 41 3.1. Overview, 41 3.1.1. Conventions And Notation, 41 3.1.2. Big-endian and Little-endian Modes, 42 3.2. General Address Formats, 43 3.2.1. Video and System Control Register Address Format, 43 3.2.2. User Register Address Format, 43 3.2.3. Pixel Address Format, 43 3.2.4. RAMDAC Address Format, 43 3.2.5. Non-Power 9000 Address Format, 43 3.3. Address Mapping, 45 3.4. Registers, 46 3.4.1. System Control Registers, 49 3.4.2. Parameter Engine Registers, 53 Chapter 4. Drawing Operation, 73 4.1. Overview, 73 4.1.1. Legal Quadrilaterals, 73 4.1.2. Drawing Modes, 73 4.1.3. Basic Quad Drawing Methods, 74 4.1.4. Negative Coordinates, 74 4.1.5. Minterms, 74 4.1.6. Flow Control, 76 4.1.7. Exception Handling, 76 4.2. Drawing Quadrilaterals, 77 3.4.3. Drawing Engine Registers, 59 3.4.4. Video Control Registers, 62 3.4.5. VRAM Control Registers, 65 3.5. Meta-Coordinate Pseudo-Registers, 67 3.6. Commands, 68 3.6.1. Quad Command, 68 3.6.2. Blit Command, 68 3.6.3. Pixel8 Command, 69 3.6.4. Pixel1 Command, 69 3.6.5. Next_pixels Command, 71 4.3. Defining and Applying a Clipping Window, 84 4.4. Performing BitBit Operations, 85 4.5. Applying a Pattern, 87 4.6. Drawing with Pixel1, 90 4.7. Applying Transparency, 92 4.8. Drawing Characters with Pixel1, 94 4.9. Drawing with Pixel8, 96 Chapter 5. Sample Programs, 99 5.1. Routines Used throughout the Sample Programs, 99 5.1.1. Initialization Routine, 99 5.1.2. Demo Initialization Routine, 100 5.1.3. Color Initialization Routine, 100 5.2. Drawing Quadrilaterals, 102 5.3. Defining and Applying a Clipping Window, 105 5.4. Performing BitBit Operations, 107 5.5. Applying a Pattern, 109 5.6. Drawing with Pixel1, 112 5.7. Applying Transparency, 114 5.8. Drawing Characters with Pixel1, 116 5.9. Drawing with Pixel8, 119 ii ======================================================================== page iii: POWER 9000 USER INTERFACE CONTROLLER October 1992 Chapter 6. Pseudo-Code for Definition of the Power 9000, 123 6.1. Introduction, 123 6.5.3. Calculate_Rop Subroutine, 130 6.2. Coordinate Register Load and Store, 124 6.6. The Blit Operation, 133 6.3. Meta-Coordinate Register Load, 125 6.7. The Quad Draw Operation, 135 6.4. Load/Store Register Support Routines, 127 6.8. The Pixe18 Operation, 135 6.5. Subroutine Operations, 130 6.5.1. Put_Pixel Subroutine, 130 6.5.2. Compute_Linear Subroutine, 130 6.9. The Pixell Operation, 138 6.10. The Next_pixels Operation, 139 Chapter 7. Spedfications, 141 7.1. DC Specifications, 141 7.1.1. Absolute maximum ratings, 141 7.1.2. Recommended Operating Conditions, 141 7.1.3. Pin Capacitance, 141 7.1.4. DC Characteristics, 141 7.2. AC Specifications, 142 7.3. Host Bus Timing Parameter Definitions, 146 7.4. VRAM Timing Parameter Definitions, 149 7.5. Video Timing Parameter Definitions, 156 7.6. Pin Configuration, 157 7.7. Physical Parameters, 158 7.7.1. QFP Packaging Illustration, 158 7.8. Test Conditions, 159 7.9. I/O Characteristics, 160 7.10. Ordering Information, 161 Documentation Request Form, 163 iii ======================================================================== page 1: POWER 9000 USER INTERFACE CONTROLLER Chapter 1. Features 2-D GRAPHICS ACCELERATOR Single-chip controller Accelerates Microsoft Windows and AutoCAD Supports X-Windows drawing modes POWERFUL GRAPHICS PRIMITIVES Draws lines and polygons with pattern fill at full VRAM bandwidth (up to 132 million pixels per second, and 1.53 million vectors per second) Performs bit block-transfer (BitBit) from screen to screen at VRAM bandwidth (up to 40 million pixels per second), and from host to screen at host bus bandwidth Supports two BitBit modes: one with color expansion for text, the other for graphics Supports patterning, plane masking, and boolean opera- tions of pixels during drawing Performs automatic clipping against window and screen edges Supports polylines and mesh polygons for faster drawing Supports pick mode Supports resolutions up to 1600xl200x8, 1280xl024x8, 1024x768x16, and 800x600x24 HIGH INTEGRATION Supports 32-bit non-multiplexed general host interface 32-bit interleaved memory interface supports 1,2, or 4MB (double buffered) VRAM frame buffer Supports video rates to 165 MHz; connects directly to a standard 32-bit serial RAMDAC interface (such as the Bt 458,459, or compatible) SOFTWARE SUPPORT Windows 3.0/3.1 AutoCAD R10 and R11 1.1. Description The WEITEK Power 9000 User Interface Controller is an accelerated 2-D graphics device used with Microsoft Win- dows and AutoCAD. It supports draw, fill, and bit block-transfer operations at the full speed of interleaved page-mode VRAMs -- 132 million pixels per second -- at screen sizes of up to 2 million pixels. The Power 9000 is a single 25-33 MHz CMOS chip which comes in a 208-pin PQFP (Plastic Quad Flat Package). ======================================================================== page 2: figure 2 power 9000 block diagram ======================================================================== page 3: POWER 9000 USER INTERFACE CONTROLLER 1.3. Architecture At the chip level, the Power 9000 is a hard-wired graphics processor. Its operation is determined by its internal regis- ters and by command words sent over the host interface bus. At the system level, it is a memory-mapped peripheral. It operates as a bus slave; the host initiates all bus reads and writes. This results in simple interface and programming models. With its direct control of VRAMs, the Power 9000 draws at the speed of its memory system. The VRAM frame buff- er runs in interleaved mode for maximum performance, us- ing standard VRAMs. The Power 9000 feeds video data into a RAMDAC, which contains internal color look-up tables and digital-to-analog converters. The graphics board then feeds the resulting analog RGB video signal, along with the horizontal and vertical synchronization sig- nals generated by the Power 9000, into a high-resolution color monitor with a screen size of up to 2 megapixels. The Power 9000 contains the following functional units: the parameter engine, the drawing engine, the host inter- face, the frame buffer controller, and the video controller. 1.3.1. PARAMETER ENGINE The parameter engine prepares drawing operations for the drawing engine; its basic function is to take input coordi- nates from the host and convert them to a form usable by the drawing engine. The input parameters include the x,y vertices of polygons and the corners of bit block-transfer (BitBit) regions. The parameter engine tests the vertices against window and screen boundaries, tests for excep- tions, and performs trivial rejection. Finally, it transfers commands that pass these tests to the drawing engine to be executed. The parameter engine prepares four kinds of "polygons" for drawing: quadrilaterals, triangles, lines, and points. It converts points, lines, and triangles into quadrilaterals by automatically replicating vertices; a point, for example, is a quadrilateral with all four vertices at the same x,y loca- tion. Thus, the user has to load only a single vertex to draw a point; the parameter engine passes four copies of that ver- tex to the drawing engine and instructs it to draw a quad. The parameter engine also handles screen-to-screen BitBit and two kinds of host-to-screen BitBit, one optimized for text and the other optimized for graphics. The parameter engine handles all exception testing and access to parame- ter engine registers, while it passes operations that actually write to the display to the drawing engine. 1.3.2. DRAWING ENGINE The drawing engine performs three basic functions: ( 1 ) It draws quadrilaterals (the quad operation), (2) it performs October 1992 screen-to-screen BitBit (the blit operation), and (3) it per- forms host-to-screen BitBit (the pixell and pixe18 opera- tions). The quad operation draws quadrilaterals in one of two modes: XI I mode, an X-Windows compatible mode, and oversized mode, a Bresenham mode. Triangles, lines, and points can always be rendered correctly, but the drawing engine cannot draw horizontally convex quadrilaterals. That is, it cannot cross from the inside to the outside of the same object more than once per scan line. This means that "bowties" cannot be drawn (such quads must be rendered in software), though "hourglasses" can (see figure 3). The blit operation copies a rectangular area of the display from one screen location to another. The pixel1 operation takes monochrome, one-bit-per-pix- el data from the host, expands the pixels internally to eight bits per pixel, and writes them to the frame buffer. Up to 32 pixels can be transferred to the Power 9000 in a single word. The pixel8 operation takes color, eight-bits-per-pix- el data (up to four pixels per word), and writes them to the frame buffer. 1.3.3. HOST INTERFACE The Power 9000 appears to the host as an array of memory. The Power 9000 uses only the lower 22 address bits. The chip ignores higher-order bits; external glue logic generally decodes them to distinguish Power 9000 from non-Power 9000 bus accesses. Half of this space (2 MB) is used for direct frame-buffer access, allowing the host to use the Power 9000 as a dumb frame buffer; IMB is reserved for non-Power 9000 operations. The rest of the address space is decoded into Power 9000 instructions. Power 9000 commands are specified by the address, allowing the data bus to be devoted solely to data transfers and minimizing the number of bus accesses. The Power 9000 supports both big-endian and little-endian address formats. It can run with both multiplexed and non-multiplexed buses, and run either synchronously or asynchronously to the bus clock. 1.3.4. FRAME BUFFER CONTROLLER The Power 9000 controls the VRAM frame buffer directly; VRAM chips are wired directly to the Power 9000 (the Power 9000 has high-current output drivers to support this). Frame-buffer control registers in the Power 9000 de- termine the VRAM refresh rate, the screen size, and single- or double-buffering; they also select interleaved or non-in- terleaved VRAM modes. The host initializes these registers at system start-up. 3 ======================================================================== page 4: 1.3. Architecture, continued 1.3.5. VIDEO CONTROLLER A typical board design feeds the VRAM shift registers into a Brooktree-compatible RAMDAC, which uses a color lookup table to convert eight-bit pixel data into a 24-bit analog video signal. The host initializes the control regis- ters and look-up tables in the RAMDAC through the Pow- er 9000's RANIDAC access instructions. The Power 9000 also generates horizontal and vertical synchronization signals and controls the clocking of the video data. The divided dot clock used by the Power 9000's video subsection is completely asynchronous to the Power 9000's main system clock. 4 ======================================================================== page 4: POWER 9000 USER INTERFACE CONTROLLER October1992 1.4. Signal Description Signal Subsystem Definition ----------------------------------------------------------------- CAS[3..O]- Frame Buffer Column address strobe output signals CBLNKNBLNK- Video Composite blank/vertical blank output signal CSYNC/HBLNK- Video Composite synchronization/horizontal blank output signal DACCE- RAMDAC Control RAMDAC enable output signal DDOTCLK Video Divided dot clock input signal DSF Frame Buffer Shift register load control output signal FA[8..O] Frame Buffer Frame buffer output address lines FBDATA[31 ..0] Frame Buffer Frame buffer I/0 data bus HA[21 ..0] Host Bus Interface Host to Power 9000 input address bus HAEN- Host Bus Interface Host address clock enable input signal HBCK Host Bus Interface Host bus clock input signal HD[31 ..0] Host Bus Interface Host to Power 9000 I/0 data bus HDRIVE- Host Bus Interface Host bus data output enable input signal HREAD Host Bus Interface Host read/write input signal HRDY- Host Bus Interface Host bus ready output signal HREQ- Host Bus Interface Host request input signal HSIZE[1 ..0] Host Bus Interface Host transfer size input signals HSYNC- Video Horizontal synchronization input/output signal INTR- Host Bus Interface System interrupt request output signal OE- Frame Buffer Frame buffer data transfer/output enable output signal RAS[1 ..0]- Frame Buffer Row address strobe output signals RESET- Host Bus Interface System reset input signal STLOAD Frame Buffer Self-timing load output signal SYSCLK Subsystem Power 9000 system clock input signal VDDPLL Frame Buffer Supply voltage for on-chip clock generator VSSPLL Frame Buffer Ground for on-chip clock generator VSYNC- Video Vertical synchronization input/output signal WEO[3..O]-. WE1 [3..0]- Frame Buffer Frame buffer write enable output signals -------------------------------------------------------------------------- Figure 4. Power 9000 signals 1.4.1. HOST BUS INTERFACE SIGNALS HOST ADDRESS BUS The HA[21 ..0] host address bus is the 22-bit synchronous, unidirectional address bus from the host system processor to the Power 9000. This bus specifies the Power 9000 com- mand. The two low order bits, combined with the HSIZE[1 ..0] host transfer size signals, define the data bus bytes to be written to the Power 9000 (see figure 5). For a host read, the Power 9000 drives an entire word of data onto the data bus; the Power 9000 ignores the two low or- der address bits and the host transfer size. HOST TRANSFER SIZE The HSIZE[l ..0] host transfer size input signals, combined with the two lowest host address bus signals, determine which bytes are valid on the data bus to write to the Power 9000. See figure 5. Figure 6 defines the equivalencies between the Power 9000 HA[1..0] and HSIZE[l..0] bits and the EISA/VESA local bus bits be[3..O]-. ======================================================================== page 6: 1.4. Signal Description, continued HOST DATA BUS The HD[31..0] host data bus is the 32-bit bidirectional data bus between the Power 9000 and the host system proces- sot. This bus allows direct transfer of data to and from each of the major Power 9000 units (the parameter engine, the drawing engine, the frame buffer controller, and the video controller). HOST ADDRESS REGISTER ENABLE The HAEN- host address register enable input signal en- ables data transfer to the host address register on the rising edge of the host bus clock, HBCK. This function is neces- sary only when the host employs a multiplexed bus for transferring addresses and data (the signal can be tied low for hosts with separate address and data buses). The host bus clock (HBCK) clocks the address into the address regis- ter only if HAEN- is asserted; otherwise, the register holds its previous value. HA[1 ..0] are not latched in the host ad- dress register (these bits are not used by that circuitry which uses the host address register). HOST BUS CLOCK The HBCK host bus clock input signal clocks the host ad- dress register. This clock signal can be asynchronous to the Power 9000 clock (see chapter 2). HOST REQUEST The HREQ- host request input signal indicates host initia- tion of a Power 9000 read or write. The HREAD signal de- termines the direction of the data transfer. The Power 9000 accepts a host request only when the Power 9000 host in- terface is ready (HRDY- asserted). HOST READ The HREAD host read input signal is a read/write signal for host requests. Asserting both HREAD and HREQ- ini- tiates a read; asserting HREQ- without asserting HREAD initiates a write. HOST DRIVE The HDRIVE- host drive input signal is an asynchronous tri-state enable for driving data from the Power 9000 to the host data bus. This signal is driven by external logic. Its as- sertion forces the Power 9000 to drive data onto the host bus. HOST BUS READY The HRDY- host bus ready output signal is asserted when the Power 9000 is ready to accept a request. The Power 9000 deasserts this signal for at least one cycle after accept- ing a host request. For a read, the Power 9000 deasserts HRDY- when it starts the read and re-asserts HRDY- one cycle before the data is valid. 6 ======================================================================== page 7: POWER 9000 USER INTERFACE CONTROLLER October 1992 1.4. Signal Description, continued INTERRUPT The lNTR- system interrupt output signal indicates a Pow- er 9000 interrupt request. This is an open-drain signal; it is driven low when asserted and floats when deasserted. RESET The RESET- system reset input signal performs a system reset on the Power 9000. The system reset signal may be asynchronous to the system clock. The RESET- signal must be asserted for a minimum of 50 SYSCLK cycles. While RESET- remains asserted, no VRAM, video, or host bus activities can occur. The Power 9000 deasserts all VRAM control signals (RAS[l ..0]-, CAS[3..O]-, WE0[3..0]-, WE1[3..0]-, and OE-) and puts the frame buffer data bus lines (FBDATA[31 ..0]), the host data bus (HD[3..O]), and the system interrupt signal (lNTR-) into the high-impedance state. A system reset affects the Power 9000 registers as summa- rized in Chapter 3, figure 57. 1.4.2. SYSTEM SIGNALS SYSTEM CLOCK The SYSCLK system clock input is the main Power 9000 clock signal. The Power 9000 system clock may be asynch- ronous to all other clocks in the system. 1.4.3. VIDEO DISPLAY SIGNALS DIVIDED DOT CLOCK The DDOTGkK divided dot clock input signal is the clock signal used to generate all video control signals. This signal is generated by external logic. Since the dot clock usually exceeds the Power 9000's maximum frequency, the Power 9000 accepts a divided dot clock. The divided dot clock is most commonly the dot clock divided by four, but the divi- sorcan be any power of two that produces a signal that sat- isfies the Power 9000's maximum frequency. HORIZONTAL SYNCHRONIZATION The HSYNG- horizontal syncbronization signal can be used as either an output signal or an input signal. When de- fined as an output signal, HSYNC- drives the horizontal synchronization signal used by the monitor, RAMDAC, and timing logic. When HSYNG- is defined as an input sig- nal, the Power 9000 accepts an external horizontal syn- chronization signal and generates screen repaints based upon that signal's timing. A system reset defines HSYNG- as an input signal by clearing the screen repaint timing control (srtctl) register (see section 3.4.4). VERTICAL SYNCHRONIZATION The VSYNC- vertical synchronization signal can be used as either an output signal or an input signal. When defined as an output signal, VSYNG- drives the vertical synchroni- zation signal used by the monitor, RAMDAC, and timing logic. When VSYNC- is defined as an input signal, the Power 9000 accepts an external vertical synchronization signal and generates screen repaints based upon that sig- nal's timing. A system reset defines VSYNC- as an input signal by clearing the screen repaint timing control (srtctl) register (see section 3.4.4). COMPOSITE SYNCHRONIZATION/HORIZON- TAL BLANK The GSYNC/HBLNK- output signal can be used either as a composite synchronization (combined horizontal and ver- tical synchronization) signal or as a horizontal blank sig- nal. As a composite syncbronization signal, it is a combination of HSYNC- and VSYNC-. As a horizontal blank signal, it generates the horizontal blanking signal used by the monitor and the timing logic. A system reset defines GSYNG/HBLNK- as a horizontal blank signal by clearing the screen repaint timing control (srtctl) register (see section 3.4.4). COMPOSITE BLANK/VERTICAL BLANK The CBLNK/VBLNK- output signal can be used either as a composite blank signal or as a vertical blank signal. In ei- ther case, the monitor and timing logic use the signal. A system reset automatically defines CBLNK/VBLNK- as a vertical blank signal by clearing the screen repaint timing control (srtctl) register (see section 3.4.4). 1.4.4. FRAME BUFFER SIGNALS ROW ADDRESS STROBE The RAS[1..0]- row address strobe output signals connect directly to the VRAM RAS inputs. COLUMN ADDRESS STROBE Each of the GAS[3..0]- column address strobe output sig- nals connects directly to the VRAM CAS inputs. The mul- tiple CAS lines reduce loading and enable double buffering (see chapter 2). WRITE ENABLE The WE0[3..0]- and WE/[3..0]- write enable output sig- nals connect directly to the VRAM WB/WE- signals. These signals provide a byte write control, enabling indi- vidual eight-bit pixels to be written with a 32-bit bus trans- fer. 7 ======================================================================== page 8: 1.4. Signal Description, continued Chapter 2 defines how these signals must be connected for vari- ous VRAM configurations. The WE1 [2..0]- signals also function as control signals for the host access port of the RAMDAC, as illustrated in figures in chapter 2. WE1 [1 "O]- control the RAMDAC control signals (CO and C1) and WE1[2]- controls the RAMDAC R/W signal. OUTPUTENABLE The OE- output enable output signal enables transfer of data from the VRAMs. The OE- signal connects directly to the DT/OE- signal for each VRAM. FRAME BUFFER DATA BUS The FBDATA[31 ..0] frame buffer data bus is the 32-bit bi- directional data bus connected through damping resistors to the VRAMs in each bank. FRAME BUFFER ADDRESS B US The FA[8..0] frame buffer address bus is a nine-bit multi- plexed output bus connected directly to the VRAM ad- dress lines in both banks, through damping resistors. SPECIAL FUNCTION CONTROL The DSF special function control input signal controls split-shift register loads. This signal is connected to the of each VRAM. See the VRAM specifications for de- tails. CLOCK GENERATOR SUPPLY VOLTAGE The VDDPLL clock generator supply voltage output signal supplies voltage for the on-chip clock generator. Keep the supply as clean as possible; you may want to use a voltage regulator. CLOCK GENERATOR GROUND The VSSPLL clock generator ground output signal sup- ' plies the ground for the on-chip clock generator. Decouple VDDPkL to VSSPLk with a .1uF capacitor located as close to the pins as possible. 1.4.5. RAMDAC CONTROL SIGNALS RAMDAC CHIP ENABLE The DACCE- RAMDAC chip enable output signal en-' ables a data transfer to or from the RAMDAC. This signal connects directly to the RAMDAC CE- signal. [2] signal determines the direction of the transfer; the ' WE1 [1 ..0] signals determine the transfer type. NOTE: This signal is intended to control workstation RAMDACs. For PCs, it may be unused, with the DAC connected to the ISA bus. SELF-TIMING LOAD The STLOAD self-timing load output signal is used to gen- erate VRAM timings. It should be connected to a capacitor equal in value to the capacitance of the most heavily loaded FA line. 8