From: Thomas McWilliams <tmcwill@holonet.net>
Newsgroups: comp.os.linux.announce
Subject: Linux and the PowerPC
Date: 24 Jul 1993 15:10:12 -0400
Approved: linux-announce@tc.cornell.edu (Matt Welsh)
Message-ID: <22s1ek$6d5@theory.TC.Cornell.EDU>

There has been some discussion about implementing Linux on new
architectures. One promising  architecture is the PowerPC
architecture co-developed by IBM and Motorola. Because of its
low-cost and high-performance, there are many in the industry who
believe that this architecture will be the replacement for the
aging Intel x86 line in desktop and commodity computer
applications. Taiwanese motherboard makers are said to have
started sampling the MPC601 chip as of early this past spring.
This article will try to provide a little background information
on the MPC601.

As of July 1993, the MPC601 is the initial entry in this new line.
Raw bench-mark comparison to Intel's top of the line Pentium
(a.k.a. 586)  shows that the MPC601 offers better floating point
performance, equivalent integer performance, at less than half
the heat dissipation (7 Watts versus Intel's 16 Watts). Real
world performance may actually be better when one considers the
MPC601 has 32 general purposes registers and 32 floating point
registers which, when properly used, can aid software
performance significantly.

The MPC601 currently (July '93) is priced at approximately $400.
This is less than half the cost of the Pentium. The MPC601's 1.5
Million transistor count versus Pentium's 3 Million transistor
count suggest that MPC601 fabrication yields will continue to be
higher. It also suggests that the cost differential is not
entirely artificial (i.e. it simply costs more to make a
Pentium). 

Below you will find a table taken from Motorola literature which
summarizes MPC601 features. Let me add the disclaimer that I have
no association with IBM, or Motorola, and that I offer no
advocacy for any processor or manufacturer. I merely present this
for informational purposes. If you find an error feel free to
correct it. Any flames to me should me sent via e-mail to save
bandwidth. Let me repeat, I offer no advocacy one way or the
other. Like most Linux users I welcome choice in the market
place, and ultimately I base any purchasing decision on what
offering has the most bang for the buck, commensurate with my
needs.

     -----------------------------------------------
     Motorola MPC601 PowerPC Microprocessor Features
     -----------------------------------------------

* High-performance, superscaler microprocessor
   - As many as 3 instructions in execution per clock (one to each
     of the three execution units).
   - Single clock cycle execution for most instructions.
   - Pipelined FPU for all single-precision and most double-
     precision operations.

* Three independent execution units and two register files
   - BPU (Branch Processing Unit) featuring static branch prediction.
   - 32 bit IU (Integer Unit). 
   - Fully IEEE 754-compliant FPU for both single- and double-
     precision operations.
   - Thirty-two (32) GPRs (general purpose registers) for integer operands
   - Thirty-two (32) FPRs (floating point registers) for single- or
     double precision operands.

* High instruction and data throughput
   - Zero-cycle branch capability
   - Programmable static branch prediction on unresolved conditional
     branches.
   - Instruction unit capable of prefetching eight instructions per
     clock from the cache
   - A prefetch queue that can hold as many as eight instructions per
     clock from the cache.
   - Interlocked pipelines with feed-forwarding that control data
     dependencies in hardware.
   - Unified 32-Kbyte internal cache--eight-way set-associative, 
     physically addressed; LRU replacement algorithm.
   - Cache write-back or write-through operation programmable on a per
     page or per block basis.
   - Memory unit with a two-element read queue and a three-element
     write queue.
   - Run-time reordering of loads and stores.
   - BPU that performs condition register (CR) look-ahead operations.
   - Programmable static branch prediction on unresolved conditional
     branches.
   - Address translation facilities for 4-Kbyte page size, variable
     block size,  and 256-Mbyte segment size.
   - A 256-entry, two-way set-associative UTLB.
   - Four-entry, first-level ITLB.    
   - Hardware table search (caused by UTLB misses) through hashed 
     page tables
   - 52-bit virtual address; 32-bit physical address.
   - Four-entry BTLB providing 128-Kbyte to 8-Mbyte blocks.

* Facilities for enhanced system performance
   - Bus speed defined as selectable division of operating frequency.
   - A 64-bit split-transaction external data-bus with burst transfers.
   - Support for address pipelining and limited out-of-order bus
     transactions
   - Snooped copyback queues for cache block (sector) copyback
     operations
   - Bus selection or I/O controller interface operations.
   - Multiprocessing support features that include the following:
      > Hardware enforced, four-state cache coherency protocol (MESI).
      > Separate port into cache tags for bus snooping.  

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