TITLE VIDEO SHIFT REGISTER. PATTERN 01 REVISION 02. AUTHOR CHRIS JAY. COMPANY MMI SANTA CLARA, CA. DATE 20TH AUGUST 1986. ; ;THE PAL32VX10 HAS BEEN DESIGNED AS A VIDEO SHIFT REGISTER ;TO SUPPORT A THREE PAL SOLUTION TO A SMALL VIDEO CONTROLLER ;CIRCUIT. SEVEN INPUTS FROM THE CHARACTER GENERATOR ARE LOADED ;INTO THE INTERNAL SHIFT REGISTER THROUGH INPUTS D1 - D7, ;WHEN THE INTERNAL STATE COUNTER S0,S1 AND S2 CONTAINS A ;ZERO COUNT. DURING STATES ONE TO SEVEN THE CHARACTER DATA ;IS SHIFTED TO THE VIDEO OUTPUT AT A CLOCK RATE OF THE ;APPLIED DOT CLOCK INPUT. THE DEVICE MAY BE ASYNCHRONOUSLY ;RESET AT 'POWER UP'. THE REV INPUT IS A REVERSE VIDEO ;CONTROL, WHEN HIGH REVERSES THE POLARITY OF THE SERIAL ;VIDEO DATA. THE BLANK AND /VSYNC CONTROLS ARE FEEDBACK ;INPUTS FROM THE LINE SYNC AND FRAME SYNC PAL OUTPUTS, ;THESE BLANK VIDEO DATA DURING ACTIVE LINE AND FRAME SYNC ;PERIODS. THE S0, S1 AND S2 OUTPUTS DRIVE THE LINE SYNC ;PAL32VX10 AND ACT AS COUNT ENABLE INPUTS. ; CHIP VIDEO_1 PAL32VX10 ; ;VIDEO SHIFT REGISTER PAL ; ;PINS 1 2 3 4 5 6 CLK /RST D1 D2 D3 D4 ;PINS 7 8 9 10 11 12 D5 D6 D7 BLANK /VSYNC GND ;PINS 13 14 15 16 17 18 REV NC NC NC NC NC ;PINS 19 20 21 22 23 24 NC VIDEO S2 S1 S0 VCC GLOBAL Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 STRING LOAD 'Q8*Q9*Q10' ;ENABLE LOADING OF CHARACTER DATA. ; EQUATIONS ; ; GLOBAL.SETF = RST ;ASYNCHRONOUS RESET. ; /Q10 := Q10 ;INTERNAL STATE COUNTER S0 = Q10 ;LEAST SIGNIFICANT BIT S0.CMBF = GND ;Q10. ENABLE REGISTER ;OUTPUT FOR PIN S0. /Q9 := /Q9 ;INTERNAL STATE COUNTER :+: Q10 ;Q10 = HIGH = TOGGLE. S1 = Q9 ;FUNCTION. ENABLE PIN S1 S1.CMBF = GND ;REGISTERED OUTPUT. ; /Q8 := /Q8 ;INTERNAL STATE COUNTER :+: Q10*Q9 ;Q10*Q9 = HIGH = TOGGLE. S2 = Q8 ;ENABLE PIN S2 AS A S2.CMBF = GND ;REGISTERED OUTPUT. ; ; /Q1 := /D1*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D1. + D1*LOAD*REV*/BLANK*/VSYNC ; + /Q8*/REV ;SHIFT HIGH INTO Q1. + /Q9*/REV ; + /Q10*/REV ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q2 := /D2*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D2. + D2*LOAD*REV*/BLANK*/VSYNC ; + /Q1*/Q8 ;SHIFT DATA FROM Q1 + /Q1*/Q9 ;INTO Q2. + /Q1*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q3 := /D3*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D3. + D3*LOAD*REV*/BLANK*/VSYNC ; + /Q2*/Q8 ;SHIFT DATA FROM Q2 + /Q2*/Q9 ;INTO Q3. + /Q2*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q4 := /D4*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D4. + D4*LOAD*REV*/BLANK*/VSYNC ; + /Q3*/Q8 ;SHIFT DATA FROM Q3 + /Q3*/Q9 ;INTO Q4. + /Q3*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q5 := /D5*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D5. + D5*LOAD*REV*/BLANK*/VSYNC ; + /Q4*/Q8 ;SHIFT DATA FROM Q4 + /Q4*/Q9 ;INTO Q5. + /Q4*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q6 := /D6*LOAD*/REV*/BLANK*/VSYNC ;LOAD DATA INPUT D6. + D6*LOAD*REV*/BLANK*/VSYNC ; + /Q5*/Q8 ;SHIFT DATA FROM Q5 + /Q5*/Q9 ;INTO Q6. + /Q5*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; ; /Q7 := /D7*LOAD*/REV*/BLANK*/VSYNC ; + D7*LOAD*REV*/BLANK*/VSYNC ; + /Q6*/Q8 ; + /Q6*/Q9 ; + /Q6*/Q10 ; + BLANK*/REV ; + VSYNC*/REV ; /VIDEO = /Q7 /VIDEO.CMBF = GND ;OUTPUT Q7 TO VIDEO. SIMULATION ;START OF SIMULATION TRACE_ON CLK RST S0 S1 S2 ;TRACE ALL ESSENTIAL VIDEO /VSYNC BLANK ; REV D1 Q1 D2 Q2 ;INPUTS AND OUTPUTS. D3 Q3 D4 Q4 D5 ; Q5 D6 Q6 D7 ; SETF /CLK RST /REV ;SET INITIAL CONDITIONS. /D1 /D2 D3 D4 ;APPLY ACTIVE RESET. D5 /D6 /D7 ; /BLANK /VSYNC ; SETF /RST ; FOR K := 1 TO 7 DO ; BEGIN ; CLOCKF CLK ; END FOR J := 0 TO 4 DO ;GENERATE FOUR LOOPS. BEGIN ; IF J = 1 THEN ; BEGIN SETF VSYNC ;SET VSYNC TO TEST END ;BLANKING. IF J = 2 THEN ; BEGIN SETF /REV BLANK /VSYNC ;TEST ACTIVE BLANK END ;INPUT. REMOVE ACTIVE IF J = 3 THEN ;VSYNC. BEGIN SETF D1 /D2 D3 /D4 ;SET BLANKING CONTROLS D5 /D6 D7 /BLANK ;INACTIVE TEST THE END ;LOADING AND SHIFTING IF J = 4 THEN ;OF DATA. BEGIN SETF /REV ;SET THE REV INPUT AS END ;INACTIVE. FOR I := 1 TO 16 DO ;GENERATE TWO LOOPS BEGIN ;TO LOAD AND SHIFT IF I = 9 THEN ;DATA AS NORMAL AND BEGIN SETF REV ;REVERSE VIDEO. END ; CLOCKF CLK ; END ; END ; TRACE_OFF ;END OF SIMULATION