TITLE UNIVERSAL PORT INTERFACE ADAPTOR ; FOR THE MC68020 32-Bit MICROPROCESSOR PATTERN PORT INTERFACE. REVISION 06. AUTHOR VINCENT J. COLI. COMPANY MONOLITHIC MEMORIES INC, SANTA CLARA, CA. DATE 23 NOVEMBER 1985. CHIP PORT_INTERFACE PAL20RA10 ;PIN 1 2 3 4 5 6 /PL /CS CLK /ECS /AS SIZ1 ;PIN 7 8 9 10 11 12 SIZ0 PS1 PS0 WS0 WS1 GND ;PIN 13 14 15 16 17 18 /OE /DSACK0 /DSACK1 /LLD /LMD /UMD ;PIN 19 20 21 22 23 24 /UUD Q0 Q1 A0 A1 VCC ; ;PIN DESCRIPTION ; ;PIN 1 : /PL..PRELOAD INPUT. /PL IS TAKEN INACTIVE HIGH ; : FOR NORMAL OPERATION. TO EFFECT A PRELOAD THE ; : THE OUTPUT BUFFERS ARE PUT INTO A 3 - STATE ; : CONDITION. DATA IS PLACED ON THE OUTPUT PINS ; : AND /PL IS TAKEN ACTIVE LOW. THE PRELOAD DATA ; : FALLS THROUGH INTO THE REGISTER ARRAY. THIS ; : PIN IS PULLED HIGH FOR NORMAL OPERATION. ;PIN 2 :/CS..EXTERNAL INPUT THAT IS DECODED FROM THE ; : MICROPROCESSORS HIGHER ORDER ADDRESS LINES WHICH ; : GOES ACTIVE LOW TO SELECT THE UNIVERSAL PORT ; : ADAPTOR. THIS IS AN ACTIVE LOW INPUT AND COULD ; : BE THE OUTPUT OF ANOTHER PAL DEVICE. ;PIN 3 : CLK..THE MICROPROCESSOR'S SYSTEM CLOCK DRIVES ; : THIS INPUT PIN TO SYNCHRONIZE EVENTS BETWEEN ; : THE 68020 AND THE PAL20RA10. ;PIN 4 : /ECS..INPUT FROM THE 68020 MICROPROCESSOR THAT ; : GOES LOW FOR ONE HALF OF A CLOCK CYCLE TO ; : INDICATE THAT THE MPU IS STARTING A BUS CYCLE. ;PIN 5 : /AS..ADDRESS STROBE FROM THE 68020 TO VALIDATE ; : THE MPU'S FUNCTION CODES, ADDRESS LINES, SIZE ; : OUTPUTS AND R/W CONTROL LINES. ;PIN 6 : SIZ1..SIZE OUTPUT USED WITH SIZ0 TO INDICATE ; : HOW MANY TRANSFERS REMAIN IN A GIVEN BUS CYCLE. ;PIN 7 : SIZ0..SIZE OUTPUT USED WITH SIZ1. ; ;PIN 8 - 9 : PS1,PS0..THESE TWO RESPECTIVE INPUTS TO ; : THE PAL20RA10 MAY BE HARDWIRED TO A ONE ; : OF FOUR DIGITAL CODE. THIS INDICATES WHETHER ; : THE PORT IS NOT PRESENT, BYTE WIDE, WORD WIDE ; : OR LONG WORD WIDE. SEE TRUTH TABLE FOR PORT ; : SIZE SELECTION. ; ;PIN 10 - 11 : WS1 AND WS0 RESPECTIVELY. THE ONE OF FOUR ; : CODES HARDWIRED TO THIS INPUT INDICATE ; : WHETHER ZERO, ONE, TWO OR THREE WAIT ; : STATES SHOULD BE INSERTED IN A GIVEN ; : CYCLE. SEE TRUTH TABLE FOR WAIT STATES. ;PIN 13 : ACTIVE LOW OUTPUT ENABLE FOR THE PAL20RA10. ;PIN 14 : /DSACK0..OUTPUT TO THE 68020, PART OF THE ; : ASYNCHRONOUS HANDSHAKE INDICATING, WITH /DSACK1 ; : THE SIZE OF THE PORT, WHEN THE PORT IS READY FOR ; : ACCESS. ;PIN 15 : /DSACK1..OUTPUT TO THE 68020 USED WITH /DSACK0. ;PIN 16 : /LLD..A COMBINATIONAL ADDRESS DECODE OUTPUT TO ; : SELECT DATA BUS D0 - D7. ACTIVE LOW. ;PIN 17 : /LMD..A COMBINATIONSL ADDRESS DECODE OUTPUT TO ; : SELECT DATA BUS D8 - D15. ACTIVE LOW. ;PIN 18 : /UMD..A COMBINATIONAL ADDRESS DECODE OUTPUT TO ; : SELECT DATA BUS D16 - D23, FOR LONG WORD ; : TRANSFERS AND /LD FOR WORD TRANSFERS. ACTIVE LOW. ;PIN 19 : /UUD..A COMBINATIONAL ADDRESS DECODE OUTPUT TO ; : SELECT DATA BUS D24 - D31, FOR LONG WORD ; : TRANSFERS AND /UD FOR WORD TRANSFERS. AND /CS ; : BYTE TRANSFERS. ACTIVE LOW. ;PIN 20 : Q0..LEAST SIGNIFICANT BIT OUTPUT FROM A TWO ; : BIT COUNTER WHICH INCREMENTS ON EACH WAIT STATE ; : SAMPLE UNTIL THE COUNT IS EQUAL TO THE WS0, WS1 ; : BINARY CODED INPUT. ;PIN 21 : Q1..MOST SIGNIFICANT BIT OUTPUT OF STATE COUNTER ; : USED WITH Q0. ;PIN 22 : A0..LEAST SIGNIFICANT ADDRESS INPUT FROM 68020. ;PIN 23 : A1..NEXT LEAST SIGNIFICANT ADDRESS INPUT FROM ; : 68020. ; EQUATIONS UUD = PS1*PS0*CS*AS*/A1*/A0 ;UPPER UPPER DATA BUS (D31-D24) + PS1*/PS0*CS*AS*/A0 ;UD FOR 16-BIT PORT + /PS1* PS0* CS*AS ;CS FOR 8 BIT PORT ; /UMD = PS0*A1 ;UPPER MIDDLE DATA BUS (D23-D16) + /SIZ1*SIZ0*/A0 ;LD FOR 16-BIT PORT + /CS ; + /AS ; ; LMD = PS1*PS0*CS*AS*A1*/A0 ;LOWER MIDDLE DATA BUS (D15-D8) + PS1*PS0*CS*AS*/SIZ1*/SIZ0*/A1 ; + PS1*PS0*CS*AS*SIZ1* SIZ0*/A1 ; + PS1*PS0*CS*AS*/SIZ0*/A1*A0 ; ; LLD = PS1*PS0*CS*AS*SIZ1*SIZ0*A0 ;LOWER LOWER DATA BUS (D7-D0) + PS1*PS0*CS*AS*/SIZ1*/SIZ0 ; + PS1*PS0*CS*AS*A1*A0 ; + PS1*PS0*CS*AS*SIZ1*A1 ; ; DSACK0 := PS0*/WS1*/WS0*/Q1*/Q0 ;NO WAIT STATES + PS0*/WS1* WS0*/Q1*Q0 ;ONE WAIT STATE + PS0* WS1*/WS0*Q1*/Q0 ;TWO WAIT STATES + PS0* WS1* WS0*Q1*Q0 ;THREE WAIT STATES DSACK0.CLKF = CLK*/DSACK1*/DSACK0 ;CLOCK WHEN DSACK IS UNASSERTED DSACK0.RSTF = /AS ;UNASSERTED ADDRESS STROBE RESETS DSACK0.TRST = CS ;3-STATE WHEN PORT IS NOT SELECTED ; DSACK1 := PS1*/WS1*/WS0*/Q1*/Q0 ;NO WAIT STATES + PS1*/WS1* WS0*/Q1*Q0 ;ONE WAIT STATE + PS1* WS1*/WS0* Q1*/Q0 ;TWO WAIT STATES + PS1* WS1* WS0*Q1*Q0 ;THREE WAIT STATES DSACK1.CLKF = CLK*/DSACK1*/DSACK0 ;CLOCK WHEN DSACK IS UNASSERTED DSACK1.RSTF = /AS ; ; DSACK1.TRST = CS ;3-STATE WHEN PORT IS NOT SELECTED ;INTERNAL STATE COUNTER IS Q0 := /Q0 + Q0*Q1 ;RESET FOR THE START OF EACH Q0.CLKF = CLK ;MEMORY CYCLE. AND IS INCREMENTED Q0.SETF = /AS ;BY THE SYSTEM CLOCK. THE COUNT ;SEQUENCE IS COMPARED WITH THE Q1 := Q0*/Q1 + /Q0*Q1 + Q0*Q1 ;WAIT STATE INPUT. WHEN THE COUNT ;IS EQUAL TO NO OF WAIT STATES Q1.CLKF = CLK ;DSACK IS ASSERTED. AT THE END Q1.SETF = /AS ;EACH CYCLE THE COUNTER RESETS. SIMULATION ;SIMULATION SECTION ; TRACE_ON CLK /ECS /AS PS1 PS0 WS0 WS1 ;SET ZERO WAIT STATES FOR /DSACK0 /DSACK1 Q0 Q1 ;FOR A 32 BIT PORT. SET SETF /PL OE /CLK CS /AS ;INITIAL CONDITIONS. TO MARK /ECS PS1 PS0 /WS1 /WS0 ;END OF PREVIOUS CYCLE. FOR J := 0 TO 3 DO ;APPLY FOUR LOOPS TO TEST BEGIN ;WAIT STATE GENERATION FIRST IF J = 1 THEN ;FOR A 32 BIT PORT. PS0 AND BEGIN SETF /PS0 PS1 /WS1 /WS0 ;PS1 HIGH. WITH PS0 LOW AND END ;PS1 HIGH THE PORT IS 16 IF J = 2 THEN ;BITS WIDE. AND THE LOOP IS BEGIN SETF PS0 /PS1 /WS1 /WS0 ;RE-RUN. WITH PS0 HIGH AND END ;PS1 LOW THE PORT IS BYTE IF J = 3 THEN ;WIDE. NO PORT IS PRESENT BEGIN SETF /PS0 /PS1 /WS1 /WS0 ;WHEN PS0 AND PS1 ARE BOTH END ;SET LOW. SETF CLK ECS ;ECS GO INACTIVE. AT START SETF /CLK /ECS ;OF CYCLE /ECS GOES ACTIVE SETF AS ;FOLLOWD BY AS. FOR I := 1 TO 2 DO ;SYSTEM CLOCK GENERATES BEGIN ;TWO CLOCKS BEFOR THE SETF CLK SETF /CLK ;END OF A CYCLE WITH END ;ZERO WAIT STATES. SETF /AS ;AT END OF CYCLE SET AS SETF CLK ;INACTIVE THEN SET /ECS SETF /CLK /AS /ECS /WS1 WS0 ;INACTIVE. SET WAIT STATE SETF CLK ECS ;INPUT FOR ONE WAIT STATE SETF /CLK /ECS ;/ECS GOES ACTIVE THEN SETF AS ;INACTIVE TO MARK START FOR I := 1 TO 3 DO ;OF CYCLE. FOLLOWED BY BEGIN ;AS GOING ACTIVE. THREE SETF CLK SETF /CLK ;SYSTEM CLOCKS ARE REQUIRED END ;ON THE APPLICATION OF ONE SETF /AS ;WAIT STATE. SET /AS INACTIVE SETF CLK ;AT THE END OF CYCLE. SET SETF /CLK /AS /ECS WS1 /WS0 ;ECS INACTIVE, AND APPLY SETF CLK ECS ;A TWO WAIT STATE INPUT. AT SETF /CLK /ECS ;START OF THE CYCLE ECS GOES SETF AS ;ACTIVE THEN INACTIVE FOLLOWED FOR I := 1 TO 4 DO ;BY THE ADDRESS STROBE. FOUR BEGIN ;SYSTEM CLOCKS ARE REQUIRED SETF CLK SETF /CLK ;WITH TWO WAIT STATES APPLIED. END ; SETF /CLK ;AT THE END OF THE CYCLE SETF /AS ;AS GOES INACTIVE FOLLOWED SETF CLK ;BY ECS. THE WAIT STATE SETF /CLK /AS /ECS WS1 WS0 ;INPUT IS SET FOR THREE. SETF CLK ECS ;AT START OF CYCLE ECS IS SETF /CLK /ECS ;DRIVEN ACTIVE THEN INACTIVE SETF AS ;AS GOES ACTIVE. WITH THE FOR I := 1 TO 5 DO ;APPLICATION OF THREE WAIT BEGIN ;STATES FIVE SYSTEM CLOCKS SETF CLK SETF /CLK ;ARE REQUIRED. END ;AT THE END OF THE THREE SETF /AS ;WAIT STATE CYCLE /AS IS SETF CLK ;DRIVEN INACTIVE. SETF /CLK ; END ; TRACE_OFF ;