;Convolution code encoder, constraint length (k=7)
; 
;This PAL 22V10 design implements a high speed convolutional 
;encoder with a constraint length k=7 and rate = 1/2.  This encoder
;is used commonly in conjuction with a Viterbi, trellis decoding
;algorithm.    Applications    include    geostationary    satellite 
;communication, high speed local loop bypass networkds etc.
 
TITLE		K7ENC.PDS
PATTERN		01
REVISION	01
AUTHOR		JOHN GATES, RAJ PARIPATYADAR
COMPANY 	MULTIPOINT COMMUNICATIONS CORP., MONOLITHIC MEMORIES INC.
DATE		1/27/87
 
CHIP		ENC1 PAL22V10
 
;PINS	1	2	3	4	5	6	7	8
	CLOCK 	INPUT 	RESETn 	DIFFn 	PASSn 	NC  	NC	NC
;PINS	9	10	11	12	13	14	15	16
	NC	NC	NC	GND	OE	DIFFOUT	NC	Q6
;PINS	17	18	19	20	21	22	23	24
	Q5	I	Q	Q4	Q3	Q2	Q1	VCC	
;PINS	25
	GLOBAL
 
;The  CLOCK  defines  the encoder  shift  rate  (typ.  25Mhz).   The 
;aggregate high speed data is fed in via the INPUT PIN.   Q1, Q2, Q3, 
;Q4,  Q5, AND Q6 are the shift register delays whose values are
;shifted with the use of PASSn signal.
 
 
EQUATIONS
 
GLOBAL.RSTF	=  /RESETn
 
DIFFOUT	:=  /DIFFOUT * INPUT
	+  DIFFn * INPUT
	+  DIFFOUT * /DIFFn * /INPUT
 
Q1	:=  DIFFOUT * PASSn * OE
 
Q2	:=  PASSn * Q1 * OE
 
Q3	:=  PASSn * Q2 * OE
 
Q4	:=  PASSn * Q3 * OE
 
Q5	:=  PASSn  * Q4 * OE
 
Q6	:=  PASSn  * Q5 * OE
 
 
I	=  /DIFFOUT * /Q2 * /Q3 * /Q5 *  Q6  * OE
	+  /DIFFOUT * /Q2 * /Q3 *  Q5 * /Q6  * OE
	+  /DIFFOUT * /Q2 *  Q3 * /Q5 * /Q6  * OE
	+  /DIFFOUT * /Q2 *  Q3 *  Q5 *  Q6  * OE
	+  /DIFFOUT *  Q2 * /Q3 * /Q5 * /Q6  * OE
	+  /DIFFOUT *  Q2 * /Q3 *  Q5 *  Q6  * OE
	+  /DIFFOUT *  Q2 *  Q3 * /Q5 *  Q6  * OE
	+  /DIFFOUT *  Q2 *  Q3 *  Q5 * /Q6  * OE
	+   DIFFOUT * /Q2 * /Q3 * /Q5 * /Q6  * OE
	+   DIFFOUT * /Q2 * /Q3 *  Q5 *  Q6  * OE
	+   DIFFOUT * /Q2 *  Q3 * /Q5 *  Q6  * OE
	+   DIFFOUT * /Q2 *  Q3 *  Q5 * /Q6  * OE
	+   DIFFOUT *  Q2 * /Q3 * /Q5 *  Q6  * OE
	+   DIFFOUT *  Q2 * /Q3 *  Q5 * /Q6  * OE
	+   DIFFOUT *  Q2 *  Q3 * /Q5 * /Q6  * OE
	+   DIFFOUT *  Q2 *  Q3 *  Q5 *  Q6  * OE
 
 
Q	=  /DIFFOUT * /Q1 * /Q2 * /Q3 *  Q6  * OE
	+  /DIFFOUT * /Q1 * /Q2 *  Q3 * /Q6  * OE
	+  /DIFFOUT * /Q1 *  Q2 * /Q3 * /Q6  * OE
	+  /DIFFOUT * /Q1 *  Q2 *  Q3 *  Q6  * OE
	+  /DIFFOUT *  Q1 * /Q2 * /Q3 * /Q6  * OE
	+  /DIFFOUT *  Q1 * /Q2 *  Q3 *  Q6  * OE
	+  /DIFFOUT *  Q1 *  Q2 * /Q3 *  Q6  * OE
	+  /DIFFOUT *  Q1 *  Q2 *  Q3 * /Q6  * OE
	+   DIFFOUT * /Q1 * /Q2 * /Q3 * /Q6  * OE
	+   DIFFOUT * /Q1 * /Q2 *  Q3 *  Q6  * OE
	+   DIFFOUT * /Q1 *  Q2 * /Q3 *  Q6  * OE
	+   DIFFOUT * /Q1 *  Q2 *  Q3 * /Q6  * OE
	+   DIFFOUT *  Q1 * /Q2 * /Q3 *  Q6  * OE
	+   DIFFOUT *  Q1 * /Q2 *  Q3 * /Q6  * OE
	+   DIFFOUT *  Q1 *  Q2 * /Q3 * /Q6  * OE
	+   DIFFOUT *  Q1 *  Q2 *  Q3 *  Q6  * OE
	 
 
 
SIMULATION
 
TRACE_ON 	INPUT  RESETn  PASSn DIFFn OE  Q1 Q2 Q3  Q4  Q5  Q6 
		DIFFOUT I Q
 
SETF OE	 SETF /RESETn  SETF PASSn  SETF /DIFFn  SETF /INPUT  CLOCKF
SETF RESETn
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF /INPUT  CLOCKF
 
 
SETF OE	 SETF /RESETn  SETF PASSn  SETF DIFFn  SETF /INPUT CLOCKF
SETF RESETn
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF /INPUT  CLOCKF
 
SETF OE	 SETF /RESETn  SETF /PASSn  SETF /DIFFn  SETF /INPUT CLOCKF
SETF RESETn
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF /INPUT  CLOCKF
 
 
SETF OE	    SETF /RESETn  SETF /PASSn  SETF DIFFn  SETF /INPUT CLOCKF
SETF RESETn
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF  INPUT  CLOCKF
SETF /INPUT  CLOCKF
SETF /INPUT  CLOCKF
TRACE_OFF