;PAL32VX10 design ;1/2 rate convolution code encoder, constraint length (k=7) ; ;This PAL 32VX10 design implements a high speed convolutional ;encoder with a constraint length k=7 and rate = 1/2. This encoder ;is used commonly in conjuction with a Viterbi, trellis decoding ;algorithm. Applications include geostationary satellite ;communication, high speed local loop bypass networks etc. TITLE K7ENC.PDS PATTERN 01 REVISION 01 AUTHOR JOHN GATES, RAJ PARIPATYADAR COMPANY MULTIPOINT COMM CORP., MONOLITHIC MEMORIES INC. DATE 1/27/87 CHIP ENC1 PAL32VX10 ;PINS 1 2 3 4 5 6 7 8 CLOCK INPUT RESETn DIFFn PASSn NC NC NC ;PINS 9 10 11 12 13 14 15 16 NC NC NC GND OE DIFFOUT NC Q6 ;PINS 17 18 19 20 21 22 23 24 Q5 I Q Q4 Q3 Q2 Q1 VCC GLOBAL /DIFFOUTi NC /Q6i /Q5i NC NC /Q4i /Q3i /Q2i /Q1i ;The CLOCK defines the encoder shift rate (typ. 25Mhz). The ;aggregate high speed data is fed in via the INPUT PIN. Q1, Q2, Q3, ;Q4, Q5, AND Q6 are the shift register delays whose values are ;shifted with the use of PASSn signal. I and Q are the final outputs. ;The 16 product terms required to calculate I and Q are only ;supported for pins 18 and 19. EQUATIONS GLOBAL.RSTF = /RESETn ;define the reset for all ;registers /DIFFOUTi := /DIFFOUTi * INPUT ;equation for internal node + DIFFn * INPUT + DIFFOUTi * /DIFFn * /INPUT DIFFOUT = DIFFOUTi ;equation for pin /Q1i := DIFFOUTi * PASSn * OE Q1 = Q1i /Q2i := PASSn * Q1i * OE Q2 = Q2i /Q3i := PASSn * Q2i * OE Q3 = Q3i /Q4i := PASSn * Q3i * OE Q4 = Q4i /Q5i := PASSn * Q4i * OE Q5 = Q5i /Q6i := PASSn * Q5i * OE Q6 = Q6i I = /DIFFOUTi * /Q2i * /Q3i * /Q5i * Q6i * OE + /DIFFOUTi * /Q2i * /Q3i * Q5i * /Q6i * OE + /DIFFOUTi * /Q2i * Q3i * /Q5i * /Q6i * OE + /DIFFOUTi * /Q2i * Q3i * Q5i * Q6i * OE + /DIFFOUTi * Q2i * /Q3i * /Q5i * /Q6i * OE + /DIFFOUTi * Q2i * /Q3i * Q5i * Q6i * OE + /DIFFOUTi * Q2i * Q3i * /Q5i * Q6i * OE + /DIFFOUTi * Q2i * Q3i * Q5i * /Q6i * OE + DIFFOUTi * /Q2i * /Q3i * /Q5i * /Q6i * OE + DIFFOUTi * /Q2i * /Q3i * Q5i * Q6i * OE + DIFFOUTi * /Q2i * Q3i * /Q5i * Q6i * OE + DIFFOUTi * /Q2i * Q3i * Q5i * /Q6i * OE + DIFFOUTi * Q2i * /Q3i * /Q5i * Q6i * OE + DIFFOUTi * Q2i * /Q3i * Q5i * /Q6i * OE + DIFFOUTi * Q2i * Q3i * /Q5i * /Q6i * OE + DIFFOUTi * Q2i * Q3i * Q5i * Q6i * OE Q = /DIFFOUTi * /Q1i * /Q2i * /Q3i * Q6i * OE + /DIFFOUTi * /Q1i * /Q2i * Q3i * /Q6i * OE + /DIFFOUTi * /Q1i * Q2i * /Q3i * /Q6i * OE + /DIFFOUTi * /Q1i * Q2i * Q3i * Q6i * OE + /DIFFOUTi * Q1i * /Q2i * /Q3i * /Q6i * OE + /DIFFOUTi * Q1i * /Q2i * Q3i * Q6i * OE + /DIFFOUTi * Q1i * Q2i * /Q3i * Q6i * OE + /DIFFOUTi * Q1i * Q2i * Q3i * /Q6i * OE + DIFFOUTi * /Q1i * /Q2i * /Q3i * /Q6i * OE + DIFFOUTi * /Q1i * /Q2i * Q3i * Q6i * OE + DIFFOUTi * /Q1i * Q2i * /Q3i * Q6i * OE + DIFFOUTi * /Q1i * Q2i * Q3i * /Q6i * OE + DIFFOUTi * Q1i * /Q2i * /Q3i * Q6i * OE + DIFFOUTi * Q1i * /Q2i * Q3i * /Q6i * OE + DIFFOUTi * Q1i * Q2i * /Q3i * /Q6i * OE + DIFFOUTi * Q1i * Q2i * Q3i * Q6i * OE SIMULATION TRACE_ON INPUT RESETn PASSn DIFFn OE Q1 Q2 Q3 Q4 Q5 Q6 DIFFOUT I Q SETF OE SETF /RESETn SETF PASSn SETF /DIFFn SETF /INPUT CLOCKF SETF RESETn SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF /INPUT CLOCKF SETF OE SETF /RESETn SETF PASSn SETF DIFFn SETF /INPUT CLOCKF SETF RESETn SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF /INPUT CLOCKF SETF OE SETF /RESETn SETF /PASSn SETF /DIFFn SETF /INPUT CLOCKF SETF RESETn SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF /INPUT CLOCKF SETF OE SETF /RESETn SETF /PASSn SETF DIFFn SETF /INPUT CLOCKF SETF RESETn SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF INPUT CLOCKF SETF /INPUT CLOCKF SETF /INPUT CLOCKF TRACE_OFF