Title     5-Bit Down Counter
Pattern   DCount.pds
Revision  B
Author    Bill Karkula
Company   Monolithic Memories Inc., Sanat Clara, CA
Date      8/1/86
  
CHIP DN_COUNTER PAL20RA10
  
/PL D4 D3 D2 D1 D0 CK NC /LD /LR /RST GND
/OE R0 R1 R2 R3 R4 Q0 Q1 Q2 Q3 Q4 VCC
  
EQUATIONS
  
/Q4             := Q4                   ;Toggle if lower MSB
Q4.CLKF          = Q3                   ;becomes a one
Q4.SETF          = RST                  ;Rollover/master RST
Q4.RSTF          = /D4*LD               ;Load initial count
  
/Q3             := Q3                   ;Toggle when Q2
Q3.CLKF          = Q2                   ;Becomes a one
Q3.SETF          = RST                  ;Rollover/master RST
Q3.RSTF          = /D3*LD               ;Load initial count
  
/Q2             := Q2                   ;Toggle when Q1
Q2.CLKF          = Q1                   ;becomes a one
Q2.SETF          = RST                  ;Rollover/master RST
Q2.RSTF          = /D2*LD               ;Load initial count
  
/Q1             := Q1                   ;Toggle when Q0
Q1.CLKF          = Q0                   ;becomes a one
Q1.SETF          = RST                  ;Rollover/master RST
Q1.RSTF          = /D1*LD               ;Load initial count
  
/Q0             := Q0                   ;Toggle  LSB
Q0.CLKF          = CK                   ;External clock input
Q0.SETF          = RST                  ;Rollover/master RST
Q0.RSTF          = /D0*LD               ;Load initial count
  
/R4             := /D4                  ;Load rollover point
R4.CLKF          = LR                   ;if /LR is low
/R3             := /D3                  ;Load rollover bit 3
R3.CLKF          = LR                   ;if /LR is asserted
/R2             := /D2                  ;Load rollover bit 2
R2.CLKF          = LR                   ;if /LR is asserted
/R1             := /D1                  ;Load rollover bit 1
R1.CLKF          = LR                   ;if /LR is asserted
/R0             := /D0                  ;Load rollover bit 0
R0.CLKF          = LR                   ;if /LR is asserted
  
SIMULATION
  
TRACE_ON PL OE CK Q0 Q1 Q2 Q3 Q4
  
SETF /PL OE /RST /CK /LD /LR
  
SETF RST LR CK D4 D3 D2 D1 D0           ;Test SET function of registers
  
CHECK /Q0 /Q1 /Q2 /Q3 /Q4               ;Check for high on
                                        ;register outputs
SETF /RST                               ;Deassert SET funct
SETF /D0 /D1 /D2 /D3 /D4 LD             ;Test RESET funct.
CHECK Q0 Q1 Q2 Q3 Q4
SETF /OE /Q4 /Q3 /Q2 /Q1 Q0 /LD         ;Disable RESET, load
                                        ;registers w/ LLLLH,
                                        ;tristate registers
SETF  PL                                ;Load regs w/ data
                                        ;on output bus.
SETF OE /PL                             ;Disable PRELOAD &
                                        ;TRISTATE function.
FOR I:=1 TO 7 DO                        ;Initially load regs
 BEGIN                                  ;w/ LLLLH & clocked
  SETF CK                               ;7 times.
  SETF /CK                              ;Rollover at I=2
  IF I=2 THEN                           ;count goes LLLLL
   BEGIN                                ;to HHHHH.
    CHECK /Q4 /Q3 /Q2 /Q1 /Q0           ;Check rollover pt.
   END
  IF I=6 THEN
   BEGIN
    CHECK Q4 Q3 Q2 /Q1 /Q0
   END
  IF I=7 THEN
   BEGIN
    CHECK Q4 Q3 /Q2 Q1 Q0
   END
  END
TRACE_OFF