TITLE CRC6
PATTERN CRC 6 ERROR DETECTION PAL
REVISION 1.01
AUTHOR THERESA SHAFER
COMPANY MMI
DATE 9/10/86
 
CHIP CRC6 PAL20R6
 
CK DATA /CLR CHECK_BIT EOX NC NC NC NC NC NC GND
/OE NC ERROR R5 R4 R3 R2 R1 R0 CRC6 NC VCC
 
; THE CRC-6 PAL PERFORMS ERROR DETECTION ON A SERIAL DATA
; STREAM.  CRC-6 PAL SUPPORTS THE T1 Fe STANDARD FOR ERROR
; DETECTION. THE CRC RESULT CAN BE OUTPUTTED EITHER IN SERIAL
; OR IN PARALLEL.
; 
;  CRC-6 = X**6 + X + 1
; 
; INPUTS:   CK          EXTERNAL CLOCK
;           /OE         ACTIVE LOW OUTPUT ENABLE SIGNAL
;           /CLR        ACTIVE LOW CLEAR SIGNAL WHICH RESETS THE
;                        CRC
;           DATA        SERIAL DATA STREAM INPUT
;           CHECK_BIT   ACTIVE HIGH SELECT INPUT WHICH SWITCHES
;                        FROM SERIAL DATA STREAM TO CHECK BITS
;           EOX         ACTIVE HIGH SIGNAL WHICH INDICATES END OF
;                         EXTENDED  SUPERFRAME  AND  ENABLES  THE
;                         ERROR DETECTION FLAG
  
; OUTPUTS:  CRC6        CRC SERIAL OUTPUT
;           ERROR       ACTIVE HIGH OUTPUT FLAG WHICH INDICATES
;                        A TRANSMISSION ERROR
EQUATIONS
 
; CRC-6 PAL
 
/CRC6 = /R5 * CHECK_BIT
     + /DATA * /CHECK_BIT
 
/ERROR = EOX * /R5 * /R4 * /R3 * /R2 * /R1 * /R0
     + /EOX
 
/R5 := /DATA * /R5 * /R4
     + DATA * R5 * /R4
     + DATA * /R5 * R4 * /CHECK_BIT
     + /DATA * R5 * R4 * /CHECK_BIT
     + /R4 * CHECK_BIT
     + CLR
 
/R4 := /R3 + CLR
 
/R3 := /R2 + CLR
 
/R2 := /R1 + CLR

/R1 := /DATA * /R5 * /R0
     + DATA * R5 * /R0
     + DATA * /R5 * R0 * /CHECK_BIT
     + /DATA * R5 * R0 * /CHECK_BIT
     + /R0 * CHECK_BIT
     + CLR
 
/R0 := /DATA * /R5
     + DATA * R5 * /CHECK_BIT
     + /DATA * /R5 * /CHECK_BIT
     + /R5 * CHECK_BIT
     + CLR
 
; .........................................................
; .........................................................
 
 
SIMULATION
 
TRACE_ON CK /OE /CLR CHECK_BIT EOX DATA CRC6 ERROR
         R5 R4 R3 R2 R1 R0
 
SETF OE               ; ENABLE OUTPUT
     CLR              ; CLEAR SHIFT REGISTER
CLOCKF CK
 
; INITIALIZE
SETF DATA
     /CHECK_BIT
     /EOX
     /CLR
CLOCKF CK
 
; FIND PERIOD
FOR J:= 0 TO 38 DO
     BEGIN
     CLOCKF CK
     END
 
; CALCULATE CRC-6 FOR INPUT STREAM 1101.1000.0101.0011.1001
SETF CLR            ; CLEAR SHIFT REGISTER
CLOCKF CK
SETF /CLR           ; BEGIN CRC CALCULATION
 
SETF DATA
CLOCKF CK
SETF DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
 
SETF DATA

CLOCKF CK
SETF /DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
 
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
 
SETF /DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
SETF DATA
CLOCKF CK
 
SETF DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
 
;  CHECK ERROR DETECTION
SETF EOX                 ;  CHECK ERROR FLAG
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
SETF /DATA
CLOCKF CK
 
; READ CRC RESULT
SETF /EOX
SETF /DATA
CLOCKF CK
SETF DATA

CLOCKF CK
SETF CHECK_BIT
     DATA
FOR J:= 0 TO 6 DO
     BEGIN
     CLOCKF CK
     END
 
  
  
TRACE_OFF