TITLE		LIFO RAM CONTROLLER.
PATTERN		01A.
REVISION	01.
AUTHOR		CHRIS JAY.
COMPANY		MMI SANTA CLARA, CA.
DATE		23 SEPTEMBER 1986.
;
;THE  ESSENTIAL  CONTROL  SIGNALS  FOR  CONTROLLING
;A  CMOS  STATIC  RAM  AS  A  HARDWARE  STACK  OR
;LAST  IN  FIRST  OUT  MEMORY  ARE  GENERATED  BY
;THE  PAL32VX10.  WHEN  A  HIGH  PUSH  INPUT  IS
;RECIEVED  THE  /WR  OUTPUT  GOES  FROM  INACTIVE
;HIGH  TO  ACTIVE  LOW  FOLLOWED  BY  AN  ACTIVE
;LOW  CHIP  SELECT, /CS.  PRIOR  TO  THE  ACTIVE  WRITE
;CYCLE  THE  ADDRESS  COUNT  IS  INCREMENTED.  SO
;A  PUSH  CYCLE  WILL CONSIST  OF  ADDRESS  INCREMENT
;FOLLOWED  BY  A  WRITE.  A  POP  CYCLE  WILL
;DECREMENT  THE  ADDRESS  COUNTER  AFTER  AN  ACTIVE
;READ.  THE  /CS  OUTPUT  WILL  GO  LOW  WITH  /WR
;INACTIVE  HIGH.  AS  A  'STAND  ALONE'  DESIGN  THIS
;PAL  CAN  CONTROL  THE  DATA  FLOW  INTO  A  STACK
;128  LOCATIONS  DEEP.  FOR  THE  CONTROL  OF  LARGER
;RAM  ARRAYS  IT  IS  POSSIBLE  TO  CASCADE  TWO  PAL
;DEVICES.  THE  MOST  SIGNIFICANT  ADDRESS  BIT  WILL
;BECOME  A  CARRY  OUT  SIGNAL  FOR  A  SECOND  PAL
;DEVICE  THE  CARRY  SIGNAL  PROPAGATES
;AN  UP/DOWN  COUNT  ENABLE  TO  THE  SECOND  PAL
;ALLOWING  ADDRESSING  OF  8K X 8 DEEP  STATIC RAMS.
;THESE  MAY  BE  EXPANDED  IN  WIDTH,  AND  CONTROLLED
;BY  THE  SAME  PAL  DEVICES TO  CREATE  STACK
;MEMORY  ARRAYS  OF  16  AND  24  AND  32  BITS
;WIDE.
;
CHIP LIFOCONT PAL32VX10
;
;PIN	1	2	3	4	5	6
	CLK 	/RST 	PUSH	POP	NC	NC 

;PIN	7	8	9	10	11	12
	NC	NC 	NC 	NC 	NC 	GND

;PIN	13	14	15	16	17	18
	NC 	/WR 	/CSX 	XO 	/Q6 	/Q5 

;PIN	19	20	21	22	23	23
	/Q4	/Q3	/Q2	/Q1	/Q0	VCC

GLOBAL  BWR BCSX X Q6B Q5B Q4B Q3B Q2B Q1B Q0B

STRING CKUEN '/BWR*/BCSX*/X*PUSH'	;CLOCK UP ENABLE
STRING CKDEN '/BCSX*X*POP'		;CLOCK DOWN ENABLE

EQUATIONS

GLOBAL.SETF = RST			;ASYNCHRONOUS
					;RESET.
/Q0B 	 :=   /Q0B			;LEAST  SIGNIFICANT
	 :+:  CKUEN			;BIT  OF  THE
	  +   CKDEN			;LIFO  ADDRESS
/Q0	  =   /Q0B			;COUNTER
/Q0.CMBF  =   GND			;ENABLE  REGISTER
					;TO  A0  OF  RAM
/Q1B 	 :=  /Q1B			;HOLD  COUNT
    	 :+: /Q0B*CKDEN			;ENABLE  DOWN COUNT
	  +  Q0B*CKUEN			;ENABLE  UP  COUNT
/Q1	  =  /Q1B			;ENABLE  REGISTER
/Q1.CMBF  =  GND			;TO  A1  OF  RAM
					;
/Q2B 	 :=  /Q2B			;HOLD
     	 :+: /Q0B*/Q1B*CKDEN		;ENABLE  DOWN  COUNT
     	  +  Q0B*Q1B*CKUEN		;ENABLE  UP  COUNT
/Q2	  =  /Q2B			;ENABLE  REGISTER
/Q2.CMBF  =  GND			;TO  A2  OF  RAM
					;
/Q3B 	 :=  /Q3B			;HOLD
     	 :+: /Q0B*/Q1B*/Q2B*CKDEN	;ENABLE  DOWN  COUNT
     	 +   Q0B*Q1B*Q2B*CKUEN		;ENABLE  UP  COUNT
/Q3	  =  /Q3B			;ENABLE  REGISTER
/Q3.CMBF  =  GND			;TO  A3  OF  RAM
					;
/Q4B 	 :=  /Q4B			;HOLD
     	 :+: /Q0B*/Q1B*/Q2B*/Q3B*CKDEN	;ENABLE  DOWN  COUNT
    	  +  Q0B*Q1B*Q2B*Q3B*CKUEN	;ENABLE  UP  COUNT
/Q4	  =  /Q4B			;ENABLE  REGISTER
/Q4.CMBF  =  GND			;TO  A4  OF  RAM
					;
/Q5B	 :=  /Q5B			;HOLD
	 :+: /Q0B*/Q1B*/Q2B*/Q3B*/Q4B	;
	  *CKDEN			;ENABLE  DOWN  COUNT
	  +  Q0B*Q1B*Q2B*Q3B*Q4B*CKUEN	;ENABLE  UP  COUNT
/Q5	 :=  /Q5B			;ENABLE  REGISTER
/Q5.CMBF  =  GND			;TO  A5  OF  RAM
					;
BCSX	 :=  /BCSX*BWR*/X*PUSH		;CHIP  SELECT  TO
	  +  POP*/X*/BCSX*/BWR		;RAM  ACTIVE  LOW
/CSX	  =  /BCSX			;FOR  READ  AND
/CSX.CMBF =  GND			;WRITE
					;
BWR	 :=  BWR*/X*PUSH		;RD/WR  CONTROL TO
	  +  /BCSX*/X*PUSH		;RAM,  ACTIVE  LOW
	  +  /BCSX*X*POP		;TO  WRITE,  HIGH
	  +  BWR*POP			;TO  READ
/WR	  =  /BWR			;
/WR.CMBF  =  GND			;
					;
X	 :=  BWR*BCSX*/X		;CONTROL  SIGNAL
	  +  X*PUSH*/BCSX		;X,  TO  ENABLE
	  +  BCSX*/X			;SEQUENCING  OF
XO	 :=  X				;CS,WR  AND  THE
XO.CMBF   =  GND			;CONTROLLING  OF
					;ADDRESS  LINES
/Q6B	 :=  /Q6B			;HOLD 
         :+:  Q0B*Q1B*Q2B*Q3B*Q4B*Q5B	;
	  *CKUEN			;ENABLE UP COUNT
	  +  /Q0B*/Q1B*/Q2B*/Q3B*/Q4B	;
	  */Q5B*CKDEN;ENABLE DOWN COUNT	;
/Q6	  =  /Q6B			;
/Q6.CMBF  = GND				;
					;
SIMULATION

TRACE_ON  /WR /CSX XO CLK PUSH POP 	;
	  Q0 Q1 Q2 Q3 Q4 Q5 Q6		;
SETF RST /PUSH /POP /CLK		;SET  INITIAL  CONDITIONS
SETF /RST				;REMOVE  ACTIVE  RESET
CLOCKF CLK				;
FOR K := 1 TO 3 DO			;GENERATE  THREE  PUSH
BEGIN					;CYCLES  INTO  THE  RAM
SETF PUSH				;SET  PUSH  INSTRUCTION
FOR I := 1 TO 5 DO			;HIGH
BEGIN CLOCKF CLK			;CLOCK  FOR  FIVE  CYCLES
END					;ONE  WRITE  CYCLE  IS
SETF /PUSH				;GENERATED.
FOR J := 1 TO 3 DO			;REMOVE  PUSH  INSTRUCTION
BEGIN CLOCKF CLK			;
END					;
END					;
SETF /POP				;SET  POP  INACTIVE
CLOCKF CLK				;GENERATE  FOUR  POP
FOR L := 1 TO 4 DO			;CYCLES
BEGIN					;GENERATE  AN  ACTIVE
SETF POP				;POP,  CLOCK  ONE  POP
FOR M := 1 TO 5 DO			;CYCLE  OVER  FIVE
BEGIN CLOCKF CLK			;CLOCKS.
END					;
SETF /POP				;SET  POP  INACTVE
FOR N := 1 TO 3 DO			;OVER  THREE  CLOCK
BEGIN CLOCKF CLK			;CYCLES.
END					;
END 					;
TRACE_OFF