TITLE PAL_B
PATTERN B8ZS ENCODER PAL B
REVISION 1.03
AUTHOR THERESA SHAFER
COMPANY MMI
DATE 10/3/86

CHIP PAL_B PAL16R6

NRZ_CK /RST NRZ_IN C2 C1 C0  NRZ_DELAY NC NC GND
/OE NC CS NPO PPO Q0 Q1 Q2 NC VCC

; 
; INPUTS:   NRZ_CK      EXTERNAL CLOCK
;           /OE         ACTIVE LOW OUTPUT ENABLE SIGNAL
;           /RST        ACTIVE LOW MASTER RESET SIGNAL
;            NRZ_DELAY  SERIAL NRZ DATA STREAM WHICH WAS DELAYED
;                        BY PAL A
;           C2 - C0     COUNTER OUTPUTS
;	    NRZ_IN 	NRZ DATA STREAM INDICATES AN
;			 8-BIT STREAM OF ALL ZERO WHEN
;			 COUNTER OUTPUTS ARE 111 AND NRZ_IN = 0
	 
; OUTPUTS:  CS           CURRENT STATE
;           PPO          POSITIVE B8ZS CODE
;           NPO          NEGATIVE B8ZS CODE
;           Q2 - Q0      B8ZS SEQUENCE STATE MACHINE STATES
  
EQUATIONS

; B8ZS ENCODING STATE MACHINE EQUATIONS
; STATE VARIATES = [CS,PPO,NPO]
; WITH THE FOLLOWING STATE ASSIGNMENT
;   P_ZERO   = [0,0,0]
;   NEGATIVE = [1,0,1]
;   N_ZERO   = [1,0,0]
;   POSITIVE = [0,1,0]
  
/CS := /CS * /NPO * /Q1 * Q0
     + CS * /PPO * Q1 * /Q0
     + /CS * /NPO * /NRZ_DELAY * /Q1
     + /CS * /NPO * Q2 * /Q1
     + CS * NRZ_DELAY * /PPO * /Q2 * /Q0
     + RST
  
/PPO := CS * /PPO * Q0 * /Q1
     + /CS * /NPO * /Q0
     + CS * /NRZ_DELAY * /PPO * /Q1
     + CS * /PPO * Q2 * /Q1
     + RST
  
/NPO := /CS * /NPO * /Q1 * Q0
     + /CS * /NPO * /NRZ_DELAY * /Q1
     + /CS * /NPO * Q2 * /Q1
     + CS * /PPO * /Q0
     + RST
  

; B8ZS SEQUENCE STATE MACHINE EQUATIONS
; STATE VARIATES [Q2,Q1,Q0]
; WITH THE FOLLOWING STATE ASSIGNMENTS
;    A = [0,0,0]
;    B = [0,0,1]
;    C = [0,1,0]
;    D = [1,0,0]
;    E = [1,0,1]
;    F = [1,1,0]
  
/Q2 := /Q2 * /Q1
     + Q2 * Q1
     + RST
  
/Q1 :=  /Q0
     + Q2 * Q1
     + RST
  
/Q0 := /Q2 * /Q1 * /Q0 * /C2
     + /Q2 * /Q1 * /Q0 * /C1
     + /Q2 * /Q1 * /Q0 * /C0
     + /Q2 * /Q1 * /Q0 * NRZ_IN
     + Q0
     + Q1
     + RST
  
; .........................................................
; .........................................................
  
SIMULATION

TRACE_ON NRZ_CK /OE /RST NRZ_DELAY NRZ_IN C2 C1 C0
         CS PPO NPO Q2 Q1 Q0
  
SETF OE               ; ENABLE OUTPUT
     RST              ; RESET
CLOCKF NRZ_CK

; INITIALIZE
SETF NRZ_DELAY
     /RST
     NRZ_IN /C2 /C1 /C0
CLOCKF NRZ_CK

; HOLD AND DO NONE THING
SETF /NRZ_DELAY
     /NRZ_IN /C2 /C1 /C0
CLOCKF NRZ_CK
SETF NRZ_DELAY
     /C2 /C1 C0
CLOCKF NRZ_CK
SETF NRZ_DELAY
     /C2 C1 /C0
CLOCKF NRZ_CK
SETF NRZ_DELAY
     /C2 C1 C0

CLOCKF NRZ_CK
SETF /NRZ_DELAY
     C2 /C1 /C0
CLOCKF NRZ_CK
SETF /NRZ_DELAY
     C2 /C1 C0
CLOCKF NRZ_CK
SETF /NRZ_DELAY
     C2 C1 /C0
CLOCKF NRZ_CK
SETF /NRZ_DELAY
     C2 C1 /C0
CLOCKF NRZ_CK
SETF C2 C1 C0
CLOCKF NRZ_CK
SETF /C2 /C1 /C0
CLOCKF NRZ_CK
FOR I:=0 TO 5 DO
     BEGIN
     CLOCKF NRZ_CK
     END
  
SETF /C2 /C1 /C0
     NRZ_DELAY
CLOCKF NRZ_CK
SETF /NRZ_DELAY
CLOCKF NRZ_CK
SETF /NRZ_DELAY
CLOCKF NRZ_CK
SETF /NRZ_DELAY
CLOCKF NRZ_CK
SETF C2 C1 C0
     /NRZ_DELAY
CLOCKF NRZ_CK
SETF /C2 /C1 /C0
     /NRZ_DELAY
CLOCKF NRZ_CK
FOR I:=0 TO 5 DO
     BEGIN
     CLOCKF NRZ_CK
     END
  
SETF /NRZ_DELAY
     NRZ_IN C2 C1 /C0
CLOCKF NRZ_CK
SETF C2 C1 C0
CLOCKF NRZ_CK
SETF /C2 /C1 /C0
CLOCKF NRZ_CK
FOR I:=0 TO 5 DO
     BEGIN
     CLOCKF NRZ_CK
     END
  
TRACE_OFF