TITLE PAL_A
PATTERN B8ZS ENCODER PAL A
REVISION 1.01
AUTHOR THERESA SHAFER
COMPANY MMI
DATE 10/1/86
 
CHIP PAL_A PAL16R8
 
NRZ_CK /RST NRZ_IN NC NC NC NC NC NC GND
/OE C0 C1 C2 NRZ_DELAY R3 R2 R1 R0 VCC
 
; 
; INPUTS:   NRZ_CK    EXTERNAL CLOCK
;           /OE         ACTIVE LOW OUTPUT ENABLE SIGNAL
;           /RST        ACTIVE LOW MASTER RESET SIGNAL
;            NRZ_IN   SERIAL NRZ DATA STREAM WHICH IS ENCODED
;                        AND TRANSMITTED
  
; OUTPUTS:  NRZ_DELAY   DELAY NRZ DATA WHICH IS INPUT FOR PAL B
;           C2 - C0     COUNTER OUTPUTS (111) INDICATES
;                        AN 8-BIT STREAM OF ALL ZEROS
 
EQUATIONS
 
; 3-BIT COUNTER WITH SYNCHRONOUS RESET AND ENABLE
 
/C2 := C2 * C1 * C0
     + /C2 * /C1
     + /C2 * /C0
     + RST               ; MASTER RESET
     + NRZ_IN            ; CLEAR COUNTER WHEN NRZ_IN = 1
  
 
/C1 := /C1 * /C0
     + C1 * C0
     + RST               ; MASTER RESET
     + NRZ_IN            ; CLEAR COUNTER WHEN NRZ_IN = 1
 
/C0 := C0
     + RST               ; MASTER RESET
     + NRZ_IN            ; CLEAR COUNTER WHEN NRZ_IN = 1
 
; 5-STAGE PIPELINE DELAY
 
/NRZ_DELAY := /R3 + RST
 
/R3 := /R2 + RST
 
/R2 := /R1 + RST
 
/R1 := /R0 + RST
 
/R0 := /NRZ_IN + RST
  

 
; .........................................................
; .........................................................
 
SIMULATION
 
TRACE_ON NRZ_CK /OE /RST NRZ_IN
         C2 C1 C0 NRZ_DELAY R3 R2 R1 R0
 
SETF OE               ; ENABLE OUTPUT
     RST              ; RESET
CLOCKF NRZ_CK
 
; INITIALIZE
SETF NRZ_IN
     /RST
CLOCKF NRZ_CK
 
; PERFORM ZERO SUBSTITUTION
SETF /NRZ_IN
FOR J:= 0 TO 8 DO
     BEGIN
     CLOCKF NRZ_CK
     END
 
SETF NRZ_IN
CLOCKF NRZ_CK
SETF NRZ_IN
CLOCKF NRZ_CK
SETF /NRZ_IN
CLOCKF NRZ_CK
SETF NRZ_IN
CLOCKF NRZ_CK
 
SETF /NRZ_IN
FOR J:= 0 TO 6 DO
     BEGIN
     CLOCKF NRZ_CK
     END
 
SETF NRZ_IN
CLOCKF NRZ_CK
 
TRACE_OFF