#ifndef	PIMAX

/* Hardware-dependent routines for the VE3IFB interface card for the PC
 */

#include "global.h"
#define PIMAX	3			/* 3 cards max */
#define AX_MTU	512
#define INTMASK 0x21		/* Intel 8259 interrupt controller mask */

struct PITAB {
	INTERRUPT (*oldvec) __ARGS((void));	/* Original interrupt vector contents */
	int16 addr;							/* Base I/O address */
	unsigned vec;						/* Vector */
	long ints;							/* Interrupt count */
};
extern struct PITAB Pi[];

/* Register offset info, specific to the PI
 * E.g., to read the data port on channel A, use
 *	inportb(pichan[dev].base + CHANA + DATA)
 */
#define CHANB		0	/* Base of channel B regs */
#define CHANA		2	/* Base of channel A regs */

/* 8530 ports on each channel */
#define CTL		0
#define DATA	1

#define DMAEN	0x4 /* Offset off DMA Enable register */

/* Timer chip offsets */
#define TMR0	0x8 /* Offset of timer 0 register */
#define TMR1	0x9 /* Offset of timer 1 register */
#define TMR2	0xA /* Offset of timer 2 register */
#define TMRCMD	0xB /* Offset of timer command register */

/* Timer chip equates */
#define SC0		0x00 /* Select counter 0 */
#define SC1		0x40 /* Select counter 1 */
#define SC2		0x80 /* Select counter 2 */
#define CLATCH	0x00 /* Counter latching operation */
#define MSB		0x20 /* Read/load MSB only */
#define LSB		0x10 /* Read/load LSB only */
#define LSB_MSB	0x30 /* Read/load LSB, then MSB */
#define MODE0	0x00 /* Interrupt on terminal count */
#define MODE1	0x02 /* Programmable one shot */
#define MODE2	0x04 /* Rate generator */
#define MODE3	0x06 /* Square wave rate generator */
#define MODE4	0x08 /* Software triggered strobe */
#define MODE5	0x0a /* Hardware triggered strobe */
#define BCD		0x01 /* BCD counter */

/* DMA controller registers */
#define DMA_STAT		8	/* DMA controller status register		*/
#define DMA_MASK        10	/* DMA controller mask register			*/
#define DMA_MODE        11	/* DMA controller mode register			*/
#define DMA_RESETFF		12	/* DMA controller first/last flip flop	*/
/* DMA data */
#define DMA_DISABLE (0x04)	/* Disable channel n */
#define DMA_ENABLE	(0x00)	/* Enable channel n */
/* Single transfers, incr. address, auto init, writes, ch. n */
#define DMA_RX_MODE	(0x54)
/* Single transfers, incr. address, no auto init, reads, ch. n */
#define DMA_TX_MODE (0x48)

struct pichan {
	long rxints;		/* Receiver interrupts */
	long txints;		/* Transmitter interrupts */
	long exints;		/* External/status interrupts */

	int enqueued;		/* Packets enqueued for transmit */
	int rxframes;		/* Packets received */
	int crcerr;			/* CRC Errors */
	int rovers;			/* Receiver Overruns */
	int tunders;		/* Tranmitter underruns */

	struct mbuf *rcvbuf;/* Buffer for current rx packet */
	int16 bufsiz;		/* Size of rcvbuf */
	char *rcp;			/* Pointer into rcvbuf */

	struct mbuf *sndq;	/* Packets awaiting transmission */
	int16 sndcnt;		/* Number of packets on sndq */
	struct mbuf *sndbuf;/* Current buffer being transmitted */
	char *txdmabuf;		/* Transmit DMA buffer */
	char tstate;		/* Transmitter state */
#define IDLE	0		/* Transmitter off, no data pending */
#define ACTIVE	1		/* Transmitter on, sending data */
#define UNDERRUN 2		/* Transmitter on, flushing CRC */
#define FLAGOUT 3		/* CRC sent - attempt to start next frame */
#define DEFER 4 		/* Receive Active - DEFER Transmit */
#define ST_TXDELAY 5	/* Sending leading flags */
#define CRCOUT 6
	char rstate;		/* Set when !DCD goes to 0 (TRUE) */
/* Normal state is ACTIVE if Receive enabled */
#define RXERROR 2		/* Error -- Aborting current Frame */
#define RXABORT 3		/* ABORT sequence detected */
#define TOOBIG 4		/* too large a frame to store */
	int16 dev;			/* Device number */
	int16 base;			/* Base of I/O registers */
	int16 cardbase;		/* Base address of card */
	int16 stata;		/* address of Channel A status regs */
	int16 statb;		/* address of Channel B status regs */
	int16 speed;		/* Line speed, bps */
#define TXDELAY 0		/* Transmit Delay 10 ms/cnt */
#define PERSIST 1		/* Persistence (0-255) as a % */
#define SLOTIME 2		/* Delay to wait on persistence hit */
#define SQUELDELAY 3	/* Delay after XMTR OFF for squelch tail */
	char params[4]; 	/* Channel control parameters */
	struct iface *iface;/* Associated interface */
	char dmachan;		/* DMA channel for this port */
	unsigned char page_addr; /* address of dma page register */
	unsigned int dma_dest;	/* address of dma dest reg */
	unsigned int dma_wcr; 	/* address of dma word count reg */

};
extern struct pichan Pichan[];

/* Interrupt vector handlers (assembler) */
int pcint();

#define OFF	0
#define ON	1

/* 8530 clock speed */
#define XTAL	((long)3686400 /2)	 /* 32X clock constant */

/* In pi.c: */
void piint __ARGS((int dev));

/* In pivec.asm: */
INTERRUPT pi0vec __ARGS((void));
INTERRUPT pi1vec __ARGS((void));
INTERRUPT pi2vec __ARGS((void));

#endif	/* PIMAX */