/*
 * 32 bit int micro RTX bindings when __NO_INLINE__
 *
 *	++jrb	bammi@dsrgsun.ces.cwru.edu
 */

#ifndef __MSHORT__

long _trap5_w(short n)
{
    long retvalue;

    __asm__ volatile
	("
		movw    %1,sp@-;
		trap    #5;
		addqw   #2,sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n)				/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wl(short n, long l1)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		addqw   #6,sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1)			/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wlw(short n, long l1, short w1)
{
    long retvalue;

    __asm__ volatile
	("
 		movw	%3,sp@-;
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		addqw   #8,sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1), "r"(w1)		/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wlwl(short n, long l1, short w1, long l2)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%4,sp@-;
 		movw	%3,sp@-;
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		lea     sp@(12),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1), "r"(w1), "r"(l2)	/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wll(short n, long l1, long l2)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%3,sp@-;
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		lea     sp@(10),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1), "r"(l2)		/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wlll(short n, long l1, long l2, long l3)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%4,sp@-;
 		movl	%3,sp@-;
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		lea     sp@(14),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1), "r"(l2), "r"(l3)	/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wwl(short n, short w1, long l1)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%3,sp@-;
 		movw	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		addqw   #8,sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(w1), "r"(l1)		/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wllwl(short n, long l1, long l2, short w1, long l3)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%4,sp@-;
 		movw	%3,sp@-;
		movl    %2,sp@-;
 		movl	%1,sp@-;
		movw    %0,sp@-"
	 : 						/* outputs */
	 : "r"(n), "r"(l1), "r"(l2), "r"(w1), "r"(l3)	/* inputs  */
	 );
    __asm__ volatile
	("
		trap    #5;
		lea     sp@(16),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : 					/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wlwwlwll(short n, long l1, short w1, short w2, long l2,
		     short w3, long l3, long l4)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%4,sp@-;
 		movl	%3,sp@-;
		movw    %2,sp@-;
 		movl	%1,sp@-;
		movw    %0,sp@-"
	 : 						/* outputs */
	 : "r"(w2), "r"(l2), "r"(w3), "r"(l3), "r"(l4)	/* inputs  */
	 );
    __asm__ volatile
	("
 		movw	%3,sp@-;
 		movl	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		lea     sp@(24),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(l1), "r"(w1)		/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

long _trap5_wwllllll(short n, short w1, long l1, long l2, long l3,
		     long l4, long l5, long l6)
{
    long retvalue;

    __asm__ volatile
	("
 		movl	%4,sp@-;
 		movl	%3,sp@-;
		movl    %2,sp@-;
 		movl	%1,sp@-;
		movl    %0,sp@-"
	 : 						/* outputs */
	 : "r"(l2), "r"(l3), "r"(l4), "r"(l5), "r"(l6)	/* inputs  */
	 );
    __asm__ volatile
	("
 		movl	%3,sp@-;
 		movw	%2,sp@-;
		movw    %1,sp@-;
		trap    #5;
		lea     sp@(28),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 : "r"(n), "r"(w1), "r"(l1)		/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}

/*
 * additional gemdos bindings (not in osbind.h)
 */
long trap_1_wwwll(short n, short w1, short w2, long l1, long l2)
{
    long retvalue;

    __asm__ volatile
	("
		movl    %4,sp@-;
		movl    %3,sp@-;
		movw    %2,sp@-;
		movw    %1,sp@-;
		movw    %0,sp@- "
	 :					 /* outputs */
	 : "r"(n), "r"(w1), "r"(w2), "r"(l1), "r"(l2) /* inputs  */
	 );
    /* no more than 5 operand allowed in asm() -- therefore the split */

    __asm__ volatile
	("
		trap    #1;
		lea    sp@(14),sp;
		movl    d0,%0"
	 : "=g"(retvalue)			/* outputs */
	 :					/* inputs  */
	 : "d0", "d1", "d2", "a0", "a1", "a2"    /* clobbered regs */
	 );
    return retvalue;
}
#endif /* !__MSHORT__ */