






            

            

            

            

            

            

                                    L O G S I M

                                          

                             a Logic Simulation program
                                    Version 2.1

                                          

                                          

                                          

                                          

                      Copyright (C), 1986 by Scott Romanowski
                                All rights reserved
                         Commercial Duplication Prohibited
                                          
                                          
                                          
                                          
                                          
                                          
                                          
                                 November 20, 1986
























                                                                        I


                                      Contents
            
            1. Introduction........................................... 1
              1.1 Duplication and Use Policy.......................... 1
            2. Using LOGSIM........................................... 2
              2.1 Equation Syntax and Node Numbers.................... 3
              2.2 Tri-State and Open Collector Outputs................ 3
              2.3 Initial Conditions.................................. 4
            3. Describing the Circuit................................. 4
              3.1 Gates............................................... 4
                3.1.1 AND Gate........................................ 5
                3.1.2 BUFFER Gate..................................... 5
                3.1.3 DELAY Gate...................................... 5
                3.1.4 DELAYH Gate..................................... 6
                3.1.5 DELAYL Gate..................................... 6
                3.1.6 NAND Gate....................................... 6
                3.1.7 NOR Gate........................................ 6
                3.1.8 NOT Gate........................................ 7
                3.1.9 OR Gate......................................... 7
                3.1.10 XNOR Gate...................................... 7
                3.1.11 XOR Gate....................................... 7
              3.2 Chips............................................... 8
                3.2.1 D Chip Descriptor............................... 8
                3.2.2 JK Chip Descriptor.............................. 8
                3.2.3 7476 Chip Descriptor............................ 9
                3.2.4 74112 Chip Descriptor........................... 9
                3.2.5 74123 Chip Descriptor........................... 9
                3.2.6 74126 Chip Descriptor.......................... 10
                3.2.7 74192 Chip Descriptor.......................... 10
                3.2.8 74193 Chip Descriptor.......................... 10
                3.2.9 74253 Chip Descriptor.......................... 11
              3.3 Clocks............................................. 11
              3.4 Data Sources....................................... 11
            4. Simulating the Circuit................................ 12
              4.1 Simulation Time.................................... 12
              4.2 Rise Time Calculations............................. 12
              4.3 Gate Delays........................................ 13
              4.4 Initial Conditions................................. 13
              4.5 Output Modes....................................... 14
                4.5.1 Display........................................ 14
                4.5.2 File........................................... 14
                4.5.3 Print.......................................... 15
                4.5.4 Fprint......................................... 16
              4.6 Time Units per Screen.............................. 17
              4.7 Monitoring nodes................................... 17
              4.8 Fanout Lists....................................... 17
            5. Chip Descriptions..................................... 17
              5.1 Making New Chips................................... 18
                5.1.1 Pins, Delay, Mode and Output Pins.............. 18
                5.1.2 Chip Modes..................................... 19
                5.1.3 Output Equations............................... 19
              5.2 Sample Chip Descriptions........................... 20
              5.3 Simulating ROMS.................................... 20
              5.4 Simulating RAMS.................................... 21



                                       LOGSIM





                                                                        II


              5.5 Simulating PALs and PLAs........................... 21
            























































                                       LOGSIM





                                                                        1



            1. Introduction


                 LOGSIM is  a digital  logic simulation  program.  It is
            very general and infinitely expandable.  Users create a file
            describing their circuit and select options to configure the
            simulation.

                 All times  in the circuit are measured in "time units".
            A time  unit is  any amount of time, determined by the user.
            If the  user wants to use 10 nanoseconds per time unit, then
            a 100 nanosecond delay would be 10 time units.

                 Logic values  are simply  represented as  high and  low
            states, the  actual voltage levels are immaterial to LOGSIM.
            Tri-state and open collector outputs are handled specially--
            see the section describing them below.

                 LOGSIM requires  DOS 2.1  or higher and one disk drive.
            To use  the PRINT  option (graphics  timing diagram  on  the
            printer), the  graphics screen  dump program included in DOS
            is  required.     Using   PC-DOS,  this  program  is  called
            GRAPHICS.COM, using  MS-DOS, this  program  is  one  of  the
            PSCxxxx.COM programs.  See your DOS manual for more informa-
            tion.

                 This manual  is written for people who have some famil-
            iarity with  DOS (somewhere  between neophyte  and  wizard).
            You must  be able to edit files to use LOGSIM.  Knowledge of
            the print  screen command,  file  and  path  names,  default
            drive, default  directory, and batch files will help, but is
            not required.   It  goes without  saying, but  you must know
            about digital  logic before  understanding what this program
            does.

              1.1 Duplication and Use Policy


                 LOGSIM is  distributed as  shareware.   You can make as
            many copies  as you  desire, and give away as many copies as
            desired.   Users may  not charge  others for  copies of this
            program without  the express  written permission  of the au-
            thor.  If you must charge for the disk(s) when you give away
            a copy,  you may  charge no more than $1.00 (one dollar) per
            disk.

                 If you  distribute this  program, you must include this
            policy with  the copy.   You  may not include any portion of
            this program,  modified or not, in any other program without
            the written permission of the author.

                 If you are pleased with this program, the author humbly
            requests that  you send  $20 to  the author.   Shareware  is



                                       LOGSIM





                                                                        2


            based on  the belief  that people will gladly pay for a good
            product, yet  should not  be required to pay for a bad prod-
            uct.   Shareware lets  people experiment  with programs, and
            form their own opinion of the product.

                 If you choose not to support the author, there is noth-
            ing to  stop you from continuing to use LOGSIM.  If you sup-
            port the  author, good  for you!   You  have made the author
            very happy.

                 The author can be reached at:
                      Scott Romanowski
                      5 Sherburn Place
                      Wilmington, MA 01887

                 In addition, improvements to LOGSIM are planned.  These
            improvements will  speed simulation,  allow larger circuits,
            allow easy  implementation of  RAM memories,  and  add  more
            standard chips.   If this program generates a good response,
            the author will surely distribute the updates.  On the other
            hand, a discouraged author probably won't.

            2. Using LOGSIM


                 In order to have LOGSIM simulate your circuit, you must
            create a  circuit descriptor  file describing  your circuit.
            To use  LOGSIM, at  the DOS  prompt, type  "LOGSIM".  LOGSIM
            will reply with "Circuit Descriptor file", to which you type
            the name  of the  circuit descriptor  file.  Optionally, you
            can include  the name  of the circuit descriptor file on the
            command line, by typing "LOGSIM filename" (where filename is
            the name of the circuit descriptor file).

                 A circuit  descriptor file  consists of  two parts: the
            circuit itself,  and a  list of options for LOGSIM.  The two
            parts are  separated by an END statement--simply a line with
            the word END.

                 A sample circuit descriptor is shown below:

                           JK H 14 1 H 2 13 3
                           JK H 15 1 H 2 14 4
                           JK H 5 1 H 2 15 16
                           AND 5 3 4
                           CLOCK 1 0000111
                           DATA 2 01
                           END
                           TIME 60
                           MONITOR 13 14 15
                           PRINT

                 The first  6 lines describe the circuit (in this case a
            simple 0-1-2-4  counter), the 7th line is the end statement,



                                       LOGSIM





                                                                        3


            and lines  8 through  10 are the options.  LOGSIM recognizes
            both upper  and lower  case letters,  and both can be freely
            mixed in your input.

                 When LOGSIM  is reading  your circuit  description,  it
            displays "Reading element ..." messages to inform you of its
            progress, and  to aid  in debugging  if there is an error in
            your circuit  description.  After LOGSIM is finished reading
            your circuit  descriptor, LOGSIM  prints "Circuit descriptor
            read in" and starts simulating your circuit.  There may be a
            few second  pause while  LOGSIM determines the initial state
            of the circuit.

              2.1 Equation Syntax and Node Numbers


                 Logical expressions  are only  used in  coding chip de-
            scriptors.  In that case and in this manual, LOGSIM uses the
            following symbols when representing logic equations:

                 ~ NOT     & AND     + OR      * XOR

                 These are  listed in order of precedence, except OR and
            XOR are the same precedence.  Expressions are evaluated from
            left to  right.   Parentheses (parentheses only, no brackets
            [] or braces {} ) can be used to group expressions and over-
            ride precedence.   This  precedence scheme can be best shown
            by some examples:

                 A & B + C = C + A & B = (A & B) + C
                 A + B * C = (A + B) * C
                 A * B + C = (A * B) + C
                 ~A & B & ~C = ( (~A) & B) & (~C)
                 ~(A + B) & ~C + D = ( ( ~(A + B) ) & (~C) ) + D

                 All nodes  in LOGSIM  are numbered.  Any integer from 0
            to 1,000  can be  used.   In addition, there are two special
            nodes: H  (a constant  logic high)  and L  (a constant logic
            low), which can be used chip input nodes.  Example: JK h 2 3
            4 5  6 7  is a JK flip flop with ~PRESET tied to logic high.
            Using the  nodes H or L in a gate (ex.: AND 4 H 3) is WRONG!
            and will cause errors!

                 There can  be up  to one  thousand nodes  in a  circuit
            descriptor.

              2.2 Tri-State and Open Collector Outputs


                 In LOGSIM, all outputs are capable of being wired-ANDed
            together (like open-collector outputs).  If you connect sev-
            eral outputs together, the state at that node will be a
            logic high if and only if all the outputs on that node are




                                       LOGSIM





                                                                        4


            logic highs.  If any output to that node is a logic low, the
            node will be a logic low.

                 Tri-state devices  are implemented by having the output
            of the  device go  high in  the high-Z  state.  For example,
            consider a  tri-state  inverter  with  the  following  truth
            table:

                           A  B    C (Output)
                           L  X    Z (high impedance)
                           H  L    H
                           H  H    L

                 In LOGSIM,  this can  be represented  by  the  equation
            C = ~A +  B.   Note that in LOGSIM, and this manual, the "~"
            is used to show negation, "~A" means "NOT A".

              2.3 Initial Conditions


                 Before LOGSIM  starts simulating  your circuit, it must
            determine the  initial state of your circuit.  To do this it
            assumes that  all nodes  start at  high logic  states, holds
            clocks and data sources in their initial states, and repeat-
            edly calculates  new states  for your  circuit.  During this
            process, all delays in the circuit are set to one time unit.

                 You are  responsible  for  ensuring  that  the  circuit
            starts in  a known state!  The easiest way is to have a data
            source that  initializes the  circuit elements as necessary,
            and then  goes to an inactive state after one time unit.  If
            the circuit  contains unstable  elements, LOGSIM will inform
            you of  that fact with a message "Element driving node xx is
            unstable."

                 The INITIAL  option (see below) can be used to manually
            set the state of your circuit.  If this is done, LOGSIM uses
            that as the initial state and does not use this process.

            3. Describing the Circuit


                 The circuit  description consists of a number of lines,
            each of  which is an element, followed by an END line.  Each
            line is either a gate, chip, clock, or data source.

                 Very Important!  Use only spaces to separate items.  Do
            not use commas, or any other punctuation.

              3.1 Gates


                 LOGSIM has  some standard  gates--AND, NAND,  OR,  NOR,
            XOR, XNOR, NOT, BUFFER, DELAYH, DELAYL, and DELAY--built in.



                                       LOGSIM





                                                                        5


            All the  gates have  one output node, and the AND, NAND, OR,
            NOR, XOR  and XNOR  can take  up to 32 input nodes.  The NOT
            gate is  a simple inverter, the BUFFER gate is a non-invert-
            ing buffer,  and the  DELAY gate  is a  non-inverting buffer
            with a  constant, specified  delay.   The DELAYH  and DELAYL
            gates are  similar to  the DELAY gate, except that they only
            delay high  or low  logic states  (respectively) by the con-
            stant delay.  The opposite state (low for a DELAYH, high for
            a DELAYL)  is delayed  by only 1 time unit.  These gates are
            further described  below, and the default gate delay (1 time
            unit +  1 time unit per input driven) formula can be changed
            by the GATEDELAY option described below.

                3.1.1 AND Gate


                 Syntax: AND [output] [input] [input] [input] ...

                 This gate ANDs together all the input nodes and outputs
            that value  to the output node.  Up to 32 nodes can be ANDed
            together with  one gate.  This gate has a default delay of 1
            time unit + 1 time unit per input driven.

                 Example: AND  3 1 2 5 15 will generate a high at node 3
            if all of nodes 1, 2, 5, and 15 are high.

                3.1.2 BUFFER Gate


                 Syntax: BUFFER [output] [input]

                 This gate  is a  non-inverting buffer--the value of the
            input appears at the output. This gate only takes one input,
            and has a default delay of 1 time unit + 1 time unit per in-
            put driven.

                 Example: BUFFER 4 5.  Node 4 equals the value of node 5
            (after the gate's inherent delay of course).

                3.1.3 DELAY Gate


                 Syntax: DELAY [output] [input] [delay]

                 This gate is a non-inverting buffer with a constant de-
            lay.   Use this  to simulate any fixed delay in the circuit.
            This gate  only takes one input.  The longest delay possible
            in LOGSIM is 32,767 time units.

                 Example: DELAY  12 1  10.  The value of node 1 will ap-
            pear at node 12 after a delay of 10 time units.






                                       LOGSIM





                                                                        6


                3.1.4 DELAYH Gate


                 Syntax: DELAYH [output] [input] [delay]

                 This gate  is a non-inverting buffer which delays logic
            high states by a constant delay.  The longest delay possible
            in LOGSIM  is 32,767  time units.   This gate only takes one
            input.  For example, if the input to a DELAYH gate (with a 4
            time unit delay) is the pattern:
                 000011111111100000001000000, the output will be
                 000000001111110000000000000.

                 Example: DELAYH  12 1 10.  The value of node 1 will ap-
            pear at  node 12  after a  delay of 10 time units if it is a
            logic high, or 1 time unit if it is a logic low.

                3.1.5 DELAYL Gate


                 Syntax: DELAYL [output] [input] [delay]

                 This gate  is a non-inverting buffer which delays logic
            low states  by a constant delay.  The longest delay possible
            in LOGSIM  is 32,767  time units.   This gate only takes one
            input.  For example, if the input to a DELAYL gate (with a 4
            time unit delay) is the pattern:
                 111100000000011111110111111, the output will be
                 111111110000001111111111111.

                 Example: DELAYL  12 1 10.  The value of node 1 will ap-
            pear at  node 12  after a  delay of 10 time units if it is a
            logic low, or 1 time unit if it is a logic high.

                3.1.6 NAND Gate


                 Syntax: NAND [output] [input] [input] [input] ...

                 This gate  NANDs together  all the input nodes and out-
            puts that  value to  the output node.  Up to 32 nodes can be
            NANDed together  with one gate.  This gate has a default de-
            lay of 1 time unit + 1 time unit per input driven.

                 Example: NAND  3 1 2 5 15 will generate a low at node 3
            if all of nodes 1, 2, 5, and 15 are high.

                3.1.7 NOR Gate


                 Syntax: NOR [output] [input] [input] [input] ...

                 This gate NORs together all the input nodes and outputs
            that value  to the output node.  Up to 32 nodes can be NORed



                                       LOGSIM





                                                                        7


            together with  one gate.  This gate has a default delay of 1
            time unit + 1 time unit per input driven.

                 Example: NOR  3 1  2 5 15 will generate a low at node 3
            if any of nodes 1, 2, 5, or 15 is high.

                3.1.8 NOT Gate


                 Syntax: NOT [output] [input]

                 This gate is simple inverter--the value of the input is
            inverted and appears at the output. This gate only takes one
            input, and  has a default delay of 1 time unit + 1 time unit
            per input driven.

                 Example: NOT  4 5.   Node  4 equals  the inverse of the
            value of node 5 (after the gate's inherent delay of course).

                3.1.9 OR Gate


                 Syntax: OR [output] [input] [input] [input] ...

                 This gate  ORs together all the input nodes and outputs
            that value  to the  output node.  Up to 32 nodes can be ORed
            together with  one gate.  This gate has a default delay of 1
            time unit + 1 time unit per input driven.

                 Example: OR  3 1  2 5 15 will generate a high at node 3
            if any of nodes 1, 2, 5, or 15 is high.

                3.1.10 XNOR Gate


                 Syntax: XNOR [output] [input] [input] [input] ...

                 This gate  XNORs together  all the input nodes and out-
            puts that  value to  the output node.  Up to 32 nodes can be
            XNORed together  with one gate.  This gate has a default de-
            lay of 1 time unit + 1 time unit per input driven.

                 Example: XNOR 3 1 2 5 15 will generate a high at node 3
            if the  value of node 3 exclusive-or the value of node 2 ex-
            clusive-or the  value of  node 5  exclusive-or the  value of
            node 15 is a logic low.

                3.1.11 XOR Gate


                 Syntax: XOR [output] [input] [input] [input] ...

                 This gate XORs together all the input nodes and outputs
            that value  to the output node.  Up to 32 nodes can be XORed



                                       LOGSIM





                                                                        8


            together with  one gate.  This gate has a default delay of 1
            time unit + 1 time unit per input driven.

                 Example: XOR  3 1 2 5 15 will generate a high at node 3
            if the  value of node 3 exclusive-or the value of node 2 ex-
            clusive-or the  value of  node 5  exclusive-or the  value of
            node 15 is a logic high.

              3.2 Chips


                 Syntax: [chip name] [pin assignments]

                 LOGSIM provides  a facility for adding new circuit ele-
            ments--chip descriptors.   A  chip descriptor is a file that
            describes the  function a  chip.   It can  also be used as a
            macro facility  to simulate  large chunks  of circuitry.  If
            LOGSIM does  not recognize an element as a gate, it searches
            for a  file with  the same  name.   You can provide full DOS
            paths as  your chip  name.   For example,  if your  chip  is
            called "JK" in your circuit descriptor file, LOGSIM looks in
            the current  directory of the current drive for a file named
            JK.  If you called it "B:\logsim\chips\jk.dat", LOGSIM would
            search for the file B:\LOGSIM\CHIPS\JK.DAT.

                 After the  name, the  pin assignments are listed.  This
            is a  of what node each pin is tied to, starting with pin 1.
            If you  had a  four pin chip named "4PIN" and pin 1 was tied
            to node 4, pin 2 to node 3, pin 3 to a constant high and pin
            4 to node 2, the line in the circuit descriptor would be:
                                    4PIN 4 3 h 2

                 A chip can have up to sixty pins.

                 Several standard  chips are included in LOGSIM, all are
            standard DIP packages.  They are described below:

                3.2.1 D Chip Descriptor


                 The D chip descriptor is identical to the 7476 chip de-
            scriptor (see below).  It is included only for compatibility
            with LOGSIM version 1.0.

                3.2.2 JK Chip Descriptor


                 The JK  chip descriptor  is identical to the 74112 chip
            descriptor (see below).  It is included only for compatibil-
            ity with LOGSIM version 1.0.







                                       LOGSIM





                                                                        9


                3.2.3 7476 Chip Descriptor

            The 7476 Chip Descriptor represents  of a 7476 chip, and is
            a negative-edge triggered D flip flop with active-low preset
            and clear.  The pin assignment is: (1) ~Preset; (2) D; (3)
            Clock; (4) ~Clear; (5) Q; (6) ~Q

                                   Function Table
                      Inputs             Outputs
                      ~PRE  ~CLR  CLK D | Q ~Q
                        L     L    X  X | H  H
                        L     H    X  X | H  L
                        H     L    X  X | L  H
                        H     H    v  L | L  H
                        H     H    v  H | H  L
                        H     H    X  X | Q ~Q

                3.2.4 74112 Chip Descriptor


                 The 74112 Chip Descriptor is equivalent to  of a 74112
            chip.   It represents a negative-edge-triggered JK flip-flop
            with preset  and clear.   Both  preset and  clear are active
            low.

                 Pin assignment:  (1) ~Preset;  (2) J; (3) Clock; (4) K;
            (5) ~Clear; (6) Q; (7) ~Q

                           Function Table
                 Inputs        Outputs
                 ~PRE ~CLR CLK J K |  Q    ~Q
                   L    L   X  X X |  H     H
                   L    H   X  X X |  H     L
                   H    L   X  X X |  L     H
                   H    H   v  L L |  Q    ~Q       v indicates a
                   H    H   v  L H |  L     H       falling edge
                   H    H   v  H L |  H     L
                   H    H   v  H H | ~Q     Q
                   H    H   H  X X |  Q    ~Q

                3.2.5 74123 Chip Descriptor


                 The 74123 chip descriptor represents  of a 74123 chip.
            Chip delays  are the  standard 1  + 1  time unit  per  input
            driven.    Pins  1 and 2 are the A and B inputs of the chip,
            pin 3  is clear,  and pins  4 and  5 are Q and ~Q.  A DELAYL
            gate must  be connected  between pins  6 and 7 (pin 7 is the
            output of  the DELAYL,  6 the  input to  the DELAYL).  Total
            pulse duration  is equal to the delay of the DELAYL plus the
            delay at  node 6  (driving one  output--the DELAYL) plus any
            delay from the output of the DELAYL to the input of the one-
            shot.   It is a 7-pin chip and is described by the following
            table:



                                       LOGSIM





                                                                        10


                      
                      Input    Output
                      1 2 3 7 | Q ~Q  6
                      X X L X | L  H  L
                      v H H X | H  L  H
                      L ^ H X | H  L  H
                      L H ^ X | H  L  H
                      X X X v | 6 ~6  L
                      X X X X | Q ~Q  L

                 Lines 2  through 4 of the table show the different ways
            to trigger the one-shot.  In addition to the change of Q and
            ~Q, a  low is outputted on pin 6.  The pulse continues until
            the low in seen on pin 7 (delayed by the DELAYL, of course),
            as shown by line 5.  The 6 and ~6 for Q and ~Q in line 5 are
            to handle  the case  that the one-shot may have been retrig-
            gered just  as pin  7 falls.  These equations force the one-
            shot to trigger again.

                3.2.6 74126 Chip Descriptor


                 The 74126 chip descriptor represents  of a 74126 chip.
            This is  a three-state  buffer, where  pin 1 is the control,
            pin 2  the input, and pin 3 the output.  Chip delays are the
            standard 1  + 1  time unit  per input driven.  It can be de-
            scribed as follows:
                           
                           Input | Output
                             1 2 | 3
                             L X | Z   (H in LOGSIM)
                             H L | L
                             H H | H

                3.2.7 74192 Chip Descriptor


                 The 74192  chip descriptor  represents a standard 74192
            counter.   The pin  assignments are  exactly as  in the real
            chip (including pin 8 for ground, and pin 16 for Vcc).  Pins
            8 & 16 are don't cares--you can tie them to anything without
            affecting the chip descriptor.

                3.2.8 74193 Chip Descriptor


                 The 74193  chip descriptor  represents a standard 74193
            counter.   The pin  assignments are  exactly as  in the real
            chip (including pin 8 for ground, and pin 16 for Vcc).  Pins
            8 & 16 are don't cares--you can tie them to anything without
            affecting the chip descriptor.






                                       LOGSIM





                                                                        11


                3.2.9 74253 Chip Descriptor


                 The 74253  chip descriptor  represents   of a standard
            74253 4-to-1  multiplexer.  It is an 8-pin chip and chip de-
            lays are  the standard  1 +  1 time  unit per  input driven.
            Pins 1  and 2  are the  select lines (pin 2 is most signifi-
            cant), pin  3 is the active-low output control.  If pin 3 is
            high, the  output is  forced high.  Pins 4 through 7 are the
            inputs C0 through C3, and pin 8 is the output.  The function
            can  be  described  by  the  equation:  8 = 3 + (4&~2&~1)  +
            (5&~2&1) + (6&2&~1) + (7&2&1).

              3.3 Clocks


                 Syntax: CLOCK [output] [pattern]

                 CLOCKS are inputs from the outside world.  They apply a
            periodic pattern  to their  output pin.  The period is given
            by the length of the pattern specified.  If you want node 21
            driven by  a clock  with a 10 time unit period, of which the
            first 3  are low and the last 7 are high, that would be rep-
            resented by the line: CLOCK 21 0001111111.  Another example:
            The line  CLOCK 1  1111001 represents a clock driving node 1
            with a  period of  7, of  which the  first 4 and last 1 time
            units are high and the 5th and 6th time units are low.

                 Long series  of 1's  and 0's  can be  compressed to the
            forms "(repeat  * 1)"  and "(repeat * 0)" respectively.  For
            example, the  line "CLOCK  21 0001111111"  can be  condensed
            into "CLOCK 21 (3*0)(7*1)".  Note that only a single bit can
            follow the  asterisk, trying to represent the pattern 010101
            with (3*01) is wrong and WILL NOT WORK.

              3.4 Data Sources


                 Syntax: DATA [output] [pattern]

                 DATA SOURCES  are inputs  from the outside world.  They
            apply a  specified pattern  to their  output  pin.    Unlike
            clocks, which  continuously repeat  their  pattern,  a  data
            source remains  at its  last state when the pattern has been
            exhausted.   For example,  the line  DATA 5  1001 is  a data
            source driving  node 5  that starts  high, goes low for time
            units 2 and 3, and then goes high for the rest of eternity.

                 Long series  of 1's  and 0's  can be  compressed to the
            forms "(repeat  * 1)"  and "(repeat * 0)" respectively.  For
            example, the line "DATA 21 0001111111" can be condensed into
            "DATA 21 (3*0)(7*1)".   Note that only a single bit can fol-
            low the  asterisk, trying  to represent  the pattern  010101
            with (3*01) is wrong and WILL NOT WORK.



                                       LOGSIM





                                                                        12


            4. Simulating the Circuit


                 Now that you've described your circuit, LOGSIM can sim-
            ulate it.   By default, LOGSIM uses a constant one time unit
            delay for  every output  (regardless of inputs driven), dis-
            plays on the CRT, and goes for 100 time units.  By selecting
            options, you  can change  these defaults to better suit your
            needs.

              4.1 Simulation Time


                 Syntax: TIME [end]
                      OR
                         TIME [start] [end]

                 The circuit  simulation can  last for  any number up to
            32,767 time  units.  The default is 100 time units (based on
            a screen width of 100) but this can be changed with the TIME
            option.   If you change the screen width (with the WIDTH op-
            tion), the  default simulation  time will also change to the
            screen width.   The  number [end]  specified is  the time in
            time units  to simulate.  For example, TIME 120 will run the
            simulation for 120 time units.

                 If you  choose the second form (TIME [start] [end]) the
            output from  the simulation  will only  be produced  for the
            times between start and end.  For example, TIME 100 200 will
            simulate the circuit for 200 time units, and the only output
            that will  appear will  be that  between 100  and  200  time
            units.

              4.2 Rise Time Calculations


                 Syntax: RISE [n]
                      OR
                         RISE VARIABLE
                      OR
                         RISE FIXED

                 Output delays  can be  calculated in one of three meth-
            ods.     Delays  can  be  constant  throughout  the  circuit
            (exception: DELAY,  DELAYL and  DELAYH gates), or delays can
            be a constant delay plus a certain amount per input the out-
            put drives.   The constant delay and the increment per input
            depends on what type of element is under consideration.  The
            third method  just uses  the constant, element-dependant de-
            lay.  These three methods can be expressed as:

                 1) Delay = n





                                       LOGSIM





                                                                        13


                 2) Delay = f(element type) + v(element type) * # inputs
                            driven by the output

                 or

                 3) Delay = f(element type)

                 By default,  LOGSIM uses the first form, with a uniform
            1 time  unit delay  for all  elements.   You can change this
            with the  RISE option.  The longest delay possible in LOGSIM
            is 32,767 time units.

                 To select  a uniform  delay for  all  elements  (except
            DELAY gates),  use the "RISE n" option.  For example, RISE 4
            will set  the output  delay for  all elements  except  DELAY
            gates to 4 time units.  This option overrides all delay for-
            mulas, including those specified with the GATEDELAY option.

                 To select  the fixed + increment delay (#2, above), use
            the RISE  VARIABLE option.   If  you are using the GATEDELAY
            option, either  RISE VARIABLE or RISE FIXED is also required
            before those numbers are utilized.

                 To select  fixed  delay  based  on  element  type  (#3,
            above), use the RISE FIXED option.

              4.3 Gate Delays


                 Syntax: GATEDELAY [fixed] [variable]

                 By default,  all gates in LOGSIM use a delay formula of
            1 time  unit +  1 time unit per input driven.  The GATEDELAY
            option is  used to  change the  numbers to  whatever is  re-
            quired. The  formula is always [fixed] + [variable] * number
            of inputs driven.  Example: GATEDELAY 2 0.1 changes the gate
            delays to 2 time units + 0.1 time units per input driven.

                 Note that  unless you  use either  the RISE VARIABLE or
            RISE FIXED option, GATEDELAY does not have any effect.

              4.4 Initial Conditions


                 Syntax:   INITIAL   [1st   node's   value][2nd   node's
                      value]...[last node's value]

                 This option  allows you to specify the initial state of
            all the  nodes in  the circuit  (note: it  must be  ALL, not
            some).   Simply list  the logic states (1 or 0) of each node
            in ascending  order after  the word  INITIAL.   For example,
            INITIAL 00001111  is an  8 node  circuit,  where  the  first
            (lowest numbered) 4 start low and the last 4 high.




                                       LOGSIM





                                                                        14


              4.5 Output Modes


                 LOGSIM can  output the results of its simulation in one
            of four ways: it can display on the CRT (the default), write
            to a file, print using graphics, or a quick-and-dirty print-
            out.  By using the DISPLAY, FILE, PRINT, and FPRINT options,
            the user  can select  which of these four methods.  Only one
            method can be used in any given simulation, so including two
            or more  of these option in your circuit descriptor file re-
            sults in only the last one taking effect.

                 To see  samples of  all four  output modes, execute the
            batch file OUTSAMPL.BAT.

                4.5.1 Display


                 Syntax: DISPLAY

                 LOGSIM will  display the  timing diagram resulting from
            the simulation  on the  CRT.  If nodes are selected with the
            MONITOR option,  they will  be displayed,  otherwise the  20
            lowest numbered nodes will be shown.

                 LOGSIM can  fit 600 time units (default is only 100) on
            the screen,  and will  beep when the screen is full.  LOGSIM
            will then  wait until the user presses a key before display-
            ing the next screenfull.

                4.5.2 File


                 Syntax: FILE [filename]

                 LOGSIM will  output the circuit timing to the specified
            file.  Every node in the circuit will be listed, even if the
            MONITOR option has been used.

                 A sample  of FILE  output, using  the circuit  0124, is
            shown below.
















                                       LOGSIM





                                                                        15


                      
                      
                                          Timing List
                      
                                      Nodes
                            000000000
                            000000000
                            000001111
                      Time  123453456
                      
                      1     001110001
                      2     011110001
                      3     011110001
                      4     011110001
                      5     111110001
                      6     111110001
                      7     111110001
                      8     011110001
                      9     011110000
                      10    011110010
                      11    011110010
                      12    111110010
                      13    111110010
                      14    111110010
                      15    011110010
                      16    011110011
                      17    011010101
                      18    011010101
                      19    111000101
                      20    111000101
                      21    111000101
                      22    011000101
                      23    011001101
                      24    010101001
                      25    010101001

                 The left-most  column is the time in time units.  Read-
            ing down  each column,  the top  is the node number (a four-
            digit number,  i.e. the  first node listed is 0001, the next
            0002, and  so on up to node 0016).  Below that, reading ver-
            tically in  each column,  is a  list of  the states for that
            node.   A '1'  indicates a logic high, and a '0' indicates a
            logic low.

                4.5.3 Print


                 Syntax: PRINT

                 Use of this option requires that you had previously run
            the graphics  screen dump  program (GRAPHICS.COM  on PC-DOS,
            PSC.....COM on MS-DOS, see your DOS manual for more informa-
            tion).  The PRINT option is identical to the DISPLAY option,
            but at  the end of each screenfull, instead of the beep-and-



                                       LOGSIM





                                                                        16


            wait routine, LOGSIM copies the screen to the printer.  This
            takes time.

                4.5.4 Fprint


                 FPRINT (which  stands for  Fast PRINT)  will print  the
            timing diagram  on the  printer in  the LPT1:  slot  (a.k.a.
            prn).   It is much faster than the PRINT option, but doesn't
            look as  nice.   FPRINT displays the nodes selected with the
            MONITOR option,  or the  twenty lowest numbered nodes if the
            MONITOR option is not used.

                 A sample  of FPRINT, from the 0124 sample circuit, look
            like:
                                               Timing List
                      
                                        Nodes
                       0   0    0    0
                       0   0    0    0
                       0   1    1    1
                       1   3    4    5
                      |   |    |    |
                      |   |    |    |
                      |   |    |    |
                      |   |    |    |
                       \  |    |    |
                        | |    |    |
                        | |    |    |
                       /  |    |    |
                      |   |    |    |
                      |   |    |     \
                      |   |    |      |
                       \  |    |      |
                        | |    |      |
                        | |    |      |
                       /  |    |      |
                      |   |    |      |
                      |   |     \    /
                      |   |      |  |
                       \  |      |  |
                        | |      |  |
                        | |      |  |
                       /  |      |  |
                      |    \     |  |
                      |     |   /   |
                      |     |  |    |

                 Again, read the node numbers vertically in each column.
            The timing  diagram makes  more sense if you rotate the page
            90 degrees  counter-clockwise.   Now, read  it like a normal
            timing diagram,  with time  increasing to  the right.  A '\'
            indicates a rising edge, and a '/' indicates a falling edge.




                                       LOGSIM





                                                                        17


              4.6 Time Units per Screen


                 Syntax: WIDTH [n]

                 By default,  LOGSIM displays  100 time units per screen
            (or page)  in the  DISPLAY and  PRINT output modes.  You can
            alter this  to anywhere  between 10  and 600  time units per
            screen with  the WIDTH  option.   Example: WIDTH 300 display
            300 time  units per screen (300 per page in PRINT mode).  If
            the TIME  option is  not used,  and the WIDTH option is, the
            simulation time will default to the screen width.

              4.7 Monitoring nodes


                 Syntax: MONITOR [node] [node] [node] ...

                 MONITOR is  used in conjunction with the DISPLAY, PRINT
            and FPRINT  options to select which nodes to display.  Up to
            twenty nodes  can be  selected in  any one  simulation.  The
            nodes will  be displayed  in the order that you list them in
            the MONITOR option, and you can repeat nodes if you wish.

                 Example: to display nodes 1, 3, 13, 14, 15, and 20, use
            MONITOR 1 3 13 14 15 20.

              4.8 Fanout Lists


                 Syntax: FANOUT
                      OR
                         FANOUT [file]

                 LOGSIM can count the number of inputs that each node is
            driving.   The FANOUT option will have LOGSIM display a list
            of how  many inputs  each node  is driving.  By default, the
            FANOUT list  appears on  the CRT,  but using the second form
            (FANOUT [file]) lets  you send  the output to a file of your
            choice.   For example, FANOUT CKT3FAN writes the fanout list
            to the file CKT3FAN.

            5. Chip Descriptions


                 The hardest  and most  useful (isn't  that  always  the
            case) part  of LOGSIM  lies in  its expandability.  Only the
            gates described  above are  built in  to the LOGSIM program.
            All other chips are included in chip descriptor files.  Yes,
            you can write you own chip descriptors, and now I'm going to
            tell you how.






                                       LOGSIM





                                                                        18


              5.1 Making New Chips


                 To implement  a new  chip (or  macro), you must write a
            new chip  descriptor.   A chip  descriptor consists  of 4 or
            more lines  that functionally  describe the chip.  The first
            three lines  of a  chip descriptor state the number of pins,
            fixed and variable delay, the mode select pins, and the out-
            put pins.   The  remaining lines  contain equations  for the
            output pins conditions for the mode pins and  in that mode.

                5.1.1 Pins, Delay, Mode and Output Pins


                 The first  line contains  three numbers:  the number of
            pins on  this chip,  the fixed delay increment and the delay
            increment.   Pins on a chip are numbered sequentially start-
            ing with 1.

                 The fixed  delay [  f(element) ]  and  delay  increment
            [ v(element) ] are used in computing rise times for the out-
            puts.  See the section on Rise Time Calculations.

                 The fixed  delay must  be an  integral number  of  time
            units, but  the variable  delay can can be in fractions of a
            time unit (e.g. 0.25)

                 The second line,  lists the Mode Select Pins.  Mode se-
            lect pins  are used to distinguish between several different
            behaviors of the chip.  For example, in the JK chip descrip-
            tor, pins  1, 3,  and 5  are mode  select pins--the ~PRESET,
            CLOCK, and  ~CLEAR  pins.  A JK flip flop's behavior is dif-
            ferent depending  on the  states of  the CLEAR,  PRESET, and
            CLOCK lines.

                 Mode select  pins are  included for convenience, as the
            JK chip descriptor could be re-written to use only the CLOCK
            pin as a mode select pin

                 Mode select  pins MUST  be used  for any edge-triggered
            inputs.

                 Every chip  descriptor MUST  have at least one mode se-
            lect pin!

                 The third line lists the output pins for this chip.  An
            output pin  is a pin whose state is determined by this chip.
            The output  delay associated with a chip applies between the
            output pin  and the  outside world.  For use within the same
            chip, there  is only a one time unit delay.  For example, in
            the JK  chip descriptor,  if the mode select pins fall under
            the HXH  state and  there is a 5 time unit delay.  The newly
            determined state for pins 6 and 7 appear 5 time units later,
            but they are usable in the chip itself one time unit later.



                                       LOGSIM





                                                                        19


                5.1.2 Chip Modes


                 Chip modes can be thought of as behavior patterns.  For
            example, a  74193 counter  can either be holding the present
            count, loading  a new  count with  the LOAD pin, clearing to
            zero with  the CLEAR pin, counting up, or counting down.  By
            implementing each  of those cases as patterns of mode select
            pins, the  equations are  simpler and more intuitively obvi-
            ous.

                 In order  to implement edge-triggered devices (example:
            the JK  flip flop,  on which  the clock pin is negative-edge
            triggered), you will have to include the edge-triggered pins
            among your mode select pins.

                5.1.3 Output Equations


                 The fourth and following lines of a chip descriptor de-
            scribe contain  equations describing  the  chip's  function.
            Each line  consists of  a mode  select pattern, a colon (:),
            the equations  for the  output pins in that mode.  The equa-
            tions follow  the colon  and are  separated by  commas.  THe
            equations determine the states of the output pins--the first
            equation goes with the first output pin, the second with the
            second, etc.

                 The mode  select pattern  is a description of the state
            of the  mode select pins.  To represent this, LOGSIM uses an
            H to  represent a  logic high  state, an  L for low, a X for
            don't-care, a  v for  a falling  edge, and  a ^ for a rising
            edge.   In the  JK chip descriptor, the mode select pins are
            1, 3,  and 5.  The mode select pattern "HVH" means that node
            1 is  high, there is a falling edge on node 3, and node 5 is
            high.

                 LOGSIM examines  each mode  select pattern in the order
            they are  listed.   The equations  associated with the first
            one mode select pattern that applies are used.

                 Examples:  Using the JK chip descriptor (see below), if
            the current  states of  pins 1, 3, and 5 are high, low, low,
            then the  equations on the sixth line (with the HXL pattern)
            are used: pin 6 goes low and pin 7 goes high.

                 If nodes  1 and 5 remain high while node 3 changes from
            a high  to low state, the seventh line (HvH) applies.  These
            equations calculate  the new  state for the Q and ~Q outputs
            according to the standard JK truth table.







                                       LOGSIM





                                                                        20


              5.2 Sample Chip Descriptions

                               The JK Chip Descriptor

                 This is a small chip descriptor that illustrates all of
            the design  topics discussed above.  Examining this chip de-
            scriptor should dispel any questions about the chip descrip-
            tor format.  The chip descriptor file is:
                      7 1 1
                      1 3 5
                      6 7
                      LxL: H, H
                      LxH: H, L
                      HxL: L, H
                      HvH: (6 & ~4) + (7 & 2), ~( (6 & ~4) + (7 & 2) )
                      HxH: ~7, ~6

                 It is a seven pin chip, with a delay of 1 time unit + 1
            per input  driven (7 1 1).  Pins 1, 3 and 5 are the mode se-
            lect pins (1 3 5), and pins 6 and 7 are the outputs (6 7).

                 The equations  show that  both outputs  (Q and  ~Q) are
            high when  pins 1  and 3 (~PRESET and ~CLEAR) are low.  Else
            if pin  1 is  low and  pin 5  is high (presetting), pin 6 is
            high and  pin 7  is low.  Else if pin 1 is high and pin 5 is
            low (clearing),  pin 6  is low and 7 is high. Else if pins 1
            and 5  are high while there is a falling edge on pin 3, pins
            6 and  7 follow  the standard  JK rules  (check them--you'll
            see).   Finally, if  pins 1 and 5 are high, pins 6 and 7 are
            inverses of each other ( Q = ~ (~Q) and ~Q = ~(Q) ).

              5.3 Simulating ROMS


                 ROMs are  easy to simulate.  Just use the address lines
            as the  mode select  lines and  express the output directly.
            For example,  an imaginary  4-word, 4-bit  ROM with contents
            0001, 0010,  0100, and  1111 in addresses 0, 1, 2, and 3 re-
            spectively.   Pins 1  through 2  are the address inputs, and
            pins 3  through 6  are the  data outputs,  delays are 4 time
            units plus  .25 time  units per  input driven.  This can  be
            coded as:

                      6 4 .25
                      1 2 3 4
                      5 6 7 8
                      LL:L,L,L,H
                      LH:L,L,H,L
                      HL:L,H,L,L
                      HH:H,H,H,H

                 Of course,  if you  can reduce the number of equations,
            you will only improve LOGSIM's performance.




                                       LOGSIM





                                                                        21


              5.4 Simulating RAMS


                 Good Luck!   RAMs  have to be represented as a group of
            flip-flops with  address decoding  and output  selection--in
            other words, you'll have to build every memory cell by hand.
            This is one item that will be changed in the future.

              5.5 Simulating PALs and PLAs


                 This is  easier than  a ROM,  just write  the equations
            down and  you're done.   For  example,  consider  a  4-input
            (called A,  B, C,  and D),  4-output (called W, X, Y, and Z)
            PAL       which        implements       the       equations:
            W = A+B; X = W*~D; Y = A&B&C&D; Z = ~(A*B) + ~(C&D).   We'll
            use pins  1 through  4 for  A through D and pins 5 through 8
            for pins W through Z.  Since there is no obvious mode select
            pin, we'll choose pin 1.  Use a standard 1 time unit + 1 per
            input driven delay, and we get:

                      8 1 1
                      1
                      5 6 7 8
                      X: 1+2, 5*~4, 1&2&3&4, ~(1&2) + ~(3&4)

                 By using pin 1 as a mode select and using the pattern X
            (don't-care), we  meet LOGSIM's requirement for at least one
            mode select pin and we don't obscure the equations.




























                                       LOGSIM





                                                                        A


                                       Index
            
            Chip descriptor, 8, 17
            Circuit descriptor, 2
            
            END statement, 2
            
            GRAPHICS.COM, 1
            
            Macro facility
              see Chip descriptor
            
            Output delays, 12
            
            Pin assignments, 8
            Precedence, 3
            PSCxxxx.COM, 1
            
            Special nodes, 3
            
            Time unit, 1
            
            Wired-ANDed, 3
            

































                                       LOGSIM


