
Copyright by Miguel A. Guerrero, 1998
All Rights reserved

Please report bugs and suggestions to e-mail: ma_gm@yahoo.com

Table Of Contents

1. Disclaimer: 
2. Revision History:
3. Introduction:
4. Installation and Customization:
5. Description of the package
	5.1 Netlist Comparator (NetCmp)
	5.2 Partlist Comparator (PartCmp)
	5.3 BOM Generator (BOM)
	5.4 Extended DRC checker (XDrc)
6. Limitations:
7. How to Register:



1. Disclaimer:

This software is distributed on "as is" basis. The author disclaims any and all warranties. In no event shall 
the copyright holder be liable for any incidental, punitive, or consequential damages of any kind arising from 
the use of this program. Use of this software indicates you agree to this.
The tools are written mainly in Perl. Perl interpreters are freely available on the internet. You will need to 
install one to run the tools. The tools have been tested, under MS Windows 95 platform, using the Perl 
interpreter for Win32 provided by ActiveWare. You can download this interpreter on
http://www.ActiveState.com
 (Look under http://www.activestate.com/pw32)
Perl version 5.003_07 is the built that has been used to test this software
Perl may be copied only under the terms of either the Artistic License or the GNU General Public License, 
which may be found in the Perl 5.0 source kit.
The Perl interpreter should be installed and made available in the path before executing ptools.

2. Revision History:

? Rev 0.92 (5/8/98) First beta release 
? Rev 0.93
- Fixed return value on some netlist/partlist converters
? Ref 0.94
- Added XDrc utility. 
- Moved to Perl 5.0

3. Introduction:

The package contains several utilities whose aim is to help to do everyday tasks in electronic CAD design 
tasks. They will help you to keep track of changes in schematics, (Netlist and Partlist comparators) and to 
link a raw BOM with a company Component Data Base or AVL (Approved Vendor List) to generate Bill Of 
Materials with no manual intervention (The utility is able to handle customer specific BOMs and Non-insert 
components, as long as they are properly specified during the schematic stage). They also provide an 
extended DRC utility that checks the netlist against common known problems that can be found on the 
netlist scanning is topology and making some assumptions on the components and nets according to their 
name. 
The point of entry to the programs is usually a netlist. This makes the utilities independent of your 
schematic tool.
Currently, The following formats are supported: Allegro, Mentor, Tango/Accel and Pads PCB. New formats 
can be implemented on demand.
4. Installation and Customization:
To install the package just double click on it and it will decompress itself. You will be prompted for the 
location where it will be decompressed
The tools should be run from the directory:
InstDrive:\InstallationPath\ptools094
Unless you add it to the path in your autoexec.bat, in which case you can execute them from anywhere 
(strongly recommended)
The file 'pt_custm.bat' includes the definition of some environment variables that will be used by the tools. 
You can modify them according to your environment. For instance:
Variable
Meaninng
Default value
Customizable
Pt
Instalition path
...\ptools094
No
Perl
Perl interpr. Path
Perl
Yes
Pted
File Viewer
Notepad
Yes
Ptavlnf
AVL number of fields
8
Yes
Ptavlsq
AVL field sequence to be 
included on BOM
0 1 3 4 5 6 7 2
Yes
? The first one 'pt' is assigned automatically according to the installation directory so you don't need 
to worry about it 
? 'perl', will have the command line to execute to call the perl interpreter. if your interpreter is on the 
path, then replace it by 'set perl=perl' 
? 'pted', will be used to call a file viewer. If you are running under DOS and not under Win95, you 
should replace it by 'set pted=edit' 
? 'ptavlnf' tells the tool how many fields does the Component Data Base (AVL) have. You should 
customize it to your case. 
? 'ptavlsq' sets the sequence of fields that will be output onto the BOM from the AVL. it also 
specifies in which order (0 denotes 1st field) 
? The customization of XDrc utility is done apart in the file XDrc.ini. See paragraph 5.4 for a complete 
description


5. Description of the package

The following tools are available:
NetCmp: A netlist comparator. It reports added, deleted, modified and renamed nets in an easy to read 
format
PartCmp: reports the difference in the partlist section of two netlists. It tells you which parts have been 
added, deleted or have changed any of the attributes reported in the netlist.
BOM: Takes as input a netlist generated according to a specific 'format' (see details bellow). It first deletes 
de elements who carry the attribute NO_STUFF used by convention to denote the components that should 
be deleted from the BOM because they should not been assembled on the board.
XDRC: Is an extension of the usual Design rule checking. It looks into the topology of the netlist to flag 
possible errors.
It then takes a key field (as the company Part Number) used as a key to the company data base (called 
here AVL or Approved Vendor List). The program takes the key from every entry present in the netlist and 
takes the rest of the fields associated with that component from the AVL. The result is a BOM with all sort 
of detailed information about the components, extracted from the netlist using only the key field. This allows 
to keep the component information only in the data base instead of having to stuff all these fields on the 
schematic to be able to get them on the BOM. This is also good to generate BOM from netlists extracted 
from a board layout.
5.1 Netlist Comparator (NetCmp)
To find out about its syntax, execute it at the DOS prompt, with no parameters
c:> NetCmp
You'll get something like
Netlist Comparison utility Rev X.XX mm/dd/yy
the sintax is : NetCmp oldnet fmt_old newnet fmt_new
where :

oldnet.net : is the filename of the old netlist
fmt_old : is the old netlist format according
to the following list

   mnt : for Mentor netlist
   all : for Allegro netlist
   tng : for Tango/Accel netlist
   pds : for Pads PCB netlist
   ...

newnet.net : is the filename of the new netlist
fmt_new : is the new netlist format
(same formats than fmt_old)
Two netlist files are provided to be used as an example, enter the following:
c:> NetCmp NET1 ALL NET2 ALL
Which means, compare netlist file 'net1.net' which is in ALLegro format with the newer file 'net2.net' which is 
also in format ALLegro. That is, you can compare netlists that are in different formats, specifying each one 
separately.
The resulting report is stored in a file called 'Net_diff.txt' that will be open in an editor once the processing 
finishes. The following is what you will get on the screen while the program executes
c:> NetCmp net1 all net2 all

- CONVERTING net1.net TO INTERNAL k-format
- CONVERTING net2.net TO INTERNAL k-format
- COMPARING net1.k WITH net2.k
Comparison. Part a
Sorting removed nets file
Sorting added nets file
Comparison. Part b
Report is in NET_DIFF.TXT

c:>
As you can see the first step is to convert the netlist into an internal common format called k-format. This 
step simplifies the comparison program, which has to deal only with one format of netlist. The conversion to 
this k-format is done in three steps with the utilities under the 'net_cnv' directory.
Native format
->
i-format
->
is-format
->
k-format
 
xxx2i.pl
 
Sort
 
is2k.pl
 
Where:
? xxx2i.pl, xxx being:
mnt for mentor
all for allegro
tng for Tango/Accel
pds for Pads PCB
and so on.., converts from native format to i-format (after internal format)
? sort, just sorts the entries on the .i file (is after i sorted format) 
? k-format is a compactation of is-format, and is an easy-to-process format for subsequent steps in 
Perl
If you need to handle a new netlist format, you just need to write a converter for the first step (i.e. for netlist 
format yyy, write a yyy2i.pl converter) or e-mail me and for a reasonable price I can do it for you. Place it on 
the 'net_cnv' directory and it will be handled automatically.
The following is an example of how the i-format looks like, so that you can write your own converter:
Example of part of Allegro netlist:
...
LSDA; H2.4 U19.8 R149.2
LSCL; H2.3 R148.2 U19.7
8051_RST; U19.9
PASSTHRU; U19.4 SW1.13
UCAD9; U19.22 U21.24 U22.24
...
In i-format it will look like:
...
LSDA!H2-4
LSDA!U19-8
LSDA!R149-2
LSCL!H2-3
LSCL!R148-2
LSCL!U19-7
8051!RST U19-9
PASSTHRU!U19-4
PASSTHRU!SW1-13
UCAD9!U19-22
UCAD9!U21-24
UCAD9!U22-24
..
Simple, isn't it? Every line has a single net-name pin-name pair, Using a hyphen to separate refdes from pin 
number as convention
After this step, the conversion to k-format is just an alphabetical sort and then a compaction (taking all 
connections on the same net to the same line)
...
LSCL!H2-3 R148-2 U19-7
LSDA!H2-4 R149-2 U19-8
N52!H2-1 R147-2
NTSC/PAL!SW1-12 U19-5
PASSTHRU!SW1-13 U19-4
...
Some lines got moved in and some moved out because of the alphabetical order but the idea is that in k-
format the lines are alphabetically sorted and the pin names are too inside the same net. A colon separates 
net-name from the connection list
The Netlist Report tells you details about the changes on the netlist and finally if the netlists are:
IDENTICAL : They have same net-names and connections (it doesn't mean that both files are exactly the same tough, 
just that the connections are the same for both files)
EQUIVALENT: Only renamed nets appear. So the netlist represent the same connectivity, but name changes are 
present
DIFFERENT: Netlists don't reflect same connectivity
5.2 Partlist Comparator (PartCmp)
This tools is quite straight-forward. Given two netlists will tell you which parts were added, removed or just 
got any kind of change on the attributes that show-up in the netlist (like a change in the value or in the 
package)
To find out about its syntax, execute it at the DOS prompt, with no parameters
c:> PartCmp
You'll get something like

Component list comparison for utility Rev X.XX mm/dd/yy
the sintax is : PartCmp oldfile fmtold newfile fmtnew
where :

oldfile.ext : is the filename of the old net/component list
newfile.ext : is the filename of the new net/component list
oldfmt : format of oldfile net/component list
newfmt : format of oldfile net/component list
         all for Allegro format
         cmp for Mentor format
         ...
ext : is assumed 'net' for Allegro format
ext : is assumed 'cmp' for Mentor format
...
Execute the following example:
c:> PartCmp NET1 ALL NET2 ALL
Which means that we want to compare component list on 'net1.net' which is in Allegro format to the 
modified newer file 'net2.net' which is in Allegro format too (as the second all indicates)
The report may look like:

COMPONENT LIST comparison utility Rev 0.9 5/12/97
OLD Component List : net1.cs
NEW component List : net2.cs
Report file : PART_DIF.TXT

MODIFIED components
===================

ADDED components
================

REMOVED components
==================
Comp. REMOVED : C59
OLD: 2981 1UF
In this case only one component was removed. The result in on the file 'Part_diff.txt' which will be open after 
the processing is done. You can rename if you need to.
For the partlist comparison also a conversion to an internal format is done to separate the conversion task 
from the comparison one. The flow is the following
native format
->
c-format
->
cs-format
 
xxx2c.pl
 
Sort
 
Example of ALLEGRO NETLIST file
$PACKAGES
0641_A! 22PF; C1000 C2000,
C3000		
0608_A! 1000PF; C1001
...
$NETS
/VME_DTACK; P1.A16 U42.3 R409.2 R788.1
...
$END
The expected output would be is (c-format)
C1000|0641_A|22PF
C2000|0641_A|22PF
C3000|0641_A|22PF
C1001|0608_A|1000PF
As you can see there is a line for every component, and component attributes are separated by the pipe 
character (|)
After this just an alphabetical sort and the cs-format is ready to be easily processed in Perl. 
cs-format
C1000|0641_A|22PF
C1001|0608_A|1000PF
C2000|0641_A|22PF
C3000|0641_A|22PF
If you need to handle a new format (abbreviated as yyy-format), you just need to write a yyy2c.pl program 
and place it on the 'part_cnv' directory. See mnt2c.pl and all2c.pl as examples
5.3 BOM Generator (BOM)
Most schematic entry tools allow you to generate Bill of Materials with a considerable amount of flexibility in 
the output fields, formatting etc. They usually don't allow you to selectively remove some components from 
the BOM though (those that shouldn't be assembled on the final built), so you end up doing this manually. 
Manual tasks are slow and error prone, so it is desirable to have a tool that allows you to do this 
automatically.
Another usual problem is the need of having to stuff the same board with different components regarding the 
application or the customer. Let's talk in general about 'customer specific' BOM's to denote these different 
BOM's from the same schematic. This task is also usually handled manually
Finally, BOM's generated from schematics usually lack a lot of information that is helpful to have when 
looking at the BOM. The have only the fields stuffed on the component attributes on the Schematic (Part 
Value, Manufacturer Part Number for example). Usually the company database has much more fields (price, 
lead time, mechanical model, power consumption...). There are two ways to handle this:
1) Stuff all this fields on the component and generate the BOM with the desired fields from the schematic 
tool. This approach has a problem. It is a nightmare to keep in sync the main database with every single 
component in all the schematics of the company, and it is a cumbersome task to create new components. 
This approach usually requires to have a librarian person devoted to these tasks and all new components 
should be created in a centralized way. Even this way it is very difficult to have the data updated
2) Keep a main data base and keep only minimum information on the Schematic. Let's say for instance the 
following set of attributes:
Part Value (ex. 1K)
Part Number (ex. 100-0034)
Stuffed (ex. NO_STUFF, or just empty if must be STUFFED)
Then generate the BOM and use the Part Number field as a key to enter extract from the database the rest 
of the fields and generate a linked file. This approach is available also in some tools linking the BOM with a 
file. But if you generate the BOM this way, you still have to deal somehow with the problems mentioned 
above.
Also, if you want to extract the BOM from a layout, usually it is not straightforward to link it with a database.
This tools assumes we are using approach 2) to handle the extra fields and allows you to remove 
components which carry the NO_STUFF attribute automatically from the BOM. It allows you also to define 
different values for a component for customer specific BOMs. Just create the schematic using the following 
conventions
Attributes for main Configuration:
Part Value
Part Reference
Part Number
Stuffed
Attributes added to the component in case a 2nd configuration exists
cfg2 Part Value
cfg2 Part Reference
cfg2 Part Number
cfg2 Stuffed
and so on...
To extract the linked BOM, generate a netlist using the following combination of attributes as PCB footprint 
field (this netlist will be used only for the BOM not for the layout)
? If only 1 configuration exists:
PCB footprint: {Part Number},{Stuffed}
? For 2 configurations:
PCB footprint: {Part Number},{Stuffed}|{cfg2 Part Number},{cfg2 Stuffed}
And so on. This field will be used by the BOM processor to generate individual BOMs for every customer 
specific configurations and removing the components whose Stuffed field is equal to NO_STUFF (anything 
different from this is assumed STUFFED)
The only additional requirement to get a linked BOM is to have a copy of the company component data base 
in tab delimited format, then convert it into a format useful for this tool using the following command
c:> tab2avl companydb.tab avl.db
This takes your database (assumed companydb.tab) tab delimited, and creates the file AVL.DB, that will be 
used by BOM program to link with the created BOMs
An example is provided (avl.tab and avl.db). avl.db can be created from avl.tab as follows
c:> tab2avl avl.tab avl.db
Then, generate a linked bom using the following example:
c:> BOM net4bom all
Where net4bom.net was a netlist created using conventions explained on "Schematic design guidelines" 
document in allegro format (all)
The output is a tab-delimited file called net4bom.tx1 (1 from 1st customer specific configuration or main 
configuration). If your netlist is generated with fields for more than one configuration (customer specifics) 
then execute,
c:> BOM your_netlist mnt 2
(Assumed to be in mentor format in this case)
This will generate a 'your_netlist.tx2', for the 2nd customer specific BOM.
5.4 Extended DRC checker (XDrc)
Extended DRC checker is a utility that scans your netlist looking for common mistakes and generating a 
warning whenever a suspicious construction is found on the netlist. To do that, some assumptions are done 
regarding what the components are in function of their reference designator. Some other assumptions are 
done looking at the net name. To maximize the usefulness of this tool, a convention should be used when 
naming the nets.
The idea of this tool is based on using the "intention-notation" by which reference designator and net name 
give additional information to the tool about the functionality of the elements found on the netlist. So 
topology plus some assumptions based on this notation allow this tool flag some possible mistakes.
An example will make it clearer: The intention notation for nets makes net-names to be composed of a 
name followed by an attribute list. The attribute for clock nets can be for instance 'CLK'. Examples of clock 
nets would be
UP_CLK
PCI_CLK
16MHZ_BUFF_CLK
(Where we are using the '_' as separator between name and attributes)
Names that wouldn't follow the notation are:
UP_CLOCK
UPCLK
CLOCK_PCI
A checking that the tool does is to verify that the clock signals have some sort of terminator (series or 
parallel). For that it scans for R/C networks in parallel, a series resistor for series terminator etc. If nothing is 
found it will be flagged so that the designer can check it
There are several rules as this one incorporated into the checker, an more will be added in the future.
Also some a layout report will be generated that ca be used as a starting point for the routing guidelines 
sent to the layout house (it flags clocks, differential pairs, decoupling capacitors etc. to be handled properly)
For a better description of this notation, read the "Schematic design guidelines" document.
The reference designators and net attributes used can be customized in the file "xdrc.ini"
The syntax of Xdrc is:
Extended DRC checker utility Rev 0.91 5/17/98
 
The Syntax is : xdrc filenet netfmt detail_lvl
 
where :
 
filenet.net : is the filename of the netlist to check
netfmt : is the netlist format according to the
following list
 
mnt : for Mentor netlist
all : for Allegro netlist
tng : for Tango/Accel netlist
pds : for Pads PCB netlist
 
detail_lvl : Is a number higher for higher level of detail on
the output report
The report file is named xdrc_rpt.txt and will be open with the default editor (see 'pted' environment variable 
on 4.) once the processing is finished


6. Limitations:


The following characters shall not appear in a net name:
! ' " <Space>
The following characters shall not appear in a component ref. designator:
! . , -
Component attributes (Part Value, Package...) in the netlist shall not contain:
| <Space> 



7. How to Register:

These utilities are Shareware. If you find yourself using it for more than two weeks, you must register. Send 
a $35 check (or the equivalent in your currency) to:
Miguel Guerrero
2175 Decoto Rd. Apt 156
Union City CA 94587 USA
Being registered you will receive updates to this software at 20% of its price and information on other low 
price CAD related software that can improve your design process.
Check http://members.tripod.com/~ma_gm for new releases
To complete the registration, e-mail the following information to: ma_gm@yahoo.com
First Name:
Last Name:
Job Title:
Company:
e-mail:
Please, report any bugs or suggestions you may have to the e-mail: ma_gm@yahoo.com
 
