jsmith@red-branch.MIT.EDU wrote:
: Theodore Walton (tpwalton@ix.netcom.com) wrote:
: : I am looking for info on the Mac NuBus with the intention of designing 
: : an expansion backplane for heritage Macs, in particular, the Mac+. I'm 
: : quite experienced with the 68xxx series cpu's having built expansion 
: : slots and accelerators for Amiga's. Why is Mac hardware info so hard to 
: : find? I would also like to build an accelerator for the Mac+.


Here goes..

First of NuBus is an IEEE/ANSI Standard 1196-1987.

NuBus runs at a transfer rate of 10 MMHz and is a synchronous bus.  It
supports multiple masters and an arbitration scheme that is 'fair'.
It supports only these bus transfers: read, write, block read, block write.
32-bit address space, and Geographic slot addressing.

All signal lines on NuBus are active low signals.

There are two board sizes specified in the NuBus Spec, a "triple-height"
and a "PC-style" board.

I will skip the "triple-height" form factor since you expressed interest
in the Mac.

Looking at the board from the component side:

The board is 4.000 inch high, and 12.858 inch long maximum with a minimum of 
7.00 inch.  There is one C096-style connector (Like those used in VMEbus) at
or centered at (and here I am looking at the mechanical drawing and not
seeing that distance dimensioned, I will find it out).  The PC form factor
board component height limitation is 0.60 inch and lead and component height on
the other side.  The board thickness is defined as 0.063 inch.  No components
may be placed within 0.15 inch of the end of the board engaging the card
guide (furthest from the bus connector).  All card cages using the PC form 
factor place boards on 0.90 inch centers.


-----


Bus Lines:

Power
  There are four voltages defined by the bus specification, +5 VDC, +12 VDC,
-12 VDC, -5.2 VDC.  The maximum current load is not controlled by the 
specification.  The -5.2 VDC power is optional.  If it is not implemented on
a given bus the lines should not be used for anything else.  The tolerance
on all power supplies is +/- 3.0%.  The line and load regulation must be
better than 0.3%.

Utility signals

CLK/    A 10-Mhz, 25% duty cycle signal use to synchronize all data transfers
        and bus arbitration operations.  All bus signals are in transition
        on the rising edge of the clock and sampled on the folling edge.
RESET/  This open collector, active low signal returns all devices on the
        bus to a power-up condition.  It is used to initialize the system
        and may be asserted asynchronously with the CLK/ signal.
PFW/    The power fail warning is an open collector, active low signal used
        to indicate an imminent power failure.  It may be asserted
        asynchronously with CLK/
ID3/ through ID0/
        These four active low, non bussed signals are binary encoded and
        used to indicate a given boards position in the card cage.
NMRQ/   The active low nonmaster request line is used by boards not capable
        of becoming bus masters but which are in need of service.

Data Signals

AD0/ through AD31/
        These 32 tristate, active low address and data lines carry both 
        address and data information.  They are multiplexed so that the
        number of lines may be minimized.  Address information is first 
        broadcast.  The responding slave may then place 8, 16, or 32 bits
        of data on these lines, depending on the type of transfer being 
        performed.
TM0/ TM1/
        These two tristate, active low transfer mode lines are used to indicate
        the type of transfer being performed.  The master initiating the
        transfer indicates the type of transfer to be performed and the
        responding slave indicates the success of the transfer over these lines.
ACK/    The acknowledge signal is active low, tristate line used to indicate
        the completion of the data bus operation.  ACK/ and START/,
        when used together, can signal that attention cycles have occurred
        on the bus.
START/  This active low, tristate signal is driven low to indicate the 
        beginning of a data operation.  
SP/     The active low, tristate system parity line is driven to a state that
        produces even parity on the AD0/ through AD31/ lines. Parity may not
        be implemented on a given system.  The status of the SPV/ line 
        indicates whether this line has significance.
SPV/    This tristate, active low line is used to indicate the validity of
        the SP/ line.  WHen driven low, the SP/ line must also be driven
        to a valid state.

Arbitration lines

RQST/   This open collector, active low line is used to indicate that a bus 
        master requests use of the bus.
ARB0 through ARB3/
        These four open collector, active low lines are used to arbitrate
        amoung multiple masters requesting use of the bus.  They are
        binary encoded.  Each board compares its own binary code with that on
        the ARB0/ through ARB3/ lines.  At the end of an arbitration cycle,
        these lines carry the binary code of the master that will control
        the bus.

--------

Types of cycles and transactions

A bus cycle occurs during the 100-ns period between two consecutive rising
edges of the CLK/ signal.  Note that all signals change on the rising edge
of the clock and are guaranteed stable on the falling edge of the clock.  The
type of bus cycle being performed is determined by the following six lines:

START/
ACK/
TM0/ and TM1/
AD0/ and AD1/

Start cycle  This cycle is signaled by
        START/ = 0
        ACK/   = 1
TM0/ TM1/ AD0/ AD1/ are used as four bits and encode one of 16 possible bus
operations.  Eight are read operations eight are write operations.

Attention cycle  This cycle is signaled by
        START/ = 0
        ACK/   = 0
TM0/ and TM1/ are then used by one of four possible types of attention cycles,
only two of which are currently defined by the NuBus Spec.

Ack Cycle  This cycle is signaled by
        START/ = 1
        ACK/   = 0
TM0/ and TM1/ are used to indicate one of four possible acknowledge codes:
they are:
1. Successful completion of operation
2. Error occurred during operation
3. Bus timeout error occurred
4. Operation postponed

All bus transactions must begin with a start cycle and conclude with an
acknowledge cycle, so they must contain at least two clock periods.

NuBus data transfers
The bus supports 8, 16, and 32bit operations.  Byte 0 is always transfered
one AD0/ through AD7/, byte 1 on AD8/ through AD15/, byte 2 on AD16/ through
AD23/ and byte 3 on AD24/ through AD31/.  Word 0 is always transfered on
AD0/ through AD15/, word 1 on AD16/ through AD31/.  A 32-bit long word
is transfered on AD0/ through AD31/.

The type of data transfer is controled by TM0/ and TM1/ in conjunction with
AD0/ and AD1/.

Transfer types          transfer mode lines             address lines
                        TM1/    TM0/                    AD1/    AD0/
----------------------------------------------------------------------
Write byte 3            0       0                       0       0
write byte 2            0       0                       0       1
write byte 1            0       0                       1       0
write byte 0            0       0                       1       1
write word 1            0       1                       0       0
Block write             0       1                       0       1
write word 0            0       1                       1       0
write long word         0       1                       1       1
read byte 3             1       0                       0       0
read byte 2             1       0                       0       1
read byte 1             1       0                       1       0
read byte 0             1       0                       1       1
read word 1             1       1                       0       0
block read              1       1                       0       1
read word 0             1       1                       1       0
read long word          1       1                       1       1
---------------------------------------------------------------------


transfer response       transfer mode lines
                        TM1/    TM0/
-------------------------------------------------
Normal Completion       0       0
Error                   0       1
Timeout Error           1       0
Device Busy             1       1
------------------------------------------------




If you need more information there is still data on block transfers and
arbitration.  Which I can and will write up also.




P1 connector


Pin Number      Row A           Row B           Row C
------------------------------------------------------------------------------
1               -12 VDC         -12 VDC         RESET/
2               RESERVED        RESERVED        RESERVED
3               SPV/            +5 VDC          +5 VDC
4               SP/             +5 VDC          +5 VDC
5               TM1/            +5 VDC          TM0/
6               AD1/            +5 VDC          AD0/
7               AD3/            -5.2VDC         AD2/
8               AD5/            -5.2VDC         AD4/
9               AD7/            -5.2VDC         AD6/    
10              AD9/            -5.2VDC         AD8/
11              AD11/           GND             AD10/
12              AD13/           GND             AD12/
13              AD15/           GND             AD14/
14              AD17/           GND             AD16/
15              AD19/           GND             AD18/
16              AD21/           GND             AD20/
17              AD23/           GND             AD22/
18              AD25/           GND             AD24/
19              AD27/           GND             AD26/
20              AD29/           GND             AD28/
21              AD31/           GND             AD30/
22              GND             GND             GND
23              GND             GND             PFW/    
24              ARB1/           -5.2VDC         ARB0/
25              ARB3/           -5.2VDC         ARB2/
26              ID1/            -5.2VDC         ID0/
27              ID3/            -5.2VDC         ID2/
28              ACK/            +5 VDC          START/
29              +5 VDC          +5 VDC          +5 VDC
30              ROST/           GND             +5 VDC
31              NMRQ/           GND             GND
32              +12 VDC         +12 VDC         CLK/


------


TI makes or used to make some interface chips for NuBus, I believe they
still do.  If you need more details I can write up or more point you at
some documents that would be of great help.




Hope it helps at least some.


Jonathan Smith


