(from Motorola Semiconductor  Master Selection Guide rev4).

The DSP56000 family of 24-bit fixed-point general purpose
DSPs feature three single-cycle execution units--The Data ALU,
the Address Arithmetic Unit and the Program Controller--Which
operate in parallel at instruction speeds up to 16.5 MHz.
Xdata,Ydata and program data memories are provided 
on-chip and each is expandable off-chip to provide up to
192K words of 24-bit data address space. The on-chip I/O is
flexible,with two serial ports and a parallel Host. The
high throughput of the DSP56000/1 makes them well-suited for 
communication,high-speed control,numeric processing and computer 
and audio applications.
The DSP56001 is a RAM-based version of the 56000.Due to its on-
chip program RAM, the 56001 is available off the shelf for 
immediate implementation.It includes two data Roms containing
MU-Law and A-Law tables and sine-wave generation tables and is 
available in the following speeds.
The DSP56001 (20.5MHz) has a run rate of 10.25 MIPS and
(27MHz) has a run rate of 13.5 and (33MHz) has a run rate
of 16.5 MIPS.

The DSP56001 Benchmarks
Benchmark                            Instruction Cycles
---------                            --------------------
Real FIR Filter                      1 per Tap
With data Shift                    

Two Dimensional Convolution          1 per Output
(3*3 coeff.mask)

LMS Adaptive Real FIR Filter         3 per tap

Real Cascaded IIR Biquad             4 per section
Filter Sections(4 coeff.) 

Complex FIR Filter With Data Shift   4 per tap

1*3 3*3 Matrix Multiplication        17

Division                             28

Leroux-Gueguen LPC Analysis:
8th order                            473
10th order                           622
16th order                           1203

256-point Complex FFT                6613
1024-point Complex FFT               33120


DSP56001 Features:

* 16.5 MIPS 60ns instructions cycle at 33MHz
* 24x24 to 56-bit parallel multiply/accumulate
*Two 56-bit accumulators
*Linear,modulo and bit reversed address generation
*Nested hardware DO loops
*No overhead auto-return(fast)interrupts
*62 MPU-style instruction types
*Suitable for high level language compilers
*On chip MCU-style peripherals
 -24 programmable I/O port pins
 -8-bit parallel host MPU/DMA interface
 -Serial Communications Interface
 -Synchronous Serial (Codec)Interface
*On-chip memory
 -Two independent 256x24bit data RAMs and ROMs
 -512x24-bit program RAM 
*Off-chip Memory
 -128Kx24-bit data memory
 -64Kx24-bit program memory

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