Motorola DSP56ADC16 EVALUATION BOARD Information on Sample Files (From the User Manual) 3.2 SUPPLIED SOFTWARE FOR USE WITH THE DSP56000ADS BOARD Included with the DSP56ADC16 EVB is a floppy disk containing a library of useful routines for using and evaluating the DSP56ADC16. Source code (.ASM extension) is included for exemplary drivers and I/O routines along with the .LOD hex files for loading and execution on the DSP56000ADS board. Additionally, the library contains a .LOD hex file for an FFT spectrum analyzer program for critical analysis of the DSP56ADC16 performance. With this library of programs, a DSP56000ADS system, and the DSP56ADC16 EVB the user has a complete setup for testing, using, and evaluating the DSP56ADC16 oversampling analog- to-digital converter chip. For loading and running programs please refer to the "DSP56000ADS Application Development System User's Manual" supplied with your DSP56000ADS kit. All programs supplied with the DSP56ADC16 EVB start at program memory address p:$0040. To execute the programs simply type the command "go p:$40" on your DSP56000ADS host computer (followed by carriage return)after loading the desired program. To stop the program and return control to the user simply type "force break" (followed by a carriage return). 3.2.1 GENERAL POLLED I/O LOOP (loopevb.asm) File "loopevb.asm" is the assembly language source code for an example driver for the DSP56ADC16 EVB. This particular driver is for simple polled operation. The driver first initializes the DSP56001 SSI peripheral to operate with the DSP56ADC16 and the D/A converter serial interfaces. After initialization the program loops indefinitely by first reading the SSI RX register at $X:FFEF in the DSP56001 and then writing the SSI TX register at $X:FFEF. Analog data appearing on BNC2 and BNC3 is digitized and then converted back to analog and will appear on BNC1. This program serves as an exemplary routine for a polled I/O device driver. This program is also a simple system "quick check" to verify that the DSP56ADC16 EVB and DSP56000ADS are functioning properly. 3.2.2 GENERAL INTERRUPT I/O LOOP (intioevb.asm) File "intioevb.asm" is the assembly language source code for an example driver featuring interrupt service routines for I/O. This routine first initializes the DSP56001 SSI peripheral to operate with interrupts enabled. The routine then sits in a loop jumping to itself, waiting for an SSI interrupt to occur. The user can substitute an application program in place of this jump loop. When an interrupt occurs the interrupt service handler will first read the SSI RX register, which contains digital output from the DSP56ADC16, followed immediately by a write to the SSI TX register to send this data to the D/A converter. In this routine only one interrupt is used, the SSI RX interrupt, because the SSI receiver and transmitter operate synchronously. Therefore, whenever the SSI RX register is full the SSI TX register is guaranteed to be empty. As in the polled routine above, the DSP56ADC16 EVB will pass analog signals from the BNC2/BNC3 jacks to the BNC1 jack in an analog "loop through" fashion. 3.2.3 SIN(X)/X CORRECTION FIR FILTER I/O ROUTINE (sxxevb.asm) The purpose of this routine is to provide a SIN(X)/X correction filter for the zero order hold effect in the D/A converter. This effect causes the D/A converter to look like a lowpass filter with a SIN(X)/X response. This program is an analog "loop through" program like the programs described in 3.2.1 and 3.2.2 above. The incoming signal is digitized by the DSP56ADC16 and then sent through a 50 tap FIR (finite impulse response) filter routine in the DSP56001. The output of the FIR filter is then passed to the D/A converter. The effects of SIN(X)/X droop are most noticeable at frequencies approaching the DSP56ADC16 output sample rate divided by two. The user can learn about zero order hold effects of D/A converters by first observing the system frequency response by using one of the programs previously described and then re- observing the system frequency response while running the SIN(X)/X correction FIR filter described here. 3.2.4 FFT EVALUATION PROGRAM (fftssi.lod) This program is a software "spectrum analyzer". The routine takes in 512 samples from the DSP56ADC16 EVB, applies a Blackman-Harris weighting window to the samples, performs a 512 point fast Fourier transform, converts the output of the transform (complex) to magnitude (scalar), converts the scalar magnitude to log magnitude, and then provides a calibrated serial output of the log spectrum to the D/A for viewing on an attached oscilloscope display. The program repeats this process over 20 times per second to form what appears to be a "real time" power spectral density. This program provides 120 dB of viewable dynamic range as well as calibration reference levels at 0, -60, and -120 dB for calibration of the vertical scale of the displaying oscilloscope. This program and setup are an excellent way of verifying the signal-to-noise (S/N) and signal-to-total harmonic distortion (S/THD) of the DSP56ADC16 conversion system. This spectrum analyzer is capable of revealing any THD in the conversion chain. For example, if additional signal preprocessing circuitry is used "in front" of the DSP56ADC16 it may be checked for S/N or S/THD degradation. This program also allows the designer to verify d.c. offset and overload points of the DSP56ADC16 as well. 3.2.4.1 CONNECTION TO AN OSCILLOSCOPE The log power spectral density generated by fftssi.lod is viewed as a repetitive sweep on an oscilloscope attached to BNC1. The oscilloscope should be set for approximately 1 millisecond/div and the vertical sensitivity should be set to .2 to .5 volts/div. See Figure 2 for setup overview. 3.2.4.2 OPERATION After loading fftssi.lod into the DSP56000ADS type "go p:$40" followed by a carriage return. Set the scope triggering to positive slope with AC coupling. A spectral display should now be present on the oscilloscope screen. Three "tick marks" should be visible on the lefthand side of the scope screen. Use the vernier vertical sensitivity to align these marks at the top, middle, and bottom positions of the screen as shown in Figure 3. 3.3 D.C. OFFSET ADJUSTMENT To trim the d.c. offset of the converter install JP8, run the FFT program described above and calibrate the oscilloscope display with the "tick" marks as described in 3.2.4.2 above. The first data point on the lefthand side of the display is the d.c. term in the FFT. Since this value is actually the LOG of the d.c. component adjustment will become very touchy as the d.c. offset goes to zero. Adjust trimpot R22 to obtain a minimum d.c. value. Keep in mind that a d.c. level of -60 dB corresponds to 1/1000th of full scale input voltage. Using the internal reference of 2.0 volts -60 dB of d.c. corresponds to about 2 millivolts. 3.4 HARMONIC DISTORTION ADJUSTMENT OF A/D CONVERTER Trimpot R21 adjusts the impedance balance between the analog inputs BNC2 and BNC3. A balanced input impedance minimizes THD of the DSP56ADC16 when driven differentially. Recommended procedure for adjustment is to apply a low distortion sine wave to differential inputs BNC2 and BNC3 and run the program "fftssi.lod" as described in 3.2.4. While observing the 2nd and 3rd harmonics of a 5KHz input sinewave adjust R21 for minimum THD. Make the adjustment slowly since the THD null will be at one sharply defined point on the adjustment.