Address Size Description Bits used Read/Write -------+-----+--------------------------------------------+---------- ############## ROM-Spiegelung von $FC0000/$E00000 ################### -------+-----+--------------------------------------------+---------- $000000|long |bei RESET: Initadr. fr SSP |R $000004|long |bei RESET: Initadr. fr PC |R -------+-----+--------------------------------------------+---------- ############## ROM ################################################## -------+-----+--------------------------------------------+---------- $FC0000| |192KB TOS-ROM |R (ST) : | | | $FEFFFF| | | -------+-----+--------------------------------------------+---------- $E00000| |256KB TOS-ROM |R (STE) : | | | $E3FFFF| | | -------+-----+--------------------------------------------+---------- $E00000| |512KB TOS-ROM |R(TT/F030) : | | | $EFFFFF| | | -------+-----+--------------------------------------------+---------- $FA0000| |128KB Cartridge-ROM |R : | | | $FBFFFF| | | -------+-----+--------------------------------------------+---------- ############## RAM ################################################## -------+-----+--------------------------------------------+---------- $000000| |512kB RAM Bank 0 |R/W : | | | $07FFFF| |(bei 256kBit-Chips) | -------+-----+--------------------------------------------+---------- $080000| |512kB RAM Bank 1 |R/W : | | | $0FFFFF| |(bei 256kBit-Chips) | -------+-----+--------------------------------------------+---------- $000000| |2MB RAM Bank 0 |R/W : | | | $1FFFFF| |(bei 1MBit-Chips) | -------+-----+--------------------------------------------+---------- $200000| |2MB RAM Bank 1 |R/W : | | | $3FFFFF| |(bei 1MBit-Chips) | -------+-----+--------------------------------------------+---------- $400000| |2MB RAM Bank 2 |R/W : | | | $5FFFFF| |(bei 1MBit-Chips) nur MEGA-HZ 8MB!)) | -------+-----+--------------------------------------------+---------- $600000| |2MB RAM Bank 3 |R/W : | | | $7FFFFF| |(bei 1MBit-Chips) nur MEGA-HZ 8MB!)) | -------+-----+--------------------------------------------+---------- $400000| |ST-RAM, "dual purpose RAM", 64Bit |R/W (TT) : | | | $DFFFFF| | | -------+-----+--------------------------------------------+---------- ############## MEGABUS ############################################## -------+-----+--------------------------------------------+---------- $C00000| |Adressbereich fr |?? MEGA-ST : | | | $CFFFFF| |Erweiterungskarte | -------+-----+--------------------------------------------+---------- $FF0000| |Adressbereich fr |?? MEGA-ST : | | | $FF7FFF| |Erweiterungskarte | -------+-----+--------------------------------------------+---------- $FFFE00| |Adressbereich fr |?? MEGA-ST : | | | $FFFFFD| |Erweiterungskarte | -------+-----+--------------------------------------------+---------- ############## ADSPEED Configuration registers ###################### -------|-----|--------------------------------------------|---------- $F00000|byte |Switch to 16 Mhz |W $F10000|byte |Switch to 8 Mhz |W $F20000|byte |Turn on high speed ROM option in 16 Mhz |W $F30000|byte |Turn off high speed ROM option |W $F40000|byte |Unknown |W $F50000|byte |Turn off cache while in 16 Mhz |W | | >> Write 0 to an address to set it. << | -------+-----+--------------------------------------------+---------- ############## Falcon030 IDE Controller ############################# -------+-----+--------------------------------------------+---------- $F00000|???? |??? |??? (F030) : | : | : | : : $F0003F|???? |??? |??? (F030) -------+-----+--------------------------------------------+---------- ############## ST MMU Controller #################################### -------+-----+--------------------------------------------+---------- $FF8001|byte |MMU memory configuration BIT 3 2 1 0|R/W(ST)STE) | |Bank 0 | | | || | |00 - 128k (?)------------------------+-+ | || | |01 - 512k ---------------------------+-+ | || | |10 - 2m -----------------------------+-+ | || | |11 - reserved -----------------------+-' | || | |Bank 1 | || | |00 - 128k (?)----------------------------+-+| | |01 - 512k -------------------------------+-+| | |10 - 2m ---------------------------------+-+| | |11 - reserved ---------------------------+-'| -------+-----+--------------------------------------------+---------- ############## Falcon030 Processor Control ########################## -------+-----+--------------------------------------------+---------- $FF8007|byte |Falcon Bus Control BIT . . 5 . . 2 . 0|R/W (F030) | |STe Bus Emulation (0 - on) ------' | || | |Blitter (0 - 8mhz, 1 - 16mhz) ---------' || | |68030 (0 - 8mhz, 1 - 16mhz) ---------------'| -------+-----+--------------------------------------------+---------- ############## SHIFTER Video Controller ############################# -------+-----+--------------------------------------------+---------- $FF8201|byte |Video screen memory position (high byte) |R/W $FF8203|byte |Video screen memory position (mid byte) |R/W $FF820D|byte |Video screen memory position (low byte) |R/W (STE) $FF8205|byte |Video address pointer (high byte) |R $FF8207|byte |Video address pointer (mid byte) |R $FF8209|byte |Video address pointer (low byte) |R $FF820E|word |Offset to next line |R/W (F030) $FF820F|byte |Width of a scanline (width in words-1) |R/W (STE) $FF8210|word |Width of a scanline (width in words) |R/W (F030) $FF8265|byte |Horizontal scroll register (0-15) |R/W (STE) -------+-----+--------------------------------------------+---------- $FF820A|byte |Video synchronization mode BIT 1 0|R/W | | 0 - 60hz, 1 - 50hz -' || | | 0 - internal, 1 - external sync ---'| | +--------------------------------------------+ | |NOTE: On the TT these bits are reversed, and| | |50/60hz is inoperative on the TT! Check what| | |machine you are running on before twiddling| | |with these bits. | -------+-----+--------------------------------------------+---------- | | BIT 11111198 76543210| | | 543210 | | | ST color value .....RRR .GGG.BBB| | |STE/TT Color value ....rRRR gGGGbBBB| $FF8240|word |Video palette register 0 |R/W : | : | : : : : | : $FF825E|word |Video palette register 15 |R/W -------+-----+--------------------------------------------+---------- $FF8260|byte |Shifter resolution BIT 1 0|R/W | |00 320x200x4 bitplanes (16 colors) ------+-+| | |01 640x200x2 bitplanes (4 colors) -------+-+| | |10 640x400x1 bitplane (1 colors) -------+-'| $FF8262|byte |TT Shifter resolution BIT 2 1 0|R/W (TT) | |000 320x200x4 bitplanes (16 colors) --+-+-+| | |001 640x200x2 bitplanes (4 colors) ---+-+-+| | |010 640x400x1 bitplane (2 colors) ---+-+-+| | |100 640x480x4 bitplanes (16 colors) --+-+-+| | |110 1280x960x1 bitplane (1 color) ----+-+-+| | |111 320x480x8 bitplanes (256 colors) -+-+-'| -------+-----+--------------------------------------------+---------- $FF827E|???? |STACY Display Driver |???(STACY) -------+-----+--------------------------------------------+---------- $FF8400|word |TT Palette 0 |R/W (TT) : | : | : : : | : : $FF85FE|word |TT Palette 255 |R/W (TT) -------+-----+--------------------------------------------+---------- ############## Falcon030 VIDEL Video Controller ##################### -------+-----+--------------------------------------------+---------- $FF8006|byte |Monitor Type BIT 1 0|R (F030) | |00 - Monochrome (SM124) -----------------+-+| | |01 - Color (SC1224) ---------------------+-+| | |10 - VGA Color --------------------------+-+| | |11 - Television -------------------------+-'| $FF820E|word |Offset to next line |R/W (F030) $FF8210|word |VWRAP - Linewidth in words |R/W (F030) $FF8266|word |SPSHIFT BIT 1 . 8 . 6 5 4 . . . .|R/W (F030) | | 0 | | | | | | |2-colour mode ---------' | | | | | | |Truecolour mode -----------' | | | | | |Use external hsync ------------' | | | | |Use external vsync --------------' | | | |Bitplane mode ---------------------' | | +--------------------------------------------+ | | Horizontal Control Registers (9bit)| $FF8280|word |HHC - Horizontal Hold Counter |R (F030) $FF8282|word |HHT - Horizontal Hold Timer |R/W (F030) $FF8284|word |HBB - Horizontal Border Begin |R/W (F030) $FF8286|word |HBE - Horizontal Border End |R/W (F030) $FF8288|word |HDB - Horizontal Display Begin |R/W (F030) $FF828A|word |HDE - Horizontal Display End |R/W (F030) $FF828C|word |HSS - Horizontal SS |R/W (F030) $FF828E|word |HFS - Horizontal FS |R/W (F030) $FF8290|word |HEE - Horizontal EE |R/W (F030) | +--------------------------------------------+ | | Vertical Control Registers (10bit)| $FF82A0|word |VFC - Vertcial Frequency Counter |R (F030) $FF82A2|word |VFT - Vertical Frequency Timer |R/W (F030) $FF82A4|word |VBB - Vertical Border Begin |R/W (F030) $FF82A6|word |VBE - Vertical Border End (count 1/2 lines)|R/W (F030) $FF82A8|word |VDB - Vertical Display Begin |R/W (F030) $FF82AA|word |VDE - Vertical Display End |R/W (F030) $FF82AC|word |VSS - Vertical SS |R/W (F030) | +--------------------------------------------+ $FF82C2|word |VCO - Video Control BIT 3 2 1 0|R/W (F030) | |Quarter pixel width (4x pixels) -----' | | || | |Halve pixel width (double pixels) -----' | || | |Skip line (interlace) -------------------' || | |Line doubling -----------------------------'| -------+-----+--------------------------------------------+---------- ############## DMA/WD1772 Disk controller ########################### -------+-----+--------------------------------------------+---------- $FF8600| |Reserved | $FF8602| |Reserved | $FF8604|word |FDC access/sector count |R/W $FF8606|word |DMA mode/status BIT 2 1 0|R | |Condition of FDC DATA REQUEST signal --' | || | |0 - sector count null,1 - not null ------' || | |0 - no error, 1 - DMA error ---------------'| $FF8606|word |DMA mode/status BIT 8 7 6 . 4 3 2 1 .|W | |0 - read FDC/HDC,1 - write ' | | | | | | | | | |0 - HDC access,1 - FDC access' | | | | | | | | |0 - DMA on,1 - no DMA ---------' | | | | | | | |reserved ------------------------' | | | | | | |0 - FDC reg,1 - sector count reg --' | | | | | |0 - FDC access,1 - HDC access -------' | | | | |0 - pin A1 low, 1 - pin A1 high -------' | | | |0 - pin A0 low, 1 - pin A0 high ---------' | $FF8609|byte |DMA base and counter (High byte) |R/W $FF860B|byte |DMA base and counter (Mid byte) |R/W $FF860D|byte |DMA base and counter (Low byte) |R/W -------+-----+--------------------------------------------+---------- ############## TT-SCSI DMA Controller ############################### -------+-----+--------------------------------------------+---------- $FF8701|byte |TT-SCSI-DMA Address Pointer (Highest byte) |R/W (TT) $FF8703|byte |TT-SCSI-DMA Address Pointer (High byte) |R/W (TT) $FF8705|byte |TT-SCSI-DMA Address Pointer (Low byte) |R/W (TT) $FF8707|byte |TT-SCSI-DMA Address Pointer (Lowest byte) |R/W (TT) $FF8709|byte |TT-SCSI-DMA Address Counter (Highest byte) |??? (TT) $FF870B|byte |TT-SCSI-DMA Address Counter (High byte) |??? (TT) $FF870D|byte |TT-SCSI-DMA Address Counter (Low byte) |??? (TT) $FF870F|byte |TT-SCSI-DMA Address Counter (Lowest byte) |??? (TT) $FF8710|???? |TT-SCSI-DMA Continue Data Register High Word|R/W (TT) $FF8712|???? |TT-SCSI-DMA Continue Data Register Low Word |R/W (TT) $FF8714|???? |TT-SCSI-DMA Control register |R/W (TT) -------+-----+--------------------------------------------+---------- ############## TT-SCSI Drive Controller 5380 ######################## -------+-----+--------------------------------------------+---------- $FF8781|byte |Contents of SCSI-Data buses |R/W (TT) $FF8783|byte |Init-Command Register |R/W (TT) $FF8785|byte |Transfer Start Register |R/W (TT) $FF8787|byte |Target-Command Register |R/W (TT) $FF8789|byte |Bus Status Register |R/W (TT) $FF878B|byte |Status Register |R/W (TT) $FF878D|byte |Command Data from SCSI-Bus |R/W (TT) $FF878F|byte |Reset DMA/Parity error/begin DMA transfer |R/W (TT) -------+-----+--------------------------------------------+---------- ############## YM2149 Sound Chip #################################### -------+-----+--------------------------------------------+---------- $FF8800|byte |Read data/Register select |R/W | |Port A (register 14) BIT 7 6 5 4 3 2 1 0| | |frei + | | | | | | || (ST/STE) | |LAN/Serial2 Select + | | | | | | || (TT) | |IDE Drive On/OFF ------------' | | | | | | || (F030) | |Monitor jack GPO pin ----------+ | | | | | || | |Internal Speaker On/Off -------' | | | | | || (F030) | |Centronics strobe ---------------' | | | | || | |RS-232 DTR output -----------------' | | | || | |RS-232 RTS output -------------------' | | || | |Drive select 1 ------------------------' | || | |Drive select 0 --------------------------' || | |Drive side select -------------------------'| | |Port B - (register 15) Parallel port | $FF8802|byte |Write data |W | +--------------------------------------------+ | |Note: PSG Registers are now fixed at these| | |addresses. All other addresses are masked| | |out on the Falcon. Any writes to the shadow| | |registers $8804-$8900 will cause a bus error| -------+-----+--------------------------------------------+---------- ############## DMA Sound System ##################################### -------+-----+--------------------------------------------+---------- $FF8900|byte |Buffer interrupts BIT 3 2 1 0|R/W (F030) | |TimerA-Int at end of record buffer --' | | || | |TimerA-Int at end of replay buffer ----' | || | |MFP-15-Int (I7) at end of record buffer -' || | |MFP-15-Int (I7) at end of replay buffer ---'| -------+-----+--------------------------------------------+---------- $FF8901|byte |DMA Control Register BIT 7 . 5 4 . . 1 0|R/W | |1 - select record register --+ | | | || (F030) | |0 - select replay register --' | | | || (F030) | |Loop record buffer --------------' | | || (F030) | |DMA Record on ---------------------' | || (F030) | |Loop replay buffer ----------------------' || (STE) | |DMA Replay on -----------------------------'| (STE) -------+-----+--------------------------------------------+---------- $FF8903|byte |Frame start address (high byte) |R/W (STE) $FF8905|byte |Frame start address (mid byte) |R/W (STE) $FF8907|byte |Frame start address (low byte) |R/W (STE) $FF8909|byte |Frame address counter (high byte) |R (STE) $FF890B|byte |Frame address counter (mid byte) |R (STE) $FF890D|byte |Frame address counter (low byte) |R (STE) $FF890F|byte |Frame end address (high byte) |R/W (STE) $FF8911|byte |Frame end address (mid byte) |R/W (STE) $FF8913|byte |Frame end address (low byte) |R/W (STE) -------+-----+--------------------------------------------+---------- $FF8920|byte |DMA Track Control BIT 5 4 . . 1 0|R/W (F030) | |00 - Set DAC to Track 0 ---------+-+ | || | |01 - Set DAC to Track 1 ---------+-+ | || | |10 - Set DAC to Track 2 ---------+-+ | || | |11 - Set DAC to Track 3 ---------+-' | || | |00 - Play 1 Track -----------------------+-+| | |01 - Play 2 Tracks ----------------------+-+| | |10 - Play 3 Tracks ----------------------+-+| | |11 - Play 4 Tracks ----------------------+-'| -------+-----+--------------------------------------------+---------- $FF8921|byte |Sound mode control BIT 7 6 . . . . 1 0|R/W (STE) | |0 - Stereo, 1 - Mono --------' | | || | |0 - 8bit ----------------------+ | || | |1 - 16bit (F030 only) ---------' | || (F030) | |Frequency control bits | || | |00 - Off (F030) -------------------------+-+| (F030) | |00 - 6258hz frequency (STE only) --------+-+| | |01 - 12517hz frequency ------------------+-+| | |10 - 25033hz frequency ------------------+-+| | |11 - 50066hz frequency ------------------+-'| | |Samples are always signed. In stereo mode, | | |data is arranged in pairs with high pair the| | |left channel, low pair right channel. Sample| | |length must ALWAYS be even in either mono or| | |stereo mode. | | |Example: 8 bit Stereo : LRLRLRLRLRLR | | | 16 bit Stereo : LLRRLLRRLLRR (F030) | | |2 track 16 bit stereo : LLRRllrrLLRR (F030) | -------+-----+--------------------------------------------+---------- ############## STE Microwire Controller (STE only!) ################# -------+-----+--------------------------------------------+---------- $FF8922|byte |Microwire data register |R/W (STE) $FF8924|byte |Microwire mask register |R/W (STE) | +--------------------------------------------+ | |Volume/tone controller commands(Address %10)| | |Master Volume 10 011 DDDDDD| | |Left Volume 10 101 xDDDDD| | |Right Volume 10 100 xDDDDD| | |Treble 10 010 xxDDDD| | |Bass 10 001 xxDDDD| | |Mixer 10 000 xxxxDD| | +--------------------------------------------+ | |Volume/tone controller values | | |Master Volume : 0-40 (0 -80db, 40=0db)| | |Left/Right Volume : 0-20 (0 80db, 20=0db)| | |Treble/bass : 0-12 (0 -12db, 12 +12db)| | |Mixer : 0-3 (0 -12db, 1 mix PSG)| | | (2 don't mix,3 reserved)| | +--------------------------------------------+ | |Procedure: | | |Set mask register to $7ff | | |Read data register and save original value | | |Write data register | | |Compare data register with original value, | | |repeat until data register returns to | | |original value to ensure data has been sent | | |over the interface. | | +--------------------------------------------+ | |Interrupts: | | |Timer A can be set to interrupt at the end | | |of a frame. Alternatively, the GPI7 (MFP | | |mono detect) can be used to generate | | |interrupts thereby freeing up Timer A. In | | |this case, the active edge $FFFA03 must be | | |set by or-ing the active edge $FFFA03 with | | |the contents of $ff8260 as follows: | | |$FF8260 - 2 (mono) or.b #$80 with edge | | |$FF8260 - 0,1 (colour) and.b #$7f with edge | | |This will generate an interrupt at the START| | |of a frame, instead of at the end as with | | |Timer A. To generate an interrupt at the END| | |of a frame, simply reverse the edge values. | -------+-----+--------------------------------------------+---------- ############## Falcon030 DMA/DSP Controllers ######################## -------+-----+--------------------------------------------+---------- $FF8930|word |Crossbar Source Controller |R/W (F030) | +--------------------------------------------+ | |Source: External Input BIT 3 2 1 0| | |0 - DSP IN, 1 - All others ----------' | | || | |00 - 25.175Mhz clock ------------------+-+ || | |01 - External clock -------------------+-+ || | |10 - 32Mhz clock ----------------------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Source: A/D Convertor BIT 7 6 5 4| | |1 - Connect, 0 - disconnect ---------' | | || | |00 - 25.175Mhz clock ------------------+-+ || | |01 - External clock -------------------+-+ || | |10 - 32Mhz clock (Don't use) ----------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Source: DMA-PLAYBACK BIT 11 10 9 8| | |0 - Handshaking on, dest DSP-REC ---+ | | || | |1 - Destination is not DSP-REC -----' | | || | |00 - 25.175Mhz clock ------------------+-+ || | |01 - External clock -------------------+-+ || | |10 - 32Mhz clock ----------------------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Source: DSP-XMIT Bit 15 14 13 12| | |0 - Tristate and disconnect DSP --+ | | || | | (Only for external SSI use) | | | || | |1 - Connect DSP to multiplexer ---' | | || | |00 - 25.175Mhz clock ----------------+--+ || | |01 - External clock -----------------+--+ || | |10 - 32Mhz clock --------------------+--' || | |0 - Handshake on, 1 - Handshake off -------'| -------+-----+--------------------------------------------+---------- $FF8932|word |Crossbar Destination Controller |R/W (F030) | +--------------------------------------------+ | |Destination: External Output BIT 3 2 1 0| | |0 - DSP out, 1 - All others ---------' | | || | |00 - Source DMA-PLAYBACK --------------+-+ || | |01 - Source DSP-XMIT ------------------+-+ || | |10 - Source External Input ------------+-+ || | |11 - Source A/D Convertor -------------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Destination: D/A Convertor BIT 7 6 5 4| | |1 - Connect, 0 - Disconnect ---------' | | || | |00 - Source DMA-PLAYBACK --------------+-+ || | |01 - Source DSP-XMIT ------------------+-+ || | |10 - Source External Input ------------+-+ || | |11 - Source A/D Convertor -------------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Destination: DMA-Record BIT 11 10 9 8| | |0 - Handshaking on, src DSP-XMIT ---+ | | || | |1 - Source is not DSP-XMIT ---------' | | || | |00 - Source DMA-PLAYBACK --------------+-+ || | |01 - Source DSP-XMIT ------------------+-+ || | |10 - Source External Input ------------+-+ || | |11 - Source A/D Convertor -------------+-' || | |0 - Handshake on, 1 - Handshake off -------'| | +--------------------------------------------+ | |Destination: DSP-RECORD BIT 15 14 13 12| | |0 - Tristate and disconnect DSP --+ | | || | | (Only for external SSI use) | | | || | |1 - Connect DSP to multiplexer ---' | | || | |00 - Source DMA-PLAYBACK ------------+--+ || | |01 - Source DSP-XMIT ----------------+--+ || | |10 - Source External Input ----------+--+ || | |11 - Source A/D Convertor -----------+--' || | |0 - Handshake on, 1 - Handshake off -------'| -------+-----+--------------------------------------------+---------- $FF8934|byte |Frequency Divider External Clock BIT 3 2 1 0|R/W (F030) | |0000 - STE-Compatible mode | | |0001 - 1111 Divide by 256 and then number | -------+-----+--------------------------------------------+---------- $FF8935|byte |Frequency Divider Internal Sync BIT 3 2 1 0|R/W (F030) | |0000 - STE-Compatible mode 1000 - 10927Hz*| | |0001 - 49170Hz 1001 - 9834Hz | | |0010 - 32780Hz 1010 - 8940Hz*| | |0011 - 24585Hz 1011 - 8195Hz | | |0100 - 19668Hz 1100 - 7565Hz*| | |0101 - 16390Hz 1101 - 7024Hz*| | |0110 - 14049Hz* 1110 - 6556Hz*| | |0111 - 12292Hz 1111 - 6146Hz*| | | * - Invalid for CODEC | -------+-----+--------------------------------------------+---------- $FF8936|byte |Record Tracks Select BIT 1 0|R/W (F030) | |00 - Record 1 Track ---------------------+-+| | |01 - Record 2 Tracks --------------------+-+| | |10 - Record 3 Tracks --------------------+-+| | |11 - Record 4 Tracks --------------------+-'| -------+-----+--------------------------------------------+---------- $FF8937|byte |CODEC Input Source from 16bit adder BIT 1 0|R/W (F030) | |Source: Multiplexer ---------------------' || | |Source: A/D Convertor ---------------------'| -------+-----+--------------------------------------------+---------- $FF8938|byte |CODEC ADC-Input for L+R Channel BIT 1 0|R/W (F030) | |0 - Microphone, 1 - Soundchip L R| -------+-----+--------------------------------------------+---------- $FF8939|byte |Channel amplification BIT LLLL RRRR|R/W (F030) | | Amplification is in +1.5dB steps | -------+-----+--------------------------------------------+---------- $FF893A|word |Channel attenuation BIT LLLL RRRR ....|R/W (F030) | | Attenuation is in -1.5dB steps | -------+-----+--------------------------------------------+---------- $FF893C|byte |CODEC-Status BIT 1 0|R/W (F030) | |Left Channel Overflow -------------------' || | |Right Channel Overflow --------------------'| -------+-----+--------------------------------------------+---------- $FF8941|byte |GPx Data Direction BIT 2 1 0|R/W (F030) | |0 - In, 1 - Out -----------------------+-+-'| | | For the GP0-GP2 pins on the DSP connector | -------+-----+--------------------------------------------+---------- $FF8943|byte |GPx Data Port BIT 2 1 0|R/W (F030) -------+-----+--------------------------------------------+---------- ############## TT Clock Chip ######################################## -------+-----+--------------------------------------------+---------- $FF8961|byte |Register select |???? (TT) $FF8963|byte |Data of selected clock chip registers |???? (TT) -------+-----+--------------------------------------------+---------- ############## Blitter (Not present on a TT!) ####################### -------+-----+--------------------------------------------+---------- $FF8A00|word |Halftone-RAM, Word 0 |R/W (Blit) : | : | : : : : | : : $FF8A1E|word |Halftone-RAM, Word 15 |R/W (Blit) $FF8A20|word |Source X Increment (signed,even)|R/W (Blit) $FF8A22|word |Source Y Increment (signed,even)|R/W (Blit) $FF8A24|long |Source Address Register (24 bit,even)|R/W (Blit) $FF8A28|word |Endmask 1 (First write of a line)|R/W (Blit) $FF8A2A|word |Endmask 2 (All other line writes)|R/W (Blit) $FF8A2C|word |Endmask 3 (Last write of a line)|R/W (Blit) $FF8A2E|word |Destination X Increment (signed,even)|R/W (Blit) $FF8A30|word |Destination Y Increment (signed,even)|R/W (Blit) $FF8A32|long |Destination Address Register (24 bit,even)|R/W (Blit) $FF8A36|word |Words per Line in Bit-Block (0=65536)|R/W (Blit) $FF8A38|word |Lines per Bit-Block (0=65536)|R/W (Blit) $FF8A3A|byte |Halftone Operation Register BIT 1 0|R/W (Blit) | |00 - All ones ---------------------------+-+| | |01 - Halftone ---------------------------+-+| | |10 - Source -----------------------------+-+| | |11 - Source AND Halftone ----------------+-'| $FF8A3B|byte |Logical Operation Register BIT 3 2 1 0|R/W (Blit) | |0000 All zeros ----------------------+-+-+-+| | |0001 Source AND destination ---------+-+-+-+| | |0010 Source AND NOT destination -----+-+-+-+| | |0011 Source -------------------------+-+-+-+| | |0100 NOT source AND destination -----+-+-+-+| | |0101 Destination --------------------+-+-+-+| | |0110 Source XOR destination ---------+-+-+-+| | |0111 Source OR destination ----------+-+-+-+| | |1000 NOT source AND NOT destination -+-+-+-+| | |1001 NOT source XOR destination -----+-+-+-+| | |1010 NOT destination ----------------+-+-+-+| | |1011 Source OR NOT destination ------+-+-+-+| | |1100 NOT source ---------------------+-+-+-+| | |1101 NOT source OR destination ------+-+-+-+| | |1110 NOT source OR NOT destination --+-+-+-+| | |1111 All ones -----------------------+-+-+-'| $FF8A3C|byte |Line Number Register BIT 7 6 5 . 3 2 1 0|R/W (Blit) | |BUSY ------------------------' | | | | | || | |0 - Share bus, 1 - Hog bus ----' | | | | || | |SMUDGE mode ---------------------' | | | || | |Halftone line number ----------------+-+-+-'| $FF8A3D|byte |SKEW Register BIT 7 6 . . 3 2 1 0|R/W (Blit) | |Force eXtra Source Read -----' | | | | || | |No Final Source Read ----------' | | | || | |Source skew -------------------------+-+-+-'| -------+-----+--------------------------------------------+---------- ############## SCC-DMA (TT Only!) ################################### -------+-----+--------------------------------------------+---------- $FF8C01|byte |DMA-Address Pointer (Highest Byte) |R/W (TT) $FF8C03|byte |DMA-Address Pointer (High Byte) |R/W (TT) $FF8C05|byte |DMA-Address Pointer (Low Byte) |R/W (TT) $FF8C07|byte |DMA-Address Pointer (Lowest Byte) |R/W (TT) $FF8C09|byte |DMA-Address Counter (Highest-Byte) |R/W (TT) $FF8C0B|byte |DMA-Address Counter (High-Byte) |R/W (TT) $FF8C0D|byte |DMA-Address Counter (Low-Byte) |R/W (TT) $FF8C0F|byte |DMA-Address Counter (Lowest-Byte) |R/W (TT) $FF8C10|byte |Continue Data Register (High-Word) |R/W (TT) $FF8C12|byte |Continue Data register (Low-Word) |R/W (TT) $FF8C14|byte |Control register |R/W (TT) -------+-----+--------------------------------------------+---------- ############## SCC Z8530 SCC (MSTE/TT/F030) ######################### -------+-----+--------------------------------------------+---------- $FF8C81|byte |Channel A - Control-Register |R/W (SCC) $FF8C83|byte |Channel A - Data-Register |R/W (SCC) $FF8C85|byte |Channel B - Control-Register |R/W (SCC) $FF8C87|byte |Channel B - Data-Register |R/W (SCC) -------+-----+--------------------------------------------+---------- ############## MSTE/TT VME Bus ###################################### -------+-----+--------------------------------------------+---------- $FF8E01|byte |VME sys_mask BIT 7 6 5 4 . 2 1 .|R/W (VME) $FF8E03|byte |VME sys_stat BIT 7 6 5 4 . 2 1 .|R/W (VME) | |_SYSFAIL in VMEBUS ----------' | | | | | |program | |MFP ---------------------------' | | | | |autovec | |SCC -----------------------------' | | | |autovec | |VSYNC -----------------------------' | | |program | |HSYNC ---------------------------------' | |program | |System software INT ---------------------' |program | +--------------------------------------------+ | |Reading sys_mask resets pending int-bits in | | |sys_stat, so read sys_stat first. | -------+-----+--------------------------------------------+---------- $FF8E05|byte |VME sys_int BIT 0|R/W (VME) | |Setting bit 0 to 1 forces an INT of level 1 |Vector $64 | |INT must be enabled in sys_mask to use it | -------+-----+--------------------------------------------+---------- $FF8E0D|byte |VME vme_mask BIT 7 6 5 4 3 2 1 .|R/W (VME) $FF8E0F|byte |VME vme_stat BIT 7 6 5 4 3 2 1 .|R/W (VME) | |_IRQ7 from VMEBUS -----------' | | | | | | |program | |_IRQ6 from VMEBUS/MFP ---------' | | | | | |program | |_IRQ5 from VMEBUS/SCC -----------' | | | | |program | |_IRQ4 from VMEBUS -----------------' | | | |program | |_IRQ3 from VMEBUS/soft --------------' | | |prog/autov | |_IRQ2 from VMEBUS ---------------------' | |program | |_IRQ1 from VMEBUS -----------------------' |program | +--------------------------------------------+ | |MFP-int and SCC-int are hardwired to the | | |VME-BUS-ints (or'ed) | | |Reading vme_mask resets pending int-bits in | | |vme_stat, so read vme_stat first. | -------+-----+--------------------------------------------+---------- $FF8E07|byte |VME vme_int BIT 0|R/W (TT) | |Setting bit 0 to 1 forces an INT of level 3 |Vector $6C | |INT must be enabled in vme_mask to use it | -------+-----+--------------------------------------------+---------- $FF8E09|byte |General purpose register - does nothing |R/W (TT) $FF8E0B|byte |General purpose register - does nothing |R/W (TT) -------+-----+--------------------------------------------+---------- ############## Mega STE Cache/Processor Control ##################### -------+-----+--------------------------------------------+---------- $FF8E21|byte |Mega STE Cache/Processor Control |R/W (MSTE) -------+-----+--------------------------------------------+---------- ############## STE Extended Joystick/Lightpen Ports ################# -------+-----+--------------------------------------------+---------- $FF9200|???? |Fire buttons 1-4 |R (STE) $FF9202|???? |Joysticks 1-4 |R (STE) $FF9210|???? |Paddle 0 Position |R (STE) $FF9212|???? |Paddle 1 Position |R (STE) $FF9214|???? |Paddle 2 Position |R (STE) $FF9216|???? |Paddle 3 Position |R (STE) $FF9220|???? |Lightpen X-Position |R (STE) $FF9222|???? |Lightpen Y-Position |R (STE) -------+-----+--------------------------------------------+---------- ############## Falcon VIDEL Palette Registers ####################### -------+-----+--------------------------------------------+---------- | | BIT 33222222 22221111 11111198 76543210| | | 10987654 32109876 543210 | | | RRRRRR.. GGGGGG.. ........ BBBBBB..| $FF9800|long |Palette Register 0 |R/W (F030) : | : | : : : | : : $FF98fc|long |Palette Register 255 |R/W (F030) -------+-----+--------------------------------------------+---------- ############## Falcon DSP Host Interface ############################ -------+-----+--------------------------------------------+---------- $FFA200|byte |Interrupt Ctrl Register BIT 7 6 5 4 3 . 1 0|R/W (F030) X:$FFE9| |INIT bit --------------------' | | | | | || | |00 - Interupt mode (DMA off) --+-+ | | | || | |01 - 24-bit DMA mode ----------+-+ | | | || | |10 - 16-bit DMA mode ----------+-+ | | | || | |11 - 8-bit DMA mode -----------+-' | | | || | |Host Flag 1 -----------------------' | | || | |Host Flag 0 -------------------------' | || | | Host mode Data transfers: | || | | Interrupt mode | || | |00 - No interrupts (Polling) ------------+-+| | |01 - RXDF Request (Interrupt) -----------+-+| | |10 - TXDE Request (Interrupt) -----------+-+| | |11 - RXDF and TXDE Request (Interrupts) -+-+| | | DMA Mode | || | |00 - No DMA -----------------------------+-+| | |01 - DSP to Host Request (RX) -----------+-+| | |10 - Host to DSP Request (TX) -----------+-+| | |11 - Undefined (Illegal) ----------------+-'| $FFA201|byte |Command Vector Register |R/W (F030) X:$FFE9| | BIT 7 . . 4 3 2 1 0| | |Host Command Bit (Handshake)-' | | | | || | |Host Vector (0-31) ----------------+-+-+-+-'| $FFA202|byte |Interrupt Status Reg BIT 7 6 . 4 3 2 1 0|R (F030) X:$FFE8| |ISR Host Request ------------' | | | | | || | |ISR DMA Status ----------------' | | | | || | |Host Flag 3 -----------------------' | | | || | |Host Flag 2 -------------------------' | | || | |ISR Transmitter Ready (TRDY) ----------' | || | |ISR Transmit Data Register Empty (TXDE) -' || | |ISR Receive Data Register Full (RXDF) -----'| $FFA203|byte |Interrupt Vector Register |R/W (F030) $FFA204|byte |Unused | (F030) $FFA205|byte |DSP-Word High |R/W (F030) X:$FFEB| | | $FFA206|byte |DSP-Word Mid |R/W (F030) X:$FFEB| | | $FFA207|byte |DSP-Word Low |R/W (F030) X:$FFEB| | | -------+-----+--------------------------------------------+---------- ############## MFP 68901 - Multi Function Peripheral Chip ########### -------+-----+--------------------------------------------+---------- | |MFP Master Clock is 2.457.600 cycles/second | -------+-----+--------------------------------------------+---------- $FFFA01|byte |Parallel Port Data Register |R/W -------+-----+--------------------------------------------+---------- $FFFA03|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W | |Monochrome monitor detect ---' | | | | | | || | |RS-232 Ring indicator ---------' | | | | | || | |FDC/HDC interrupt ---------------' | | | | || | |Keyboard/MIDI interrupt -----------' | | | || | |Reserved ----------------------------' | | || | |RS-232 CTS (input) --------------------' | || | |RS-232 DCD (input) ----------------------' || | |Centronics busy ---------------------------'| | +--------------------------------------------+ | | When port bits are used for input only: | | |0 - Interrupt on pin high-low conversion | | |1 - Interrupt on pin low-high conversion | -------+-----+--------------------------------------------+---------- $FFFA05|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W | |0 - Pin becomes an input | | |1 - Pin becomes an output | -------+-----+--------------------------------------------+---------- $FFFA07|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W $FFFA0B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W $FFFA0F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W $FFFA13|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W | |MFP Address | | | | | | | || | |$13C GPI7-Monochrome Detect -' | | | | | | || | |$138 RS-232 Ring Detector ---' | | | | | || | |$134 (STE sound) Timer A -----' | | | | || | |$130 Receive buffer full -------' | | | || | |$12C Receive buffer empty ---------' | | || | |$128 Sender buffer empty -----------' | || | |$124 Sender error -------------' || | |$120 (HBL) Timer B ---------------'| | |1 - Enable Interrupt 0 - Disable Interrupt| -------+-----+--------------------------------------------+---------- $FFFA09|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W $FFFA0D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W $FFFA11|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W $FFFA15|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W | |MFP Address | | | | | | | || | |$11C FDC/HDC -' | | | | | | || | |$118 Keyboard/MIDI ---' | | | | | || | |$114 (200hz clock) Timer C -----' | | | | || | |$110 (USART timer) Timer D -------' | | | || | |$10C Blitter done ---------' | | || | |$108 RS-232 CTS - input -----------' | || | |$104 RS-232 DCD - input -------------' || | |$100 Centronics Busy ---------------'| | |1 - Enable Interrupt 0 - Disable Interrupt| -------+-----+--------------------------------------------+---------- $FFFA17|byte |Vector Register BIT 3|R/W | |1 - Software End-of-interrupt mode (Default)| | |0 - Automatic End-of-interrupt mode | -------+-----+--------------------------------------------+---------- $FFFA19|byte |Timer A Control BIT 3 2 1 0|R/W $FFFA1B|byte |Timer B Control BIT 3 2 1 0|R/W | +--------------------------------------------+ | |0000 - Timer stop, no function executed | | |0001 - Delay mode, divide by 4 | | |0010 - : : 10 | | |0011 - : : 16 | | |0100 - : : 50 | | |0101 - : : 64 | | |0110 - : : 100 | | |0111 - Delay mode, divide by 200 | | |1000 - Event count mode | | |1xxx - Pulse extension mode, divide as above| | +--------------------------------------------+ $FFFA1F|byte |Timer A Data |R/W $FFFA21|byte |Timer B Data |R/W -------+-----+--------------------------------------------+---------- $FFFA1D|byte |Timer C & D Control BIT 6 5 4 . 2 1 0|R/W | | Timer Timer| | | C D | | +--------------------------------------------+ | |000 - Timer stop | | |001 - Delay mode, divide by 4 | | |010 - : : 10 | | |011 - : : 16 | | |100 - : : 50 | | |101 - : : 64 | | |110 - : : 100 | | |111 - Delay mode, divide by 200 | | +--------------------------------------------+ $FFFA23|byte |Timer C Data |R/W $FFFA25|byte |Timer D Data |R/W -------+-----+--------------------------------------------+---------- $FFFA27|byte |Sync Character |R/W $FFFA29|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W | |Clock divide (1 - div by 16) ' | | | | | | || | |Word Length 00 - 8 bits -------+-+ | | | | || | | 01 - 7 bits | | | | | | || | | 10 - 6 bits | | | | | | || | | 11 - 5 bits -------+-' | | | | || | |Bits Stop Start Format ------------+-+ | | || | |00 0 0 Synchronous | | | | || | |01 1 1 Asynchronous | | | | || | |10 1 1.5 Asynchronous | | | | || | |11 1 2 Asynchronous ------+-' | | || | |Parity (0 - ignore parity bit) --------' | || | |Parity (0 - odd parity,1 - even) --------' || | |Unused ------------------------------------'| $FFFA2B|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W | |Buffer full -----------------' | | | | | | || | |Overrun error -----------------' | | | | | || | |Parity error --------------------' | | | | || | |Frame error -----------------------' | | | || | |Found - Search/Break detected -------' | | || | |Match/Character in progress -----------' | || | |Synchronous strip enable ----------------' || | |Receiver enable bit -----------------------'| $FFFA2D|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W | |Buffer empty ----------------' | | | | | | || | |Underrun error ----------------' | | | | | || | |Auto turnaround -----------------' | | | | || | |End of transmission ---------------' | | | || | |Break -------------------------------' | | || | |High bit ------------------------------' | || | |Low bit ---------------------------------' || | |Transmitter enable ------------------------'| $FFFA2F|byte |USART data |R/W -------+-----+--------------------------------------------+---------- ############# Floating Point Coprocessor (in MSTE) ################## -------+-----+--------------------------------------------+---------- $FFFA40|???? |FP_stat Response-Register |??? (MSTE) $FFFA42|???? |FP_ctl Control-Register |??? (MSTE) $FFFA44|???? |FP_save Save-Register |??? (MSTE) $FFFA46|???? |FP_restor Restore-Register |??? (MSTE) $FFFA4A|???? |FP_cmd Command-Register |??? (MSTE) $FFFA4E|???? |FP_ccr Condition-Code-Register |??? (MSTE) $FFFA50|???? |FP_op Operanden-Register |??? (MSTE) $FFFA54|???? |FP_selct Register Select |??? (MSTE) $FFFA58|???? |FP_iadr Instruction Address |??? (MSTE) -------+-----+--------------------------------------------+---------- ############## MFP 68901 #2 (MFP2) - TT Only ######################## -------+-----+--------------------------------------------+---------- $FFFA81|byte |Parallel Port Data Register |R/W (TT) -------+-----+--------------------------------------------+---------- $FFFA83|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W (TT) | +--------------------------------------------+ | | When port bits are used for input only: | | |0 - Interrupt on pin high-low conversion | | |1 - Interrupt on pin low-high conversion | -------+-----+--------------------------------------------+---------- $FFFA85|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W (TT) | |0 - Pin becomes an input | | |1 - Pin becomes an output | -------+-----+--------------------------------------------+---------- $FFFA87|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA8B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA8F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA93|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W (TT) | |MFP Address | | | | | | | || | |$17C ------------------------' | | | | | | || | |$178 --------------------------' | | | | | || | |$174 ----------------------------' | | | | || | |$170 ------------------------------' | | | || | |$16C --------------------------------' | | || | |$168 ----------------------------------' | || | |$164 ------------------------------------' || | |$160 --------------------------------------'| | |1 - Enable Interrupt 0 - Disable Interrupt| -------+-----+--------------------------------------------+---------- $FFFA89|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA8D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA91|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W (TT) $FFFA95|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W (TT) | |MFP Address | | | | | | | || | |$15C ------------------------' | | | | | | || | |$158 --------------------------' | | | | | || | |$154 ----------------------------' | | | | || | |$150 ------------------------------' | | | || | |$14C --------------------------------' | | || | |$148 ----------------------------------' | || | |$144 ------------------------------------' || | |$140 --------------------------------------'| | |1 - Enable Interrupt 0 - Disable Interrupt| -------+-----+--------------------------------------------+---------- $FFFA97|byte |Vector Register BIT 3|R/W (TT) | |1 - Software End-of-interrupt mode (Default)| | |0 - Automatic End-of-interrupt mode | -------+-----+--------------------------------------------+---------- $FFFA99|byte |Timer A Control BIT 3 2 1 0|R/W (TT) $FFFA9B|byte |Timer B Control BIT 3 2 1 0|R/W (TT) | +--------------------------------------------+ | |0000 - Timer stop, no function executed | | |0001 - Delay mode, divide by 4 | | |0010 - : : 10 | | |0011 - : : 16 | | |0100 - : : 50 | | |0101 - : : 64 | | |0110 - : : 100 | | |0111 - Delay mode, divide by 200 | | |1000 - Event count mode | | |1xxx - Pulse extension mode, divide as above| | +--------------------------------------------+ $FFFA9F|byte |Timer A Data |R/W (TT) $FFFAA1|byte |Timer B Data |R/W (TT) -------+-----+--------------------------------------------+---------- $FFFA9D|byte |Timer C & D Control BIT 6 5 4 . 2 1 0|R/W (TT) | | Timer Timer| | | C D | | +--------------------------------------------+ | |000 - Timer stop | | |001 - Delay mode, divide by 4 | | |010 - : : 10 | | |011 - : : 16 | | |100 - : : 50 | | |101 - : : 64 | | |110 - : : 100 | | |111 - Delay mode, divide by 200 | | +--------------------------------------------+ $FFFAA3|byte |Timer C Data |R/W (TT) $FFFAA5|byte |Timer D Data |R/W (TT) -------+-----+--------------------------------------------+---------- $FFFAA7|byte |Sync Character |R/W (TT) $FFFAA9|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W (TT) | |Clock divide (1 - div by 16) ' | | | | | | || | |Word Length 00 - 8 bits -------+-+ | | | | || | | 01 - 7 bits | | | | | | || | | 10 - 6 bits | | | | | | || | | 11 - 5 bits -------+-' | | | | || | |Bits Stop Start Format ------------+-+ | | || | |00 0 0 Synchronous | | | | || | |01 1 1 Asynchronous | | | | || | |10 1 1.5 Asynchronous | | | | || | |11 1 2 Asynchronous ------+-' | | || | |Parity (0 - ignore parity bit) --------' | || | |Parity (0 - odd parity,1 - even) --------' || | |Unused ------------------------------------'| $FFFAAB|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W (TT) | |Buffer full -----------------' | | | | | | || | |Overrun error -----------------' | | | | | || | |Parity error --------------------' | | | | || | |Frame error -----------------------' | | | || | |Found - Search/Break detected -------' | | || | |Match/Character in progress -----------' | || | |Synchronous strip enable ----------------' || | |Receiver enable bit -----------------------'| $FFFAAD|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W (TT) | |Buffer empty ----------------' | | | | | | || | |Underrun error ----------------' | | | | | || | |Auto turnaround -----------------' | | | | || | |End of transmission ---------------' | | | || | |Break -------------------------------' | | || | |High bit ------------------------------' | || | |Low bit ---------------------------------' || | |Transmitter enable ------------------------'| $FFFAAF|byte |USART data |R/W (TT) -------+-----+--------------------------------------------+---------- ############## 6850 ACIA I/O Chips ################################## -------+-----+--------------------------------------------+---------- $FFFC00|byte |Keyboard ACIA control |R/W $FFFC02|byte |Keyboard ACIA data |R/W $FFFC04|byte |MIDI ACIA control |R/W $FFFC06|byte |MIDI ACIA data |R/W -------+-----+--------------------------------------------+---------- ############## Realtime Clock ####################################### -------+-----+--------------------------------------------+---------- $FFFC21|byte |s_units |??? $FFFC23|byte |s_tens |??? $FFFC25|byte |m_units |??? $FFFC27|byte |m_tens |??? $FFFC29|byte |h_units |??? $FFFC2B|byte |h_tens |??? $FFFC2D|byte |weekday |??? $FFFC2F|byte |day_units |??? $FFFC31|byte |day_tens |??? $FFFC33|byte |mon_units |??? $FFFC35|byte |mon_tens |??? $FFFC37|byte |yr_units |??? $FFFC39|byte |yr_tens |??? $FFFC3B|byte |cl_mod |??? $FFFC3D|byte |cl_test |??? $FFFC3F|byte |cl_reset |??? -------+-----+--------------------------------------------+---------- Cookie Jar Atari "Official" Cookies Cookie Description -------+------------------------------------------------------------- _CPU | CPU Type (Decimal) (0 - 68000, 40 - 68040) _VDO | Shifter Type 0 - ST, 1 - STE, 2 - TT _SND | Sound Hardware BIT 4 3 2 1 0 | Connection Matrix ----' | | | | | DSP56001 ---------------' | | | | 16 Bit DMA Sound ---------' | | | 8 Bit DMA Sound ------------' | | YM2149 -----------------------' _MCH | Hardware Description High Word + Low word | $00000000 - ST $00010000 - Mega 1/2/4 ST $00020000 - STE | $00030000 - TT $00010010 - MSTE (?) _SWI | State of configuration switches (MSTE/TT only) _FRB | Fast Ram Buffer (TT specific) 64k buffer for ACSI DMA | 0 - no buffers assigned >0 - address of FastRam buffer _FPU | FPU Type High word - hardware Low word - software | 0 - No FPU | 1 - SFP004 or compatible 68881 | 2 - 68881 or 68882 unsure which one 3 - plus SFP004 | 4 - 68881 for sure 5 - plus SFP004 | 6 - 68882 for sure 7 - plus SFP004 | 8 - 68040's internal FPU 9 - plus SFP004 _OOL | Poolfix ID -------+------------------------------------------------------------- 68000 Exception Vector Assignments Vector Number Address Space Assignment ---------------+---------+-------+-------------------------------- 0 |0/$0 |SP |Reset:Initial SSP 1 |4/$4 |SP |Reset:Initial PC Reset vector (0) requires four words, unlike other vectors which only require two words, and is located in the supervisor program space. ---------------+---------+-------+-------------------------------- 2 |8/$8 |SD |Bus Error 3 |12/$C |SD |Address Error 4 |16/$10 |SD |Illegal Instruction 5 |20/$14 |SD |Zero Divide 6 |24/$18 |SD |CHK, CHK2 Instruction 7 |28/$1C |SD |cpTRAPcc, TRAPcc, TRAPV Instruction 8 |32/$20 |SD |Privilege Violation 9 |36/$24 |SD |Trace 10 |40/$28 |SD |Line 1010 Emulator (LineA) 11 |44/$2C |SD |Line 1111 Emulator (LineF) 12 |48/$30 |SD |(Unassigned, Reserved) 13 (68030)|52/$34 |SD |Coprocessor Protocol Violation 14 (68010)|56/$38 |SD |Format Error 15 |60/$3C |SD |Uninitialized Interrupt Vector 16-23 |64/$40 |SD |(Unassigned, Reserved) |95/$5F |SD |- 24 |96/$60 |SD |Spurious Interrupt Spurious interrupt vector is taken when there is a bus error during interrupt processing. ---------------+---------+-------+-------------------------------- 68000 Auto-Vector Interrupt Table ---------------+---------+-------+-------------------------------- 25 |100/$64 |SD |Level 1 Int Autovector (TT VME) 26 |104/$68 |SD |Level 2 Int Autovector (HBL) 27 |108/$6C |SD |Level 3 Int Autovector (TT VME) 28 |112/$70 |SD |Level 4 Int Autovector (VBL) 29 |116/$74 |SD |Level 5 Int Autovector 30 |120/$78 |SD |Level 6 Int Autovector (MFP) 31 |124/$7C |SD |Level 7 Int Autovector ---------------+---------+-------+-------------------------------- 32-47 |128/$80 |SD |Trap Instruction Vectors |191/$BF |SD |(Trap #n = vector number 32+n) ---------------+---------+-------+-------------------------------- Math Coprocessor Vectors (68020 and higher) ---------------+---------+-------+-------------------------------- 48 |192/$C0 |SD |FFCP Branch or Set | | | on Unordered Condition 49 |196/$C4 |SD |FFCP Inexact Result 50 |200/$C8 |SD |FFCP Divide by Zero 51 |204/$CC |SD |FFCP Underflow 52 |208/$D0 |SD |FFCP Operand Error 53 |212/$D4 |SD |FFCP Overflow 54 |216/$D8 |SD |FFCP Signaling NAN 55 |220/$DC |SD |(Unassigned, Reserved) ---------------+---------+-------+-------------------------------- 56 |224/$E0 |SD |MMU Configuration Error 57 |228/$E4 |SD |MC68851, not used by MC68030 58 |232/$E8 |SD |MC68851, not used by MC68030 ---------------+---------+-------+-------------------------------- 59-63 |236/$EC |SD |(Unassigned, Reserved) |255/$FF |SD |- ---------------+---------+-------+-------------------------------- 64-254 |256/$100 |SD |User Defined Interrupt Vectors |1019/$3FB|SD |- 255 |1020/$3FC|SD |DSP-IRQ Vector (F030) ---------------+---------+-------+--------------------------------