CLA : Currently Under Development List
======================================

These are the features either currently being worked on, or pencilled in
for when time allows. They aren't in any particular order.
Feel free to mail me additions (or solutions!!)

1)	VHDL Compiler : The version included at present is very limited, and has
					many of the options disabled at the moment.
	More complex structures & data types will be allowed as time goes on,
	starting with certain elements of behavioural modelling to allow for
	definition of clocked devices (PROCESS statements with sensitivity lists).

2)	Block move.

3)	Colour display configuration dialog (for owners of Falcons/TT or
	Crazy Dots et al cards).

4)	Textual stimulus files (Galaxy .txi format)

5)	Textual output files (Galaxy .txo format)

6)	Synthesisable VHDL output - for those of you lucky enough to own a 
	synthesis tool :) (Synopsis standard?)

7)	Attatch Vector description to blocks - custom components. Once this is
	done, I'll enable the add component option in VECEDIT to allow you to
	create your own (currently all you can do is edit the existing gates).

8)	Hierachy navigator - similar to the one in TransLogic's EASE system.

9)	The Librarian - although the current one is a big improvement on
	what went before, it still needs work.

10)	Text positioning - let you change it to be where you like.

11)	EPLD synthesis - I've worked out how to get simple stuff down to a form
	that should fit in an INTEL 5032/5060/5090 EPLD, 
	Programming details for EPLD's are required here.
	I have enough info to do a 22V10/26V12 & produce a JEDEC fuse map for it, so 
	these will be the first IC to be supported, others will only come when I
	have the fuse maps to do them.

12)	Clock buttons in the word generator - yeah I know they donn't work, this is
	on the current fix it list.

13)	Multi-signal buses. A serious must here. I'd like to keep it elegant though
	so any suggestions on the GUI side of this would be appreciated, so I know
	how to approach it. Perhaps a PopUp with a list of the contents of a bus
	for extracting a single signal......?

14)	SPICE output module.
	SPOUT (SPice OUTput) has been under developement for some 16 months. Not
	by me however, as developement was given over entirely to someone else,
	who has made a very nice job as far as it goes, but still needs about 2
	monthes of actual work to get it into a decent shape.
	I have given up on trying to push the guy into getting on with it, so...
	EMAIL to P.B.Johnson@newcastle.ac.uk to prod him into finishing the bloody
	thing........

15)	Online Help. Only if people want it......actually that applies to most of
	the stuff on this list (except for the synthesis tool, which is a
	priority 'coz I want it for my own use before mid '95).

16) Finite State Machine Designer. This will start off as a seperate program,
	able to 'cartoon' simulate the behaviour of an FSM, and export CLA blocks
	in the same way that the VHDL compiler does. It MAY then become properly
	integrated, or more likely, will run under MultiTOS to provide client-
	server FSM editting (see below).

    NOTE: Well, it didn't quite start off that way after all. The FSM designer
          is currently a stand alone (unintegrated) which allows you to design
          FSM's and output .GEM images of them, AND to output synthesised
          chip design's in PALASM for programming a p22v10 PAL to do the job.
          it's been done like that just 'coz I needed one for my MEng Group
          Design Project. AVAILABLE NOW.

17) Modularisation. This is the big IF. My idea for CLA is to eventually split
	the entire system into seperate programs, running under a client-server
	model. The Schematic editor could act as a base for this, and would start
	up service processes (eg. an FSM editor, or a simulator) as required. This
	would allow a much more flexible system than exists at the moment. Oh well,
	that'll have to wait for MultiTOS to get sorted out, or for MagiX to get
    MiNT compatible Pipes & stuff.

5/12/93, Craig.