SOZOBON make documentation	    this is not a man file!

    sozobon-make version 1.6
    date: oct, 7. 93


    this sozobon-make was made from and by:

    PDMAKE, Atari ST version

    Adapted from mod.sources posting (Volume 7, Issue 71, 1986-12-03)
    by Neil Russell and from Jwahar Bammi's port of Neil Russell's
    original net.sources posting.
    Thanks to both of them, they did most of the work and should
    get all the credit they deserve.
                Ton van Overbeek

This is a public domain 'make' program adapted for use with the Sozobon
C compiler by Tony Andrews. Several new features have been added, and
the default rules are set appropriately for use with the Sozobon compiler.

And now it's my turn. I have fixed a bug with commandline handling, made the
automatic variables work more consistent, and added some features.

		Jerry G. Geiger

Please send all comments, bug reports or wishes to me:

	email:	Internet   jerry@zelator.in-berlin.de
		MAUS	   Jerry Geiger @B


Disclaimer

IN NO EVENT WILL I AND/OR ANY OTHER PARTY WHO MAY MODIFY AND REDISTRIBUTE
THIS 'MAKE' PERMITTED AT END OF FILE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY LOST PROFITS, LOST MONIES, OR OTHER SPECIAL, INCIDENTAL OR
CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE (INCLUDING
BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES
SUSTAINED BY THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH OTHER
PROGRAMS) THE PROGRAM, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY.
---------------------------------------------------------------------------


    make [OPTIONS] [<macro>=<value> ...] [target(s) ...]

You have to keep this order in comandline: first the switches, then macro
assignements and at last the targets!

OPTIONS:
    -		read makefile from stdin
    -c <dir>	chdir to 'dir' before running... (uppercase -C works too)
    -e		let the environment overwrite variables from makefile
    -f <file>	use makefile 'file'
    -i		ignore exit status of commands
                - just execute all commands (may cause trouble)
    -k          keep going on processing makefile after an error
                - much better then -i cause if an error occurs the next
		  target is made, so you can test compiling your source
		  files, and maybe collect all errors (cc!)
    -h		print a help page and exit
    -n		do nothing (pretend to make)
                - make will show you what it would do with your makefile
		  so you can test your makefiles without killing any file
    -p		print all macros & targets
    -q 		question up-to-dateness of target, exit status 1 if not.
    -r		don't not use inbuilt rules
    -s		make silently
    -t		touch files instead of making them
    -v		print version
    -V		print more about version
the switches 
    -m  and -b  are ignored for compatibility

This is not a manual for using make, but you will find the features and
something about them in this file. For a good documentation of make
please use the GNU's make manual (the basic concepts are of course the
same, but it's a more sophisticated make) or the UNIX make documentation.


The features are:

 * Make looks at first for a makefile named 'makefile', if there is none
   specified in the commandline. This file is not searched in any path.
 
 * Make will attempt to use its internal rules if no makefile exists, but
   a target was given on the command line. This means that simple programs
   in a single file can be made without a makefile by typing:

	make file.ttp

   Where 'file.o' or/and 'file.c' is the assumed name of the source file.
   You can specify options for 'cc' too:

	make CFLAGS=-VO LDFLAGS=+L-p LOADLIBS=float file.ttp

   Will work as you may have assumed: the optimizer is run, ld make multiple
   passes over the libraries, and the float.a library gets linked.

 * That above is an example for an implicit rule. 
   If for a target with an extension (!!) no commands are specified, make
   tries to find an implicit rule that matches this target by testing
   possible dependencies. The assumed dependency is added to the target's
   dependency list, if it exists. 
   If not, the extension of the assumed dependancy is compared with the first
   depandancy of the target, if it's the same the matching implicit rule
   will be used for this target. To
   pervent a problem with linking all dependencies (default rule) and
   implicit adding an assumed target, this not added for the default
   target (if there are any dependencies).  So:
	foo.ttp: bar.o x.o y.o
   will run the linker with the commandline:
        cc -o foo.ttp bar.o x.o y.o
   And not add any dependency 'foo.o'. The imlicit rule used is:
	.o.ttp:
		$(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES)
   The implicit rule used for a default target is searched be looking at
   the first dependency's suffix too! Think of this if you specify
   dependencies with different suffixes! For the default target you will
   have to write your own command(s) in this case.

   The implicit rules are always suffix rules. So your targets and
   dependencies must have a suffix form '.SUFFFIXES' if they should be
   made with an implicit rule.
   You can of course define new implicit rules, or overwrite built-in ones.
   Don't forget to add the new suffixes to '.SUFFIXES'!

   If you are not shure what make will do test your makefile with make's
   -n option!
	
 * Make uses the PATH variable/macro to find executables automatically and
   looks for all standard suffixes (.tos, .ttp, .prg). Commands in makefiles
   can be given without pathnames and without any suffix.


 * The environment is read, and macros corresponding to the variables
   found are initialized within make. This means that setting the "PATH"
   env. variable causes make to set the macro "PATH" to the value found
   and use that for command searches as described above.
   With a macro assignement in commandline you can overwrite any macro,
   from makefile and environment, too.

   Macros are normally set in the following order:

   	internal defaults
   	environment variables		EXPORTED
   	makefile assignments
	commandline assignements	EXPORTED

   If the -e option is given on the command line, the environment overrides
   assignments in the makefile and the order becomes:

   	internal defaults
   	makefile assignments
   	environment variables		EXPORTED
	commandline assignements	EXPORTED


 * The syntax for recognizing a macro/variable is:
	   '$(VAR)' or '${VAR}', where 'VAR' is the variable/macro name.
   To define a variable/macro in a makefile write:
	   'MACRONAME = VALUE'
   where the rest of the line gets the value, skipping leading and trailing
   whitespaces. 
   In a commandline you cannot include whitespaces in a macro - an ATARI
   problem !
	   'MACRONAME=VALUE'
   All environment variables will be visible as macros to make.

 * I have built in some directives to handle these macros/variables:
   Directives are tokens with no preceding TAB, and may have arguments,
   seperated with whitespace. There are:
   export
   	Export all macros from makefiles via environment to subsequent
	processes (nested makes, or other child processes).
        this directive works only if no unexport follows; global export 
   export  MACRONAME [MACRONAME ...]
   	Export all specified macros as environment variables, they must not
	exist until this directive is read, a global unexport does not
	affect this directive.
   export MACRONAME = VALUE
   	define a macro and make it exportable

   Exported macros are expanded before putting them into environment! In a
   subsequent make you can use them as macros again.
   
   unexport
   	don't export any macros from any makefile; this is default, an
	resets only a earlier global export directive (from another included
	makefile perhaps); the last export or unexport directive is valid
   unexport MACRONAME  [MACRONAME ...]
   	do not export specified macros, even environment variables or
	commandline assignements are affected; a global export directive
	does not change the macros' status
   unexport MACRONAME  VALUE
   	define a macro and make it private

   override MACRONAME VALUE
   	define a macro and prevent it from being overwritten; subsequent
	assignements to this macro (e.g. from commandline) will not replace
	the current value, but be appended to the end:
	in makefile you typed:
		override CFLAGS = -O
	in commandline you may type:
		CFLAGS=-V
	and $(CFLAGS) will expand to
		"-O -V"
	 

 * To provide better support for nested makefiles, a '-c' option is provided
   to tell make to change its current directory before running. Upper level
   makefiles can invoke make with -c as in following line from a makefile:

   	make -c subdir1 -f sub1.mk install

   In this case, make would 'cd' to 'subdir1' before doing anything.

  * With the include directive I added, the reading of current makefile is
  stopped, all specified files are processed like the default makefile, and
  after that the curent makefile processing is continued.
  Default targets are never taken from an include file!
  	include FILENAME [FILENAME...]
  FILENAME may be a macro, known at this state, and have wildcards.

 * Now this make tries to expand every token containing a wildcard
   character like: '*' or '?' or '[' as a filename. The token is
   replaced by the matching filenames found. It uses FNRexpressions
   as wildcards: '*' '?' '[...]' '[?-?]' '[^...]'

 * There are two special targets with dependencies defined:
	.SUFFIXES: .app .prg .tos .ttp .o .bin .s .c .pas
        .PRECIOUS:
   and there are two with no dependencies recognizing:
        .SILENT:
        .IGNORE:
   The last two set global switches like -i (.IGNORE) and -s (.SILENT).
   Dependencies of .PRECIOUS are not deleted if a command fails, by default
   it has no dependencies.


 * There are now four command prefixes defined, to modify make's commandline
   handling. These perfixes are: [-@][%|!] The last two are ST specific!
   The first one '-' means 'ignore' (sets .IGNORE switch to this single
   command), the second 'silent' (sets .SILENT ...).
   You can additionaly specify another switch - but never before '@' or '-':
   Either '%', which means take this command as an inbuilt one, or '!',
   which means execute this command by passing to a shell. Built in commands
   are 'rm', 'cp' (both working with TOS wildcards) and 'echo'.
   The shell command feature tries first to pass the command to a shell via
   '_SHELL_P' variable. If it is empty make tries to execute '$(SHELL)',
   adding a commandline prefix '$(SHPREFIX)' which is '-c' by default.


 * Now this make knows five automatic variables:
   '$@', '$*', '$<', '$^' and '$?'

   $@	Is the current target of an implicit, or an explicit rule
   	with multiple targets.
	$(@F) is the filename part of $@, and $(@D) the path in $@

   $*	Is the basename of the curent target. This works only if the target
   	has a recognized suffix.
	$(*F) is the filename part of $*, and $(*D) the path in $*

   $<	The name of the first dependency. If the target got it's commands
   	from an implicit rule, this will be the first dependency added by
	this rule.
	$(<F) is the filename part of $<, and $(<D) the path in $<

   $^	The names of all dependencies, with spaces between them. This is
   	useful for linking a file. (See default rules).

   $?	The names of all dependencies that are newer than the target, with
   	spaces between them. This maybe useful in explicit rules when you
	want to work only with the changed files. For example to update an
	archive:
	lib.a: foo.o bar.o win.o lose.o
		ar r lib.a $?

 * Make distinguishes double colon rules from normal rules.
   A double colon rule (e.g. foo:: bar) is executed without looking
   at any dependency's time stamp. You may wish to run a special makeTeX or
   makedvi program to get TeX's or LaTeX's special dependency
   files examined, cause time stamps help very little there.

 * The line continuation character is '\'. Back slashes may appear in
   pathname, but NOT at the end of a line, as it will be taken as a
   continuation backslash, and not as a part of the pathname. This should
   not create any big problem as far as i can see.


 * If a environment variable '$MAKEFILES' exists, it's value is used
   as a list of makefiles to include. The default target is never taken
   from one of these files, but they are read at first. If there are no
   absolut paths specified in the filenames, they are searched in the paths
   of '$INCLUDE' and a directory 'make' in that paths. If there is no
   environment variable '$INCLUDE' '\usr\include,\usr\local\include' is
   assumed. (You should not use these feature for portable makefiles.
   You can define more impizit rules there, e.g. to run TeX with
   makindex and bibTeX, etc.)

   Of course it is better to use the new include directive, cause you 
   can't see $MAKEFILE in your makefile.
   
   
 * The default values of all predefined variables:

	PATH = \bin,\sozobon\bin
	CC = cc
	CFLAGS =
	LDFLAGS =
	LOADLIBES =
	SHPREFIX = -c
	TEX = tex
	TFLAGS =
	LEX = lex
	YACC = yacc
	RM = %rm
		$(RM) remove files

   Atari ST Specific Information:

    ATARI SPECIAL MACROS:

    Since the Atari ST does not have any standard shell, Jwahar built in
    commands for the macros $(RM), $(CP) and $(ECHO) that are useful: 

	CP = %cp
	ECHO = %echo

    These macros expand to the inbuilt commands  '%cp' and '%echo' by
    default.
		%cp  copies one file to another. NO directories 
	      allowed, will only accept two arguments, both of which
              must be files. If the destination file exists, it will
              be overwritten.

		%echo echo's its arguments.

		%rm removes one or more files - wildcards allowed.


 * The default rules should be what you'd expect. To help with running
   'make' from GEM, the PATH macro is initialized by default to something
   reasonable. The complete set of defaults is:

	.SUFFIXES: .app .prg .tos .ttp .o .s .c .y .l .bin .pas .dvi .tex

	.c.o:
		$(CC) -c $(CFLAGS) $<

	.s.o:
		$(CC) -c $(CFLAGS) $<

	.c.s:
		$(CC) -S $(CFLAGS) $<

	.c.prg:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.c.tos:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.c.ttp:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.c.app:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.o.prg:
		$(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES)

	.o.tos:
		$(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES)

	.o.ttp:
		$(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES)

	.o.app:
		$(CC) $(LDFLAGS) -o $@ $^ $(LOADLIBES)

	.s.prg:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.s.tos:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.s.ttp:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.s.app:
		$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< $(LOADLIBES)

	.l.c:
		$(LEX) $(LFLAGS) $<

	.y.c:
		$(YACC) $(YFLAGS) $<

	.tex.dvi:
		$(TEX) $(TFLAGS) $<

	.pas.bin:
		$(PC) -c $(PFLAGS) $<

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BUGS
   make sometimes takes  the default target from an include file. I hope I
   get this fixed soon.


   Handling of intermediate files (remove them if not .PRECIOUS) is not
   implemented, 'cc' handled this till now, and can do it in future, too.

	Jerry G. Geiger		Berlin, oct 93

		adress - see above
 I already mentioned it, if you want a more complex, more sophisticated
 'make', use GNU make! This one should stay small (and faster?).

 --------------------------------------------------------------------------
 --------------------------------------------------------------------------
 from original documenation:

    This program is fully in the Public Domain, and you are encouraged
    to distribute copies of the program. Your comments/criticisms/fixes etc.
    will be very much appreciated. I am however not responsible for any bugs
    and/or correctness of behavior of the program. No part of this
    distribution may be used for commercial gains.

                Send your comments to:

                Ton van Overbeek
                Earn/Bitnet:  tpc862@estec
                     Usenet:  .....!{ucbvax|mcvax}!tpc862%estec.bitnet
                       Arpa:  tpc862%estec.bitnet@wiscvm.wisc.edu
                 CompuServe:  71450,3537

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