/*
 * $Header: DH0:src/omti/dist/src/include/omtihard.h,v 1.1 92/11/25 02:11:11 Barnard Exp $
 *
 */

/*
 * Hardware Definitions
 */

struct OmtiController
{
	UBYTE	odata;
	UBYTE	o_pad_1;
	UBYTE	ostatus;
	UBYTE	o_pad_2;
	UBYTE	oselect;
	UBYTE	o_pad_3;
	UBYTE	omask;
};

/* Basisadresse des Controllers */

#define	omtibase	0xef0641

#define	omtidata	(omtibase+odata)
#define	omtistatus	(omtibase+ostatus)
#define	omtireset	(omtibase+oreset)
#define	omticonfig	(omtibase+oconfig)
#define	omtiselect	(omtibase+oselect)
#define	omtimask	(omtibase+omask)

/* Nummer des verwendeten Interrupts */

#define	IntNum	3

/* Bits in den OMTI-Registern */

/* Status */

#define	B_oIREQ		5	/* 1: Interrupt pending */
#define	B_oDREQ		4	/* 1: DMA-Cycle requested */
#define	B_oBSY		3	/* 1: Controller is selected */
#define	B_oCD		2	/* 1: Command-Bytes / 0: Data-Bytes transferred */
#define	B_oIO		1	/* 1: Transfer Controller -> Host / 0: vice versa */
#define	B_oREQ		0	/* 1: Byte-Transfer requested */

#define	F_oIREQ		(1 << B_oIREQ)
#define	F_oDREQ		(1 << B_oDREQ)
#define	F_oBSY		(1 << B_oBSY)
#define	F_oCD		(1 << B_oCD)
#define	F_oIO		(1 << B_oIO)
#define	F_oREQ		(1 << B_oREQ)

/* Data in Status-State */

#define	B_sCS		1		/* Fehlerstatus der Kommandos */
#define	B_sLUN		5		/* LUN der verwendeten Platte */

#define	F_sCS		(1 << B_sCS)
#define	F_sLUN		(1 << B_sLUN)

#define	LUN0		(0 << sLUN)	/* Bit 5 is 0 */
#define	LUN1		(1 << sLUN)	/* Bit 5 is 1 */
#define	LUNMASK		(1 << sLUN)	/* Bit 5 in Status-Register */

#define	MAXCYL		2047		/* Maximale Zylindernummer des Controllers */