MC680x0 Instruction types: ~~~~~~~~~~~~~~~~~~~~~~~~~ Arithmetic Instructions Logic Instructions Shift and Rotate Instructions Bit Manipulation Instructions Bit Field Manipulation Instructions BCD Instructions Data Transfer Instructions Flow Control Instructions Privileged Instructions 'Exceptions' Instructions CCR related Instructions PMMU control Instructions Multiprocessor Instructions CoProcessor Instructions Arithmetic Instructions ---------------------------------------------------------------------------- ADD ADDA ADDI ADDQ ADDX SUB SUBA SUBI SUBQ SUBX DIVS DIVU MULS MULU CLR CMP CMPA CMPI CMPM CMP2 EXT NEG NEGX NOP ============================================================================ Logic Instructions ---------------------------------------------------------------------------- AND ANDI EOR EORI OR ORI NOT TST Scc ============================================================================ Shift and Rotate Instructions ---------------------------------------------------------------------------- ASL ASR LSL LSR ROL ROR ROXL ROXR SWAP ============================================================================ Bit Manipulation Instructions ---------------------------------------------------------------------------- BCHG BCLR BSET BTST ============================================================================ Bit Field Manipulation Instructions ---------------------------------------------------------------------------- BFCHG BFCLR BFSET BFTST BFEXTS BFEXTU BFFFO BFINS ============================================================================ BCD Instructions ---------------------------------------------------------------------------- ABCD NBCD SBCD PACK UNPK ============================================================================ Data transfer Instructions ---------------------------------------------------------------------------- EXG LEA LINK MOVE MOVEA MOVEM MOVEQ MOVEP PEA UNLK ============================================================================ Flow Control Instructions ---------------------------------------------------------------------------- Bcc DBcc BRA BSR JMP JSR RTD RTR RTS ============================================================================ Privileged Instructions ---------------------------------------------------------------------------- ANDI SR CINV CPUSH EORI SR ORI SR MOVE to SR MOVE from SR MOVE USP MOVEC MOVES RESET RTE STOP ============================================================================ 'Exceptions' Instructions ---------------------------------------------------------------------------- BKPT CHK CHK2 ILLEGAL TRAP TRAPcc TRAPV ============================================================================ CCR related Instructions ---------------------------------------------------------------------------- ANDI CCR EORI CCR ORI CCR MOVE from CCR MOVE to CCR ============================================================================ PMMU control Instructions ---------------------------------------------------------------------------- PFLUSH PFLUSHA PLOADR PLOADW PMOVE PTESTR PTESTW CALLM RTM ============================================================================ Multiprocessor Instructions ---------------------------------------------------------------------------- TAS CAS CAS2 ============================================================================ CoProcessor Instructions ---------------------------------------------------------------------------- cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc ============================================================================ Alphabetical Index ---------------------------------------------------------------------------- ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI CCR ANDI SR ASL ASR Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CALLM CAS CAS2 CHK CHK2 CINV CPUSH CLR CMP CMP2 CMPA CMPI CMPM cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc DBcc DIVS DIVU EOR EORI EORI CCR EORI SR EXG EXT ILLEGAL JMP JSR LEA LINK LSL LSR MOVE MOVEA MOVE from CCR MOVE to CCR MOVE from SR MOVE to SR MOVE from/to USP MOVEC MOVE16 MOVEM MOVEP MOVEQ MOVES MUL NBCD NEG NEGX NOP NOT OR ORI ORI CCR ORI SR PACK PEA PFLUSH PFLUSHA PLOADR PLOADW PMOVE PTESTR PTESTW RESET ROL ROR ROXL ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK ============================================================================ Add Binary Coded Decimal (w/extend) ---------------------------------------------------------------------------- NAME ABCD -- Add binary coded decimal SYNOPSIS ABCD Dy,Dx ABCD -(Ay),-(Ax) Size = (Byte) FUNCTION Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binary coded decimal arithmetic. The operands, which are packed BCD numbers, can be addressed in two different ways: 1. Data register to data register: The operands are contained in the data registers specified in the instruction. 2. Memory to memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction. This operation is a byte operation only. Normally the Z condition code bit is set via programming before the start of an operation. That allows successful tests for zero results upon completion of multiple-precision operations. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|---|---|---|---|---|-----------| | 1 | 1 | 0 | 0 | Rx | 1 | 0 | 0 | 0 | 0 |R/M| Ry | ----------------------------------------------------------------- R/M = 0 -> data register R/M = 1 -> address register Rx: destination register Ry: source register RESULT X - Set the same as the carry bit. N - Undefined Z - Cleared if the result is non-zero. Unchanged otherwise. V - Undefined C - Set if a decimal carry was generated. Cleared otherwise. SEE ALSO ADD ADDI ADDQ ADDX SUB SUBI SUBQ SBCD SUBX ============================================================================ ADD integer ---------------------------------------------------------------------------- NAME ADD -- Add integer SYNOPSIS ADD ,Dn ADD Dn, Size = (Byte, Word, Long) FUNCTION Adds the source operand to the destination operand using binary addition, and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination as well as the operand size. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 1 | REGISTER | OP-MODE | MODE | REGISTER | ----------------------------------------========================= OP-MODE Byte Word Long ~~~~ ~~~~ ~~~~ 000 001 010 (Dn) + () -> Dn 100 101 110 () + (Dn) -> REGISTER One of the 8 data registers If is source, allowed addressing modes are: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An * |001 |No reg. An| | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data |111 | 100 | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- * Word or Long only If is destination, allowed addressing modes are: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- When destination is an Address Register, ADDA instruction is used. RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. SEE ALSO ADDI ADDQ ADDX SUB SUBI SUBQ SUBX ============================================================================ ADD Address ---------------------------------------------------------------------------- NAME ADDA -- Add address SYNOPSIS ADDA ,An Size = (Word, Long) FUNCTION Adds the source operand to the destination address register, and stores the result in the destination address register. The size of the operation may be specified as word or long. The entire destination operand is used regardless of the operation size. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 1 | REGISTER | OP-MODE | MODE | REGISTER | ----------------------------------------========================= OP-MODE Indicates operation lenght: 011->one Word operation: source operand is extended to 32 bits 111->one Long operation REGISTER One of the 8 address registers. is always source, all addressing modes are allowed. --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An |001 |No reg. An| | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data |111 | 100 | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- RESULT None. SEE ALSO ADDQ SUBQ SUBA ============================================================================ ADD Immediate ---------------------------------------------------------------------------- NAME ADDI -- Add immediate SYNOPSIS ADDI #, Size = (Byte, Word, Long) FUNCTION Adds the immediate data to the destination operand, and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size. FORMAT ----------------------------------------========================= |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|-------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | SIZE | MODE | REGISTER | |---------------------------------------------------------------| | 16 BITS DATA (with last Byte) | 8 BITS DATA | |---------------------------------------------------------------| | 32 BITS DATA (included last Word) | ----------------------------------------------------------------- SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the followings: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. SEE ALSO ADD ADDQ ADDX SUB SUBI SUBQ SUBX ============================================================================ ADD 3-bit immediate Quick ---------------------------------------------------------------------------- NAME ADDQ -- Add 3-bit immediate quick SYNOPSIS ADDQ #, Size = (Byte, Word, Long) FUNCTION Adds the immediate value of 1 to 8 to the operand at the destination location. The size of the operation may be specified as byte, word, or long. When adding to address registers, the condition codes are not altered, and the entire destination address register is used regardless of the operation size. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|-----------|-----------| | 0 | 1 | 0 | 1 | DATA | 0 | SIZE | MODE | REGISTER | ----------------------------------------========================= DATA 000 ->represent value 8 001 to 111 ->immediate data from 1 to 7 SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the followings: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An * |001 |No reg. An| | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- * Word or Long only. RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. SEE ALSO ADD ADDI SUB SUBI SUBQ ============================================================================ ADD integer with eXtend ---------------------------------------------------------------------------- NAME ADDX -- Add integer with extend SYNOPSIS ADDX Dy,Dx ADDX -(Ay),-(Ax) Size = (Byte, Word, Long) FUNCTION Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binary coded decimal arithmetic. The operands, which are packed BCD numbers, can be addressed in two different ways: 1. Data register to data register: The operands are contained in the data registers specified in the instruction. 2. Memory to memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction. The size of operation can be specified as byte, word, or long. Normally the Z condition code bit is set via programming before the start of an operation. That allows successful tests for zero results upon completion of multiple-precision operations. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|---|---|---|-----------| | 1 | 1 | 0 | 1 | Rx | 1 | SIZE | 0 | 0 |R/M| Ry | ----------------------------------------------------------------- R/M = 0 -> data register R/M = 1 -> address register Rx: destination register Ry: source register SIZE 00->one Byte operation 01->one Word operation 10->one Long operation RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Cleared if the result is non-zero. Unchanged otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. SEE ALSO ADD ADDI SUB SUBI SUBX ============================================================================ Logical AND ---------------------------------------------------------------------------- NAME AND -- Logical AND SYNOPSIS AND ,Dn AND Dn, Size = (Byte, Word, Long) FUNCTION Performs a bit-wise AND operation with the source operand and the destination operand and stores the result in the destination. The size of ther operation can be specified as byte, word, or long. The contents of an address register may not be used as an operand. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 0 | REGISTER | OP-MODE | MODE | REGISTER | ----------------------------------------========================= OP-MODE Byte Word Long 000 001 010 (Dn)AND()-> Dn 100 101 110 ()AND(Dn)-> REGISTER One of the 8 data registers If is source, allowed addressing modes are: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data |111 | 100 | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- If is destination, allowed addressing modes are: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- AND between two data registers is allowed if you consider the syntax where Dn is at destination's place. If you use this instruction with an immediate data, it does the same as instruction ANDI. RESULT X - Not affected N - Set if the most-significant bit of the result was set. Cleared otherwise. Z - Set if the result was zero. Cleared otherwise. V - Always cleared. C - Always cleared. SEE ALSO ANDI ============================================================================ Logical AND Immediate ---------------------------------------------------------------------------- NAME ANDI -- Logical AND immediate SYNOPSIS ANDI #, Size = (Byte, Word, Long) FUNCTION Performs a bit-wise AND operation with the immediate data and the destination operand and stores the result in the destination. The size of ther operation can be specified as byte, word, or long. The size of the immediate data matches the operation size. FORMAT ----------------------------------------========================= |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|-------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | SIZE | MODE | REGISTER | |---------------------------------------------------------------| | 16 BITS DATA (with last Byte) | 8 BITS DATA | |---------------------------------------------------------------| | 32 BITS DATA (included last Word) | ----------------------------------------------------------------- SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the followings: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- RESULT X - Not affected N - Set if the most-significant bit of the result was set. Cleared otherwise. Z - Set if the result was zero. Cleared otherwise. V - Always cleared. C - Always cleared. SEE ALSO AND ANDI to CCR ANDI to SR ============================================================================ Logical AND Immediate to CCR ---------------------------------------------------------------------------- NAME ANDI to CCR -- Logical AND immediate to condition code register SYNOPSIS ANDI #,CCR Size = (Byte) FUNCTION Performs a bit-wise AND operation with the immediate data and the lower byte of the status register. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | |---|---|---|---|---|---|---|---|-------------------------------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 BITS IMMEDIATE DATA | ----------------------------------------------------------------- RESULT X - Cleared if bit 4 of immed. operand is zero. Unchanged otherwise. N - Cleared if bit 3 of immed. operand is zero. Unchanged otherwise. Z - Cleared if bit 2 of immed. operand is zero. Unchanged otherwise. V - Cleared if bit 1 of immed. operand is zero. Unchanged otherwise. C - Cleared if bit 0 of immed. operand is zero. Unchanged otherwise. SEE ALSO AND ANDI ANDI to SR ============================================================================ Logical AND Immediate to SR (privileged) ---------------------------------------------------------------------------- NAME ANDI to SR -- Logical AND immediate to status register (privileged) SYNOPSIS ANDI #,SR Size = (Word) FUNCTION Performs a bit-wise AND operation with the immediate data and the status register. All implemented bits of the status register are affected. FORMAT ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | |---------------------------------------------------------------| | 16 BITS IMMEDIATE DATA | ----------------------------------------------------------------- RESULT X - Cleared if bit 4 of immed. operand is zero. Unchanged otherwise. N - Cleared if bit 3 of immed. operand is zero. Unchanged otherwise. Z - Cleared if bit 2 of immed. operand is zero. Unchanged otherwise. V - Cleared if bit 1 of immed. operand is zero. Unchanged otherwise. C - Cleared if bit 0 of immed. operand is zero. Unchanged otherwise. SEE ALSO AND ANDI ANDI to CCR ============================================================================ Arithmetic Shift Left and Arithmetic Shift Right ---------------------------------------------------------------------------- NAME ASL, ASR -- Arithmetic shift left and arithmetic shift right SYNOPSIS ASd Dx,Dy ASd #,Dy ASd where d is direction, L or R Size = (Byte, Word, Long) FUNCTION Performs an arithmetic shifting bit operation in the indicated direction, with an immediate data, or with a data register. If you shift address contents, you only can do ONE shift, and your operand is ONE word exclusively. ASL: <-- C <------ OPERAND <--- 0 | | X <---' ASR: --> .---> OPERAND ------> C | T | | | | Ÿ----' Ÿ---> X FORMAT In the case of the shifting of a register: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|---|---|---|-----------| | 1 | 1 | 1 | 0 | NUMBER/ |dr | SIZE |i/r| 0 | 0 | REGISTER | | | | | | REGISTER | | | | | | | ----------------------------------------------------------------- In the case of the shifting of a memory area: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|-----------|-----------| | 1 | 1 | 1 | 0 | 0 | 0 | 0 |dr | 1 | 1 | MODE | REGISTER | ----------------------------------------========================= NUMBER/REGISTER Specifies number of shifting or number of register which contents the number of shifting. If i/r = 0, number of shifting is specified in the instruction as immediate data If i/r = 1, it's specified in the data register. If dr = 0, right shifting If dr = 1, left shifting SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER For a register shifting: Indicates the number of data register on which shifting is applied. For a memory shifting: indicates operand which should be shifted. Only addressing modes relatives to memory are allowed: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| --------------------------------- RESULT X - Set according to the list bit shifted out of the operand. Unaffected for a shift count of zero. N - Set if the most-significant bit of the result is set. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. C - Set according to the list bit shifted out of the operand. Cleared for a shift count of zero. SEE ALSO ROd ROXd ============================================================================ Conditional branch ---------------------------------------------------------------------------- NAME Bcc -- Conditional branch SYNOPSIS Bcc