Tips & Traps With The 68HC05

.Don't use bitset & bitclr instructions to initalise output ports prior
 to setting the DDR register. Only do a write. Read modify write cycles
 don't work on ports configured as inputs because the read reads the pins
 not the latch. This seems to apply to bitset & bitclr.

.The SPI system has a nasty little bug. When polling the SPIF flag
 for a complete transfer a short delay is required before reading
 the transfered byte. This probably only applies to one of the
 clock phase & polarity combinations. Check 1000 transfers before
 deleting the NOPs.

		STA Spdr		; shift in byte
wait		BBC SpiSPIF wait	; wait for tranfer complete
		NOP			; Wait! don't read just yet
		NOP			; thanks Motorola
		LDA Spdr		; ok. now it's ready.

.The interupt system can cause problems for programmers.

.There is no real interupt priority. When any interupt occurs all other
 interupts are masked until the RTI instruction is executed. All interupts
 cause the mask bit to be set. To write code with an interupt priority less
 than the other interupts you clear the mask bit with a CLI instruction.
 Thus you can control the other interupts comeing in over the top by
 using CLI and SEI the same way as in non interupt code.

.Another interupt trap can occur when testing the interupt flags. Lets
 call them event flags (eg SPIF). The event flags get set both if the
 interupt is enabled or disabled. So if you are looking for the cause of
 an interupt. Check that it is enabled before checking the event flag.
 I call them event flags because you can check them & clear them totally
 independant of the interupt system.

.Beware of the interupt flags (event flags). ALWAYS do all the things
 and in the right order to clear the flag prior to returning from
 interupt. Any blooper and you end up with an infinite interupt loop. 
 When enabling interupts, if you don't want to be interupted straight away
 do all the things to clear the interupt (event) flag prior to setting
 the interupt enable bit.