Z80 Control Signals:

  MREQ	(Output, active low)
	Signals that the address on the address bus is a valid memory address.

  RD	(Output, active low)
	Signals that the  Z80 is ready to read from the data bus. Present only
	when the address bus holds a valid address.

  WR	(Output, active low)
	Signals that the  Z80 wants to send data, and is present only when the
	address bus holds a valid address and the data bus valid data.

  M1	(Output, active low)
	Indicates  that  the z80  is  in  Machine Cycle  1  State (Instruction
	fetch.)

  IOREQ (Output, active low)
	Indicates that the address on the address bus (mainly a0 to a7, but a8
	to  a15 are  also used	with some  instructions) is  a valid  I/O port
	address.
	   Normal I/O operations never occur during M1. The combination M1 and
	IORQ is used to acknowlede (INTA) a maskable interrupt.

  RFSH	(Output, active low)
	Indicates that	a0 to a6 hold  an address that can  be used to refresh
	dynamic memories. MREQ appears with RFSH.

  HALT	(Output, active low)
	Indicates  that  the  CPU  has halted  following  a  Halt instruction.
	Meanwhile, the memory refresh continues.

  WAIT	(Input, active low)
	Used  by memory or  I/O to indicate  that the  requested data transfer
	cannot yet take place. The CPU pauses and no memory refresh is done.

  RESET (Input, active low)
	i)  PC, I and R are set to zero.
	ii) Interrupts are disabled. Interrupt Mode 0 is set.

  BUSRQ (Input, active low.)
	At the end of the current machine cycle, z80 sets all bus signals, the
	data-  and the	address bus  to a high	impedance state.  When this is
	done, it sets BUSAK low.

  BUSAK (Output, active low)
	Reply to a BUSRQ. Indicates that the z80 has released the buses.

  NMI	(Input, triggered by a negative edge.)
	Current  instruction finishes.	IFF1 is copied	to IFF2.  IFF1 is then
	reset. PC is set to Hex 0066. The RETI instruction copies IFF2 to IFF1
	and pulls the PC from the stack.

  INT	(Input, active low. Detected only if IFF1 is set.)
	IFF1 and IFF2 are reset. Current instruction finishes. Z80 sets M1 and
	IORQ low and waits.
	   In mode 0, the calling device  is expected to put an instruction on
	the data bus during the next cycle. If the instruction takes more than
	one  byte,  the  remaining  bytes  are	read  one  after  one  without
	incrementing the PC.  The instruction must be a Call or Rst, since the
	PC is not automatically pushed on the stack in mode 0.
	   In mode 1, the  data bus is ignored.  The PC is pushed on the stack
	and then set to Hex 0038.
	   In mode 2, the PC is pushed	on the stack before IORQ goes low. The
	calling device	puts the lower 8  bits of the address of the interrupt
	vector	on the data  bus during the  next cycle. The  upper 8 bits are
	taken from  the I register. PC	is then loaded from the full interrupt
	vector address.
	   IORQ and M1 go back high and the routine is serviced.