===== Parallax PIC16Cxx Assembler v1.6 ===== 1 2 3 0000- DEVICE PIC16C84,HS_OSC,WDT_OFF,PROTECT_OFF 4 5 6 7 ;this is a test source for PicSim (device=16C84) 8 ;the commands are from Microchip, the assembler from parallax 9 ;Copyright 04.02.97 Dirk Düsterberg 10 11 12 13 14 15 0000- 070C START ADDWF 0Ch,0 ; C,DC,Z add w and fileregister to w 16 0001- 078C ADDWF 0Ch,1 ; C,DC,Z add w and fileregister to fileregister 17 18 19 0002- 3973 ANDLW 115 ; Z literal and w to w 20 21 22 0003- 050C ANDWF 0Ch,0 ; Z fileregister and w to w 23 0004- 058C ANDWF 0Ch,1 ; Z fileregister and w to fileregister 24 25 26 0005- 138C BCF 0Ch,7 ; clear bit from fileregister 27 0006- 178C BSF 0Ch,7 ; set bit from fileregister 28 29 30 0007- 1A0C BTFSC 0Ch,4 ; skip next command if bit 0 31 0008- 1E8C BTFSS 0Ch,5 ; skip next command if bit 1 32 33 34 0009- 202E CALL LABEL ; call subroutine 35 36 37 000A- 018C CLRF 0Ch ; Z clear fileregister 38 000B- 0100 CLRW ; Z clear w 39 000C- 0064 CLRWDT ; TO,PD clear watchdogtimer 40 41 42 000D- 090C COMF 0Ch,0 ; Z complement from fileregister to w 43 000E- 098C COMF 0Ch,1 ; Z complement from fileregister to fileregister 44 45 46 000F- 030C DECF 0Ch,0 ; Z count fileregister down to w 47 0010- 038C DECF 0Ch,1 ; Z count fileregister down to fileregister 48 49 50 0011- 0B0C DECFSZ 0Ch,0 ; count fileregister down to w and springe falls 0 51 0012- 0B8C DECFSZ 0Ch,1 ; count fileregister down to fileregister and springe falls 0 52 53 54 0013- 0A0C INCF 0Ch,0 ; Z count fileregister up to w 55 0014- 0A8C INCF 0Ch,1 ; Z count fileregister up to fileregister 56 57 58 0015- 0F0C INCFSZ 0Ch,0 ; count fileregister up to w and springe falls 0 59 0016- 0F8C INCFSZ 0Ch,1 ; count fileregister up to fileregister and springe falls 0 60 61 62 0017- 3873 IORLW 115 ; Z write literal or w in w 63 64 65 0018- 040C IORWF 0Ch,0 ; Z write fileregister or w to w 66 0019- 048C IORWF 0Ch,1 ; Z write fileregister or w to fileregister 67 68 69 001A- 080C MOVF 0Ch,0 ; Z write fileregister to w 70 001B- 088C MOVF 0Ch,1 ; Z write fileregister to fileregister 71 72 73 001C- 3073 MOVLW 115 ; write literal to w 74 75 76 001D- 008C MOVWF 0Ch ; write w to fileregister 77 78 79 001E- 0000 NOP ; no operation 80 81 82 001F- 0062 OPTION ; write w in optionregister 83 84 85 0020- 0D0C RLF 0Ch,0 ; C rotate fileregister left to w 86 0021- 0D8C RLF 0Ch,1 ; C rotate fileregister left to fileregister 87 88 89 0022- 0C0C RRF 0Ch,0 ; C rotate fileregister right to w 90 0023- 0C8C RRF 0Ch,1 ; C rotate fileregister right to fileregister 91 92 93 0024- 0063 SLEEP ; TO,PD do the sleep mode 94 95 96 0025- 020C SUBWF 0Ch,0 ; C,DC,Z substract w from fileregister to w 97 0026- 028C SUBWF 0Ch,1 ; C,DC,Z substract w from fileregister to fileregister 98 99 100 0027- 0E0C SWAPF 0Ch,0 ; swap nibbles from fileregister to w 101 0028- 0E8C SWAPF 0Ch,1 ; swap nibbles from fileregister to fileregister 102 103 104 0029- 0065 TRIS ra ; write w in tristate Register from port b 105 002A- 0066 TRIS rb ; write w in tristate Register from port b 106 107 108 ; XORLW #15 ; Z write literal exclusiv oder w to w 109 110 111 002B- 060C XORWF 0Ch,0 ; Z write w exclusiv oder fileregister to w 112 002C- 068C XORWF 0Ch,1 ; Z write w exclusiv oder fileregister to fileregister 113 114 115 116 002D- 2800 GOTO START 117 118 119 120 121 122 123 124 125 126 127 002E- 3005 0085 LABEL MOV RA,#05h ; write literal to port 128 0030- 30AA 0086 MOV RB,#0aah 129 130 131 0032- 3000 0065 MOV !RA,#0h ; write literal ins tristate register 132 0034- 302D 0066 MOV !RB,#45 133 134 135 0036- 0805 MOV w,RA ; write port to w 136 0037- 0806 MOV w,RB 137 138 139 140 141 0038- 1405 SETB RA.0 ; set bit 0 from Port A 142 0039- 1005 clrb RA.0 ; clear bit 0 from Port A 143 144 145 003A- 3002 0685 XOR RA,#00000010b ; toggle (exclusive or) bit 1 from port A 146 147 003C- 1885 BTFSC RA.1 ; skip next command if not bit 148 149 003D- 347F RETW 127 ; jump back from subroutine and write literal to w 150 003E- 343F RETW 63 ; jump back from subroutine and write literal to w 151 152 153 154 155 156 157 ;indirect file addressing (clear fileregister betwen 0Ch and 1fh) 158 159 160 003F- 300C 0084 mov FSR,#0Ch ;file adress pointer to 10h 161 162 163 0041- 0180 milka clr INDIRECT ;clear the indirect address 164 0042- 0A84 inc FSR ;next register 165 0043- 1E84 sb FSR.5 ;all done ? (FSR >= 20h ?) 166 0044- 2841 jmp milka ;do it 167 168 169 170 171 172 173 174 175 ;Data EEProm access 176 177 0045- 080E 0089 witedat mov EEADR,0eh ;0e is my address 178 179 0047- 080F 0088 mov EEDATA,0fh ;0f is my data 180 181 182 0049- 1683 setb STATUS.5 ;select PAGE1 183 184 004A- 1508 setb EECON1.2 ;set EEPROM write enable 185 186 004B- 3055 0089 mov EECON2,#55h 187 004D- 30AA 0089 mov EECON2,#0AAh 188 189 004F- 1488 setb EECON1.1 ;init a write cycle 190 191 192 193 194 195 0050- 1E08 wait sb EECON1.4 ;wait for write to finish 196 0051- 2850 jmp wait 197 0052- 0188 clr EECON1 ;EEPROM write disable & int accept 198 199 0053- 1283 clrb STATUS.5 ;select PAGE0 200 201 202 203 204 205 0054- 1283 readdat clrb STATUS.5 206 0055- 0089 mov EEADR,W 207 0056- 1683 setb STATUS.5 ;select PAGE1 208 209 0057- 1408 setb EECON1.0 ;EEPROM read 210 0058- 1283 clrb STATUS.5 ;select PAGE0 211 212 0059- 0808 mov w,EEDATA 213 214 005A- 2800 GOTO START 215 ===== Errors: 0 =====