PowerPC 602 Risc Microprocessor

Product Description

The PowerPC 602(tm) microprocessor is a 32-bit implementation of the PowerPC(tm) family of Reduced Instruction Set Computer (RISC) microprocessors. It is intended for use in portable and small form factor uniprocessor applications such as PDAs. It achieves its performance through the concurrent execution of up to two instructions per cycle in its four parallel execution units: the fixed-point unit, floating point unit, branch processing unit, and the load/store unit. The low-power design of the PowerPC 602 microprocessor, and the power management features it incorporates, offer competitive advantages in performance oriented, power-sensitive portable applications.

The PowerPC Architecture(tm) is derived from the IBM Performance Optimized With Enhanced RISC (POWER(tm)) architecture. The PowerPC Architecture shares all the benefits of the POWER Architecture(tm) but is optimized for single-chip implementation. The PowerPC architecture is a major component of the PowerOpen(tm) environment.

The PowerPC Architecture offers a complete range of processor solutions for computing needs from embedded applications through multi-processor mainframe systems. Its unique combination of high performance, wide operating systems applicability, and small die size has resulted in its unprecedented success in the RISC computing market.

Highlights

Power Management Unit

Static low-power design
Dynamic power management
Hardware support for power saving modes
Internal clock multiplier for operation at 2x and 3x of bus clock

Control Unit

Dispatches one instruction per cycle
Supports Superscalar Execution
Branch folding implemented
Retires up to one instruction per cycle

Load/Store Unit

One cycle cache access
Speculative cacheable loads (for no data dependencies)

Integer Unit

One cycle add, subtract, shift, rotate, or compare
Hardware multiply and divide
32 x 32-bit general purpose registers

Floating-Point Unit

IEEE-754 compliant single-precision operations
32 x 32-bit floating point registers

Memory Management Unit

Separate 32-entry instruction and data TLBs
Separate instruction and data BATs - (4 each), offer protection and translation for 128K - 4MB of memory
32 bit PowerPC architecture compliant mode
Additional "protection-only-mode" offers protection of up to 4MB per TLB

Cache Unit

Separate 4K instruction and data caches, 2-way set associative
3-statc coherency protocol
Physically addressed tag and cache arrays
Copy-back data cache
Data coherency in hardware

Bus Interface Unit

General purpose interface for a wide range of system configurations
32-bit address and 64-bit data bus
Time multiplexed address and data bus
Powerful diagnostic and test interfaces through the Common On-Chip Processor (COP) and IEEE 1149.1 (JTAG) interface.

(C) International Business Machines Corporation 1995
Printed in the United States of America 1995 All Rights Reserved
IBM and the I'm logo are registered trademarks and IBM Microelectronics is a trademark of the IBM Corporation.
POWER is a trademark licensed to International Business Machines Corporation. PowerOpen is a trademark of International Business Machines Corporation. PowerPC is a trademark of International Business Machines Corporation. PowerPC Architecture is a trademark of International Business Machines Corporation. PowerPC 602 is a trademark of International Business Machines Corporation.
All performance data contained in this publication was obtained in a specific environment, and is presented as illustration. The results obtained in other operating environments may vary
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE OFFERED IN THIS DOCUMENT