PowerPC 620 RISC Microprocessor

Product Description

The PowerPC 620* RISC microprocessor is the first chip in a new product line of servers and high-end workstations within the PowerPC microprocessor family. It features a high bandwidth memory subsystem ideal for symmetric multiprocessing, transaction processing and numerically intensive computing. It's the first 64-bit implementation of the PowerPC Architecture* supporting both 32/64-bit applications.

The PowerPC 620 microprocessor(tm) has a center frequency of 133 MHz and uses a 5-stage pipeline: fetch, dispatch, execute, complete and writeback. It uses a superscaler design to control six independent execution units: branch, three integer, floating-point and load/store. Branch prediction, instruction prefetching and speculative execution are used to take advantage of multiple execution units. Instructions are dispatched to the execution units in program order, executed out-of-order, and completed in-order to support precise exceptions.

Specifications

-----------------------------------------------------------------
| Technology             | 0.5  m CMOS, four levels of metal    |
|------------------------|--------------------------------------|
| Die Size               | 311mm2  , 17.1 mm x 18.2 mm          |
|------------------------|--------------------------------------|
| Number of Transistors  | -7 million                           |
|                        |                                      |
|------------------------|--------------------------------------|
| Performance            | 225 SPECint92**  , 300 SPECfp92**    |
|                        | @ 133MHz (estimated)                 |
|------------------------|--------------------------------------|
| Supply Voltage         | 3.3V + 0.3V                          |
|------------------------|--------------------------------------|
| Power Dissipation      | 30W @ 133MHz                         |
|------------------------|--------------------------------------|
| Signal I/O             | 482                                  |
|------------------------|--------------------------------------|
| Packaging              | 25 x 25 Ball Grid Array (BGA)        |
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Highlights

L2 Cache Interface:

128-bit CMOS/GTL data interface
Unified instruction and data secondary cache
Direct mapped, physically indexed, physically tagged
Cache capacity configur- able from 1MB to 128MB
Interface clocked at 1, 1/2 or 1/3 the processor clock
ECC protected

Bus Interface:

40-bit address bus, 128-bit data bus with byte parity
Supports 64-bit data bus mode
Split transaction, pipelined snoop bus protocol
Interface clocked at 1/2, 1/3 or 1/4 the processor clock
On-chip phase-lock-loop

Software/System Support:

Performance monitor functions
Power management
IEEE 1149.1 (JTAG) interface and on-chip LSSD
Array built-in self test and on-chip debug support

64-bit Advanced Superscaler Processor:

Fetch and dispatch up to 4 instructions per cycle
Speculative execution past 4 unresolved branches
Register renaming for integer, floating-point registers

Six Execution Units:

Branch unit with 4 reservation stations
3 integer units with 2 reservation stations each
Floating-point unit supporting IEEE-754 single and double precision with 2 reservation stations
Load/store unit with 3 reservation stations

Static/Dynamic Branch Prediction:

Branch prediction in fetch and dispatch stages
256-entry branch target address cache
2048-entry branch history table

Caches:

32KB, 8-way set associative non-blocking data cache
Write-thru or write-back data cache modes
Parity protection on both caches
20-entry, fully associative segment lookaside buffer
16 segment registers for 32-bit mode support
Separate 64-entry, fully associative effective to real address translators for instruction and data
4 instruction, 4 data block address translation registers
Coherent data cache
(4-state MESI protocol)

Memory Management and MP Support:

80-bit virtual, 64-bit effective addressing
128-entry, 2-way set associative shared TLB
20-entry, fully associatve segment lookaside buffer
16 segment registers for 32-bit mode support
Separate 64-entry, fully associative effective to real address translators for instruction and data
4 instruction, 4 data block address translation registers
Coherent data cache (4-state MESI protocol)

L2 Cache Interface:

128-bit CMOS/GTL data interface
Unified instruction and data secondary cache
Direct mapped, physically indexed, physically tagged
Cache capacity configurable from 1MB to 128MB
Interface clocked at 1, 1/2 or 1/3 the processor clock
ECC protected

Bus Interface:

40-bit address bus, 128-bit data bus with byte parity
Supports 64-bit data bus mode
Split transaction, pipelined snoop bus protocol
Interface clocked at 1/2, 1/3 or 1/4 the processor clock
On-chip phase-lock-loop

Software/System Support:

Performance monitor functions
Power management
IEEE 1149.1 (JTA(3) interface and on-chip LSSD
Array built-in self test and on-chip debug support

(C) International Business Machines Corporation 1994
Printed in the United States of America
9/94
All rights reserved.

IBM and the IBM logo are registered trademarks of the IBM Corporation. The following terms are trademarks or registered trademarks of the IBM Corporation: IBM Microelectronics, Total Technology Solutions.
* Indicates a trademark or registered trademark of the International Business Machines Corporation.
**All other product and company names are trademarks or registered trademarks of their respective holders.
Document No. MPR620SFU-01 In this document, the terms "PowerPC 620 microprocessor" and "620" are used to denote the fourth microprocessor of the PowerPC Architecture family.

This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE OFFERED IN THIS DOCU-MENT.
Document No. MPR620SFU-01