PowerPC 604 RISC Microprocessor
100, 120, 133, 150MHz

• 8-instruction buffer
• Dispatches 4 instructions per cycle

• Branch
• 3 integer
• Floating point (IEEE-754 single
  and double precision)
• Load/store

• Speculative execution past 2 unresolved branches
• 16-entry reorder buffer
• 2-entry reservation station per execution unit
• Register renaming on GPR, FPR, and CH

• Branch prediction in fetch, decode and dispatch stages
• 64-entry, fully associative branch target address cache
• 512-entry branch history table

• 16K bytes, 4-way set associative instruction cache
• 16K bytes, 4-way set associative data cache
• Non-blocking, write-thru or copy-back data cache
• Byte parity on both caches
• Software cache disable, locking and invalidate

• 52-bit virtual and 32-bit real addressing 4 instruction,data block address translation registers
• 128-entry, 2-way set associative instruction TLB
• 128-entry, 2-way set associative data TLB

• Coherent cache access (MESI)
• Bus snooping
• Separate data cache tag array

• 32-bit address and 64-bit data buses with byte parity
• 60x bus compatible (split transaction, pipelined)
• An optional mode optimized for fast secondary cache
• Up to 66 MHz bus clock
• On-chip PLL to generate 1x, 1.5x, 2x or 3x processor clockfrom the bus clock

• Performance monitor functions
• Instruction and data address breakpoints
• Nap mode power management
• IEEE 1149.1 (JTAG) interface

Product Description

The PowerPC 604 RISC microprocessor is a 32-bit implementationof the PowerPC ArchitectureTM, and is software and bus compatiblewith thePowerPC 601^TM and PowerPC 603^TM microprocessors. It can sustaina maximum rate of 4 instructions per cycle to provide balancedhigh integer and floating point performance suitable for desktoppersonal computers, workstations and midrange servers.

The PowerPC 604 microprocessor uses a 6-stage pipeline to achieveits high speed design: fetch, decode, dispatch, execute, completionand writeback. It uses a superscalar design to provide six independentexecution units: branch, three integer, floating point and load/store.It also uses dynamic branch prediction techniques to enhance instructionprefetching as well as speculative execution techniques to takeadvantage of the improved instruction prefetching and multipleexecution units. Instructions are executed out-of-order, and arecompleted in-order to support precise exceptions.

Printed in the United States of America

10-95

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The performance information contained in this document are estimates based on various assumptions, including, but not limited to, the characteristics of the systems that the products described in this document are incorporated. Such systems may not be presently available, and IBM makes no commitments to make such systems available in the future. All performance data contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. The information contained in this document (which includes, but is not limited to, the aforementioned performance information) is subject to change without notice.

The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not effect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties.

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