(is)pLSI Development System Plus Release 2.2.11, Nov  2 1995 16:37:23


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
STRATEGY:                       AREA


Design Specification
--------------------

Design:                         isp1m256
Part:                           ispLSI2032-80LJ44


Y1_AS_RESET:                    ON


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          32


Input Pins

    Pin Name                Pin Attribute

        AINC                    LOCK 19
        CLR                     LOCK 21
        DIR                     LOCK 22
        EA15                    LOCK 15
        EA16                    LOCK 16
        EMCE                    LOCK 17
        EMOE                    LOCK 18
        WR                      LOCK 20


Output Pins

    Pin Name                Pin Attribute

        A0                      LOCK 37
        A1                      LOCK 38
        A10                     LOCK 5
        A11                     LOCK 6
        A12                     LOCK 7
        A13                     LOCK 8
        A14                     LOCK 9
        A2                      LOCK 39
        A3                      LOCK 40
        A4                      LOCK 41
        A5                      LOCK 42
        A6                      LOCK 43
        A7                      LOCK 44
        A8                      LOCK 3
        A9                      LOCK 4
        ATDBEN                  LOCK 27
        BUSENB                  LOCK 25
        CS0                     LOCK 29
        CS1                     LOCK 30
        CS2                     LOCK 31
        CS3                     LOCK 32
        EMDBEN                  LOCK 26
        OE                      LOCK 10
        WE                      LOCK 28


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 8
Number of I/Os:                 32
Number of Nets:                 34

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    8
Number of Locked DIs:           0
Number of Locked Outputs:       9
Number of Locked Three-States:  15
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      0


GLB Utilization (Out of 8):	100%
I/O Utilization (Out of 34):	94%
Net Utilization (Out of 66):	51%


Nets with Fanout of  1:         11
Nets with Fanout of  2:         4
Nets with Fanout of  3:         10
Nets with Fanout of  4:         6
Nets with Fanout of  5:         3

Average Fanout per Net:         2.59


GLBs with  3 Input(s):          1
GLBs with  6 Input(s):          1
GLBs with  7 Input(s):          1
GLBs with  8 Input(s):          1
GLBs with  9 Input(s):          2
GLBs with 11 Input(s):          2

Average Inputs per GLB:         8.00


GLBs with  1 Output(s):         1
GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         1
GLBs with  4 Output(s):         5

Average Outputs per GLB:        3.25


Output Enable Nets

    Net Name                Net Fanout

        _BUF_571                15


Post-Route Design Implementation
--------------------------------

Number of GLBs:			8
Number of IOCs:			32
Number of DIs:			0
Number of GLB Levels:		2


GLB glb00, A1

    6 Input(s)
        (glb07.O1, A15, I1), (glb07.O0, A16, I0), (DIR.O, 
        _PIN_DIR, I7), (EA15.O, _PIN_EA15, I4), (EA16.O, 
        _PIN_EA16, I5), (EMCE.O, _PIN_EMCE, I2)
    4 Output(s)
        (_OR_479, O3), (_OR_478, O2), (_OR_477, O1), (_OR_476, O0)
    1 Enable Output
        _BUF_571
    9 Product Term(s)

    Output _OR_479

        6 Input(s)
            A15, A16, _PIN_DIR, _PIN_EA15, _PIN_EA16, _PIN_EMCE
        1 Fanout(s)
            CS3.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_479 = (A15 & A16 & _PIN_DIR
            # !_PIN_DIR & _PIN_EA15 & _PIN_EA16 & !_PIN_EMCE)

    Output _OR_478

        6 Input(s)
            A15, A16, _PIN_DIR, _PIN_EA15, _PIN_EA16, _PIN_EMCE
        1 Fanout(s)
            CS2.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_478 = (A16 & _PIN_DIR & !A15
            # !_PIN_DIR & _PIN_EA16 & !_PIN_EA15 & !_PIN_EMCE)

    Output _OR_477

        6 Input(s)
            A15, A16, _PIN_DIR, _PIN_EA15, _PIN_EA16, _PIN_EMCE
        1 Fanout(s)
            CS1.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_477 = (A15 & _PIN_DIR & !A16
            # !_PIN_DIR & _PIN_EA15 & !_PIN_EA16 & !_PIN_EMCE)

    Output _OR_476

        6 Input(s)
            A15, A16, _PIN_DIR, _PIN_EA15, _PIN_EA16, _PIN_EMCE
        1 Fanout(s)
            CS0.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_476 = (_PIN_DIR & !A15 & !A16
            # !_PIN_DIR & !_PIN_EA15 & !_PIN_EA16 & !_PIN_EMCE)

    Enable Output _BUF_571

        1 Input(s)
            _PIN_DIR
        15 Fanout(s)
            A9.OE0, A8.OE0, A7.OE0, A6.OE0, A5.OE0, A4.OE0, A3.OE0,
            A2.OE0, A1.OE0, A14.OE0, A13.OE0, A12.OE0, A11.OE0, A10.OE0,
            A0.OE0
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_571 = _PIN_DIR


GLB glb01, A2

    3 Input(s)
        (DIR.O, _PIN_DIR, I7), (EMCE.O, _PIN_EMCE, I2), (WR.O, 
        _PIN_WR, I5)
    4 Output(s)
        (_BUF_572_part2, O0), (_AND_482, O3), (_AND_480, O1), 
        (_BUF_572_part1, O2)
    3 Product Term(s)

    Output _BUF_572_part2

        1 Input(s)
            _PIN_DIR
        1 Fanout(s)
            BUSENB.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_572_part2 = (_PIN_DIR)

    Output _AND_482

        2 Input(s)
            _PIN_DIR, _PIN_WR
        1 Fanout(s)
            WE.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_482 = _PIN_DIR & _PIN_WR

    Output _AND_480

        2 Input(s)
            _PIN_DIR, _PIN_EMCE
        1 Fanout(s)
            EMDBEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_480 = !_PIN_DIR & !_PIN_EMCE

    Output _BUF_572_part1

        1 Input(s)
            _PIN_DIR
        1 Fanout(s)
            ATDBEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_572_part1 = (_PIN_DIR)


GLB glb02, A4

    11 Input(s)
        (glb05.O0, A0_Q, I12), (glb04.O1, A1_Q, I10), (glb04.O2, 
        A2_Q, I9), (glb04.O3, A3_Q, I8), (glb04.O0, A4_Q, I11), 
        (glb02.O1, A5_Q, I16), (glb02.O2, A6_Q, I13), (glb02.O3, 
        A7_Q, I17), (glb02.O0, A8_Q, I15), (AINC.O, _PIN_AINC, I0), 
        (CLR.O, _PIN_CLR, I2)
    4 Output(s)
        (A8_Q, O0), (A7_Q, O3), (A6_Q, O2), (A5_Q, O1)
    10 Product Term(s)

    Output A8_Q

        11 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, A5_Q, A6_Q, A7_Q, A8_Q,
            _PIN_AINC, _PIN_CLR
        3 Fanout(s)
            glb06.I0, glb02.I15, A8.IR
        2 Product Term(s)
        1 GLB Level(s)

        A8_Q.D = (A8_Q)
            $ A0_Q & A1_Q & A2_Q & A3_Q & A4_Q & A5_Q & A6_Q & A7_Q
        A8_Q.C = _PIN_AINC
        A8_Q.R = !_PIN_CLR

    Output A7_Q

        10 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, A5_Q, A6_Q, A7_Q, _PIN_AINC,
            _PIN_CLR
        3 Fanout(s)
            glb06.I7, glb02.I17, A7.IR
        2 Product Term(s)
        1 GLB Level(s)

        A7_Q.D = (A7_Q)
            $ A0_Q & A1_Q & A2_Q & A3_Q & A4_Q & A5_Q & A6_Q
        A7_Q.C = _PIN_AINC
        A7_Q.R = !_PIN_CLR

    Output A6_Q

        9 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, A5_Q, A6_Q, _PIN_AINC,
            _PIN_CLR
        3 Fanout(s)
            glb06.I2, glb02.I13, A6.IR
        2 Product Term(s)
        1 GLB Level(s)

        A6_Q.D = (A6_Q)
            $ A0_Q & A1_Q & A2_Q & A3_Q & A4_Q & A5_Q
        A6_Q.C = _PIN_AINC
        A6_Q.R = !_PIN_CLR

    Output A5_Q

        8 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, A5_Q, _PIN_AINC, _PIN_CLR
        3 Fanout(s)
            glb06.I1, glb02.I16, A5.IR
        2 Product Term(s)
        1 GLB Level(s)

        A5_Q.D = (A5_Q)
            $ A0_Q & A1_Q & A2_Q & A3_Q & A4_Q
        A5_Q.C = _PIN_AINC
        A5_Q.R = !_PIN_CLR


GLB glb03, A7

    9 Input(s)
        (glb05.O2, A10_Q, I14), (glb03.O3, A11_Q, I4), (glb03.O0, 
        A12_Q, I16), (glb03.O1, A13_Q, I17), (glb03.O2, A14_Q, I5), 
        (glb05.O1, A9_Q, I13), (AINC.O, _PIN_AINC, I11), (CLR.O, 
        _PIN_CLR, I9), (glb06.O0, _AND_450, I7)
    4 Output(s)
        (A14_Q, O2), (A13_Q, O1), (A12_Q, O0), (A11_Q, O3)
    12 Product Term(s)

    Output A14_Q

        9 Input(s)
            A10_Q, A11_Q, A12_Q, A13_Q, A14_Q, A9_Q, _PIN_AINC, _PIN_CLR,
            _AND_450
        3 Fanout(s)
            glb07.I10, glb03.I5, A14.IR
        2 Product Term(s)
        2 GLB Level(s)

        A14_Q.D = (A14_Q)
            $ A10_Q & A11_Q & A12_Q & A13_Q & A9_Q & _AND_450
        A14_Q.C = _PIN_AINC
        A14_Q.R = !_PIN_CLR

    Output A13_Q

        8 Input(s)
            A10_Q, A11_Q, A12_Q, A13_Q, A9_Q, _PIN_AINC, _PIN_CLR,
            _AND_450
        3 Fanout(s)
            glb07.I9, glb03.I17, A13.IR
        2 Product Term(s)
        2 GLB Level(s)

        A13_Q.D = (A13_Q)
            $ A10_Q & A11_Q & A12_Q & A9_Q & _AND_450
        A13_Q.C = _PIN_AINC
        A13_Q.R = !_PIN_CLR

    Output A12_Q

        7 Input(s)
            A10_Q, A11_Q, A12_Q, A9_Q, _PIN_AINC, _PIN_CLR, _AND_450
        3 Fanout(s)
            glb07.I8, glb03.I16, A12.IR
        2 Product Term(s)
        2 GLB Level(s)

        A12_Q.D = (A12_Q)
            $ A10_Q & A11_Q & A9_Q & _AND_450
        A12_Q.C = _PIN_AINC
        A12_Q.R = !_PIN_CLR

    Output A11_Q

        6 Input(s)
            A10_Q, A11_Q, A9_Q, _PIN_AINC, _PIN_CLR, _AND_450
        3 Fanout(s)
            glb07.I11, glb03.I4, A11.IR
        4 Product Term(s)
        2 GLB Level(s)

        A11_Q.D = (A11_Q & !A10_Q
            # A11_Q & !A9_Q
            # A11_Q & !_AND_450
            # A10_Q & A9_Q & _AND_450 & !A11_Q)
        A11_Q.C = _PIN_AINC
        A11_Q.R = !_PIN_CLR


GLB glb04, A5

    7 Input(s)
        (glb05.O0, A0_Q, I12), (glb04.O1, A1_Q, I10), (glb04.O2, 
        A2_Q, I17), (glb04.O3, A3_Q, I8), (glb04.O0, A4_Q, I16), 
        (AINC.O, _PIN_AINC, I11), (CLR.O, _PIN_CLR, I9)
    4 Output(s)
        (A4_Q, O0), (A3_Q, O3), (A2_Q, O2), (A1_Q, O1)
    13 Product Term(s)

    Output A4_Q

        7 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, _PIN_AINC, _PIN_CLR
        4 Fanout(s)
            glb06.I4, glb02.I11, glb04.I16, A4.IR
        2 Product Term(s)
        1 GLB Level(s)

        A4_Q.D = (A4_Q)
            $ A0_Q & A1_Q & A2_Q & A3_Q
        A4_Q.C = _PIN_AINC
        A4_Q.R = !_PIN_CLR

    Output A3_Q

        6 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, _PIN_AINC, _PIN_CLR
        4 Fanout(s)
            glb06.I12, glb02.I8, glb04.I8, A3.IR
        4 Product Term(s)
        1 GLB Level(s)

        A3_Q.D = (!A0_Q & A3_Q
            # A3_Q & !A1_Q
            # A3_Q & !A2_Q
            # A0_Q & A1_Q & A2_Q & !A3_Q)
        A3_Q.C = _PIN_AINC
        A3_Q.R = !_PIN_CLR

    Output A2_Q

        5 Input(s)
            A0_Q, A1_Q, A2_Q, _PIN_AINC, _PIN_CLR
        4 Fanout(s)
            glb06.I6, glb02.I9, glb04.I17, A2.IR
        3 Product Term(s)
        1 GLB Level(s)

        A2_Q.D = (!A0_Q & A2_Q
            # A2_Q & !A1_Q
            # A0_Q & A1_Q & !A2_Q)
        A2_Q.C = _PIN_AINC
        A2_Q.R = !_PIN_CLR

    Output A1_Q

        4 Input(s)
            A0_Q, A1_Q, _PIN_AINC, _PIN_CLR
        4 Fanout(s)
            glb06.I5, glb02.I10, glb04.I10, A1.IR
        2 Product Term(s)
        1 GLB Level(s)

        A1_Q.D = (!A0_Q & A1_Q
            # A0_Q & !A1_Q)
        A1_Q.C = _PIN_AINC
        A1_Q.R = !_PIN_CLR


GLB glb05, A6

    8 Input(s)
        (glb05.O0, A0_Q, I16), (glb05.O2, A10_Q, I14), (glb05.O1, 
        A9_Q, I13), (AINC.O, _PIN_AINC, I11), (CLR.O, _PIN_CLR, I9), 
        (DIR.O, _PIN_DIR, I8), (EMOE.O, _PIN_EMOE, I12), (glb06.O0, 
        _AND_450, I7)
    4 Output(s)
        (_AND_481, O3), (A9_Q, O1), (A10_Q, O2), (A0_Q, O0)
    9 Product Term(s)

    Output _AND_481

        2 Input(s)
            _PIN_DIR, _PIN_EMOE
        1 Fanout(s)
            OE.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_481 = !_PIN_DIR & !_PIN_EMOE

    Output A9_Q

        4 Input(s)
            A9_Q, _PIN_AINC, _PIN_CLR, _AND_450
        4 Fanout(s)
            glb07.I2, glb05.I13, glb03.I13, A9.IR
        2 Product Term(s)
        2 GLB Level(s)

        A9_Q.D = (_AND_450 & !A9_Q
            # A9_Q & !_AND_450)
        A9_Q.C = _PIN_AINC
        A9_Q.R = !_PIN_CLR

    Output A10_Q

        5 Input(s)
            A10_Q, A9_Q, _PIN_AINC, _PIN_CLR, _AND_450
        4 Fanout(s)
            glb07.I1, glb05.I14, glb03.I14, A10.IR
        3 Product Term(s)
        2 GLB Level(s)

        A10_Q.D = (A10_Q & !A9_Q
            # A10_Q & !_AND_450
            # A9_Q & _AND_450 & !A10_Q)
        A10_Q.C = _PIN_AINC
        A10_Q.R = !_PIN_CLR

    Output A0_Q

        3 Input(s)
            A0_Q, _PIN_AINC, _PIN_CLR
        5 Fanout(s)
            glb06.I3, glb02.I12, glb04.I12, glb05.I16, A0.IR
        1 Product Term(s)
        1 GLB Level(s)

        A0_Q.D = !A0_Q
        A0_Q.C = _PIN_AINC
        A0_Q.R = !_PIN_CLR


GLB glb06, A3

    9 Input(s)
        (glb05.O0, A0_Q, I3), (glb04.O1, A1_Q, I5), (glb04.O2, 
        A2_Q, I6), (glb04.O3, A3_Q, I12), (glb04.O0, A4_Q, I4), 
        (glb02.O1, A5_Q, I1), (glb02.O2, A6_Q, I2), (glb02.O3, 
        A7_Q, I7), (glb02.O0, A8_Q, I0)
    1 Output(s)
        (_AND_450, O0)
    1 Product Term(s)

    Output _AND_450

        9 Input(s)
            A0_Q, A1_Q, A2_Q, A3_Q, A4_Q, A5_Q, A6_Q, A7_Q, A8_Q
        3 Fanout(s)
            glb07.I12, glb05.I7, glb03.I7
        1 Product Term(s)
        1 GLB Level(s)

        _AND_450 = A0_Q & A1_Q & A2_Q & A3_Q & A4_Q & A5_Q & A6_Q & A7_Q
            & A8_Q


GLB glb07, A0

    11 Input(s)
        (glb05.O2, A10_Q, I1), (glb03.O3, A11_Q, I11), (glb03.O0, 
        A12_Q, I8), (glb03.O1, A13_Q, I9), (glb03.O2, A14_Q, I10), 
        (glb07.O1, A15, I17), (glb07.O0, A16, I16), (glb05.O1, 
        A9_Q, I2), (AINC.O, _PIN_AINC, I4), (CLR.O, _PIN_CLR, I6), 
        (glb06.O0, _AND_450, I12)
    2 Output(s)
        (A16, O0), (A15, O1)
    6 Product Term(s)

    Output A16

        11 Input(s)
            A10_Q, A11_Q, A12_Q, A13_Q, A14_Q, A15, A16, A9_Q, _PIN_AINC,
            _PIN_CLR, _AND_450
        2 Fanout(s)
            glb07.I16, glb00.I0
        2 Product Term(s)
        2 GLB Level(s)

        A16.D = (A16)
            $ A10_Q & A11_Q & A12_Q & A13_Q & A14_Q & A15 & A9_Q
            & _AND_450
        A16.C = _PIN_AINC
        A16.R = !_PIN_CLR

    Output A15

        10 Input(s)
            A10_Q, A11_Q, A12_Q, A13_Q, A14_Q, A15, A9_Q, _PIN_AINC,
            _PIN_CLR, _AND_450
        2 Fanout(s)
            glb07.I17, glb00.I1
        2 Product Term(s)
        2 GLB Level(s)

        A15.D = (A15)
            $ A10_Q & A11_Q & A12_Q & A13_Q & A14_Q & A9_Q & _AND_450
        A15.C = _PIN_AINC
        A15.R = !_PIN_CLR


Three-State Output A0, IO16

    Input (glb05.O0, A0_Q)
    Enable (glb00.OE, _BUF_571)

    A0 = A0_Q
    A0.E = _BUF_571


Three-State Output A1, IO17

    Input (glb04.O1, A1_Q)
    Enable (glb00.OE, _BUF_571)

    A1 = A1_Q
    A1.E = _BUF_571


Three-State Output A10, IO26

    Input (glb05.O2, A10_Q)
    Enable (glb00.OE, _BUF_571)

    A10 = A10_Q
    A10.E = _BUF_571


Three-State Output A11, IO27

    Input (glb03.O3, A11_Q)
    Enable (glb00.OE, _BUF_571)

    A11 = A11_Q
    A11.E = _BUF_571


Three-State Output A12, IO28

    Input (glb03.O0, A12_Q)
    Enable (glb00.OE, _BUF_571)

    A12 = A12_Q
    A12.E = _BUF_571


Three-State Output A13, IO29

    Input (glb03.O1, A13_Q)
    Enable (glb00.OE, _BUF_571)

    A13 = A13_Q
    A13.E = _BUF_571


Three-State Output A14, IO30

    Input (glb03.O2, A14_Q)
    Enable (glb00.OE, _BUF_571)

    A14 = A14_Q
    A14.E = _BUF_571


Three-State Output A2, IO18

    Input (glb04.O2, A2_Q)
    Enable (glb00.OE, _BUF_571)

    A2 = A2_Q
    A2.E = _BUF_571


Three-State Output A3, IO19

    Input (glb04.O3, A3_Q)
    Enable (glb00.OE, _BUF_571)

    A3 = A3_Q
    A3.E = _BUF_571


Three-State Output A4, IO20

    Input (glb04.O0, A4_Q)
    Enable (glb00.OE, _BUF_571)

    A4 = A4_Q
    A4.E = _BUF_571


Three-State Output A5, IO21

    Input (glb02.O1, A5_Q)
    Enable (glb00.OE, _BUF_571)

    A5 = A5_Q
    A5.E = _BUF_571


Three-State Output A6, IO22

    Input (glb02.O2, A6_Q)
    Enable (glb00.OE, _BUF_571)

    A6 = A6_Q
    A6.E = _BUF_571


Three-State Output A7, IO23

    Input (glb02.O3, A7_Q)
    Enable (glb00.OE, _BUF_571)

    A7 = A7_Q
    A7.E = _BUF_571


Three-State Output A8, IO24

    Input (glb02.O0, A8_Q)
    Enable (glb00.OE, _BUF_571)

    A8 = A8_Q
    A8.E = _BUF_571


Three-State Output A9, IO25

    Input (glb05.O1, A9_Q)
    Enable (glb00.OE, _BUF_571)

    A9 = A9_Q
    A9.E = _BUF_571


Input AINC, IO4

    Output _PIN_AINC
        5 Fanout(s)
            glb07.I4, glb02.I0, glb04.I11, glb05.I11, glb03.I11


Output ATDBEN, IO10

    Input (glb01.O2, _BUF_572_part1)

    ATDBEN = !_BUF_572_part1


Output BUSENB, IO8

    Input (glb01.O0, _BUF_572_part2)

    BUSENB = _BUF_572_part2


Input CLR, IO6

    Output _PIN_CLR
        5 Fanout(s)
            glb07.I6, glb02.I2, glb04.I9, glb05.I9, glb03.I9


Output CS0, IO12

    Input (glb00.O0, _OR_476)

    CS0 = !_OR_476


Output CS1, IO13

    Input (glb00.O1, _OR_477)

    CS1 = !_OR_477


Output CS2, IO14

    Input (glb00.O2, _OR_478)

    CS2 = !_OR_478


Output CS3, IO15

    Input (glb00.O3, _OR_479)

    CS3 = !_OR_479


Input DIR, IO7

    Output _PIN_DIR
        3 Fanout(s)
            glb00.I7, glb01.I7, glb05.I8


Input EA15, IO0

    Output _PIN_EA15
        1 Fanout(s)
            glb00.I4


Input EA16, IO1

    Output _PIN_EA16
        1 Fanout(s)
            glb00.I5


Input EMCE, IO2

    Output _PIN_EMCE
        2 Fanout(s)
            glb00.I2, glb01.I2


Output EMDBEN, IO9

    Input (glb01.O1, _AND_480)

    EMDBEN = !_AND_480


Input EMOE, IO3

    Output _PIN_EMOE
        1 Fanout(s)
            glb05.I12


Output OE, IO31

    Input (glb05.O3, _AND_481)

    OE = !_AND_481


Output WE, IO11

    Input (glb01.O3, _AND_482)

    WE = !_AND_482


Input WR, IO5

    Output _PIN_WR
        1 Fanout(s)
            glb01.I5


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb00, A1                6,  4,  9          
            _OR_476                                      6,  1,  2,  1      
            _OR_477                                      6,  1,  2,  1      
            _OR_478                                      6,  1,  2,  1      
            _OR_479                                      6,  1,  2,  1      

        glb01, A2                3,  4,  3          
            _AND_480                                     2,  1,  1,  1      
            _AND_482                                     2,  1,  1,  1      
            _BUF_572_part1                               1,  1,  1,  1      
            _BUF_572_part2                               1,  1,  1,  1      

        glb02, A4               11,  4, 10          
            A5_Q                                         8,  3,  2,  1      
            A6_Q                                         9,  3,  2,  1      
            A7_Q                                        10,  3,  2,  1      
            A8_Q                                        11,  3,  2,  1      

        glb03, A7                9,  4, 12          
            A11_Q                                        6,  3,  4,  2      
            A12_Q                                        7,  3,  2,  2      
            A13_Q                                        8,  3,  2,  2      
            A14_Q                                        9,  3,  2,  2      

        glb04, A5                7,  4, 13          
            A1_Q                                         4,  4,  2,  1      
            A2_Q                                         5,  4,  3,  1      
            A3_Q                                         6,  4,  4,  1      
            A4_Q                                         7,  4,  2,  1      

        glb05, A6                8,  4,  9          
            A0_Q                                         3,  5,  1,  1      
            A10_Q                                        5,  4,  3,  2      
            A9_Q                                         4,  4,  2,  2      
            _AND_481                                     2,  1,  1,  1      

        glb06, A3                9,  1,  1          
            _AND_450                                     9,  3,  1,  1      

        glb07, A0               11,  2,  6          
            A15                                         10,  2,  2,  2      
            A16                                         11,  2,  2,  2      


Maximum-Level Trace

    GLB Level, Name, Ins    GLB Output Name

        2, glb03, 17            A14_Q               
        1, glb06                 _AND_450            

        2, glb03, 16            A13_Q               
        1, glb06                 _AND_450            

        2, glb03, 15            A12_Q               
        1, glb06                 _AND_450            

        2, glb03, 14            A11_Q               
        1, glb06                 _AND_450            

        2, glb05, 12            A9_Q                
        1, glb06                 _AND_450            

        2, glb05, 13            A10_Q               
        1, glb06                 _AND_450            

        2, glb07, 19            A16                 
        1, glb06                 _AND_450            

        2, glb07, 18            A15                 
        1, glb06                 _AND_450            


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        A8                      3                       Three-State Output
        A9                      4                       Three-State Output
        A10                     5                       Three-State Output
        A11                     6                       Three-State Output
        A12                     7                       Three-State Output
        A13                     8                       Three-State Output
        A14                     9                       Three-State Output
        OE                      10                      Output
        EA15                    15                      Input
        EA16                    16                      Input
        EMCE                    17                      Input
        EMOE                    18                      Input
        AINC                    19                      Input
        WR                      20                      Input
        CLR                     21                      Input
        DIR                     22                      Input
        BUSENB                  25                      Output
        EMDBEN                  26                      Output
        ATDBEN                  27                      Output
        WE                      28                      Output
        CS0                     29                      Output
        CS1                     30                      Output
        CS2                     31                      Output
        CS3                     32                      Output
        A0                      37                      Three-State Output
        A1                      38                      Three-State Output
        A2                      39                      Three-State Output
        A3                      40                      Three-State Output
        A4                      41                      Three-State Output
        A5                      42                      Three-State Output
        A6                      43                      Three-State Output
        A7                      44                      Three-State Output


Design process management completed successfully
