(is)pLSI Development System Plus Release 2.2.11, Nov 2 1995 16:37:23 Copyright (c) 1994, 1995 by Lattice Semiconductor Corporation All Rights Reserved Design Process Management Renaming existing rpt file to isp1m256.rp- Preprocessing design 'isp1m256'... PLA Reading and Translation Reading design 'isp1m256'... Checking design rules... Writing output files... PLA reading and translation completed successfully Processing design 'isp1m256'... Logical LAF Reading and Translation Reading file 'isp1m256.laf'... Checking design rules... Part is 'ispLSI2032-80LJ44' Writing output files... Logical LAF reading and translation completed successfully Synthesis and Partitioning Reading design 'isp1m256'... Optimizing logic... 33519 WARNING: Part 'ispLSI2032-80LJ44' does not support clock GLB; clock 'AINC' is changed to PT clock Partitioning logic into 16-input, 16-input with DIs, functions to minimize area... Extracting LXOR2 gates to minimize area... Packing functions into GLBs using 16 inputs and 4 outputs per GLB to minimize area... 34506 WARNING: OE net 'DIR' comes from an IOC or drives logic besides three-state buffers; buffer '_BUF_571' is inserted to generate PT OE Number of GLBs is 8 Number of product terms is 52 Number of feasible functions is 26 Maximum number of GLB levels is 2 Average number of inputs per GLB is 8.0 Average number of outputs per GLB is 3.2 Average number of product terms per GLB is 6.5 Synthesis and partitioning completed successfully Physical LAF Reading and Translation Reading design 'isp1m256'... Writing output files... Physical LAF reading and translation completed successfully Placement and Routing Reading design 'isp1m256'... Routing Writing output files... Placement and routing completed successfully Technology Remapping Reading design 'isp1m256'... Remapping... Writing output files... Technology remapping completed successfully Physical LAF Reading and Translation Reading design 'isp1m256'... Writing output files... Physical LAF reading and translation completed successfully Fusemap Generation Reading design 'isp1m256'... Writing output files... Fusemap generation completed successfully Test Vector Translation and Merging Vectors are added to file 'isp1m256.jed' Test vector translation and merging completed successfully Design process management completed successfully