(is)pLSI Development System Plus Release 2.2.11, Nov  2 1995 16:37:23


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
STRATEGY:                       AREA


Design Specification
--------------------

Design:                         isp1m
Part:                           ispLSI2032-80LJ44


Y1_AS_RESET:                    ON


Number of Critical Pins:        0
Number of Free Pins:            1
Number of Locked Pins:          29


Input Pins

    Pin Name                Pin Attribute

        AINC                    LOCK 19
        CLR                     LOCK 21
        DIR                     LOCK 22
        EA16                    LOCK 16
        EMCE                    LOCK 17
        EMOE                    LOCK 18
        WR                      LOCK 20


Output Pins

    Pin Name                Pin Attribute

        ATDBEN                  LOCK 27
        BUSENB                  LOCK 25
        CS                      LOCK 29
        EMDBEN                  LOCK 26
        OE                      LOCK 30
        RA16                    
        WE                      LOCK 28


Bidirectional Pins

    Pin Name                Pin Attribute

        A0                      LOCK 37
        A1                      LOCK 38
        A10                     LOCK 5
        A11                     LOCK 6
        A12                     LOCK 7
        A13                     LOCK 8
        A14                     LOCK 9
        A15                     LOCK 10
        A2                      LOCK 39
        A3                      LOCK 40
        A4                      LOCK 41
        A5                      LOCK 42
        A6                      LOCK 43
        A7                      LOCK 44
        A8                      LOCK 3
        A9                      LOCK 4


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 8
Number of I/Os:                 30
Number of Nets:                 47

Number of Free Inputs:          0
Number of Free Outputs:         1
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    7
Number of Locked DIs:           0
Number of Locked Outputs:       6
Number of Locked Three-States:  0
Number of Locked Bidi's:        16

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      0


GLB Utilization (Out of 8):	100%
I/O Utilization (Out of 34):	88%
Net Utilization (Out of 66):	71%


Nets with Fanout of  1:         11
Nets with Fanout of  2:         26
Nets with Fanout of  3:         8
Nets with Fanout of  5:         2

Average Fanout per Net:         2.06


GLBs with  1 Input(s):          1
GLBs with  4 Input(s):          1
GLBs with  9 Input(s):          1
GLBs with 10 Input(s):          1
GLBs with 11 Input(s):          1
GLBs with 12 Input(s):          1
GLBs with 13 Input(s):          1
GLBs with 14 Input(s):          1

Average Inputs per GLB:         9.25


GLBs with  0 Output(s):         1
GLBs with  1 Output(s):         1
GLBs with  3 Output(s):         1
GLBs with  4 Output(s):         5

Average Outputs per GLB:        3.00


Output Enable Nets

    Net Name                Net Fanout

        _BUF_518                16


Post-Route Design Implementation
--------------------------------

Number of GLBs:			8
Number of IOCs:			30
Number of DIs:			0
Number of GLB Levels:		2


GLB glb00, A1

    12 Input(s)
        (A0.O, A0_PIN, I0), (A1.O, A1_PIN, I1), (A2.O, A2_PIN, I2), 
        (A3.O, A3_PIN, I3), (A4.O, A4_PIN, I4), (A5.O, A5_PIN, I5), 
        (A6.O, A6_PIN, I13), (A7.O, A7_PIN, I7), (A8.O, A8_PIN, I8), 
        (DIR.O, _PIN_DIR, I12), (EMCE.O, _PIN_EMCE, I6), (WR.O, 
        _PIN_WR, I14)
    4 Output(s)
        (_AND_455, O3), (_AND_453, O1), (_AND_435, O2), (CS_PIN, O0)
    4 Product Term(s)

    Output _AND_455

        2 Input(s)
            _PIN_DIR, _PIN_WR
        1 Fanout(s)
            WE.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_455 = _PIN_DIR & _PIN_WR

    Output _AND_453

        2 Input(s)
            _PIN_DIR, _PIN_EMCE
        1 Fanout(s)
            EMDBEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_453 = !_PIN_DIR & !_PIN_EMCE

    Output _AND_435

        9 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_PIN, A5_PIN, A6_PIN,
            A7_PIN, A8_PIN
        3 Fanout(s)
            glb06.I13, glb05.I2, glb03.I2
        1 Product Term(s)
        1 GLB Level(s)

        _AND_435 = A0_PIN & A1_PIN & A2_PIN & A3_PIN & A4_PIN & A5_PIN
            & A6_PIN & A7_PIN & A8_PIN

    Output CS_PIN

        2 Input(s)
            _PIN_DIR, _PIN_EMCE
        1 Fanout(s)
            CS.IR
        1 Product Term(s)
        1 GLB Level(s)

        CS_PIN = !_PIN_DIR & _PIN_EMCE


GLB glb01, A2

    4 Input(s)
        (glb06.O0, A16, I8), (DIR.O, _PIN_DIR, I7), (EA16.O, 
        _PIN_EA16, I1), (EMOE.O, _PIN_EMOE, I3)
    4 Output(s)
        (_BUF_519_part2, O0), (_AND_454, O1), (RA16_PIN, O3), 
        (_BUF_519_part1, O2)
    4 Product Term(s)

    Output _BUF_519_part2

        1 Input(s)
            _PIN_DIR
        1 Fanout(s)
            BUSENB.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_519_part2 = (_PIN_DIR)

    Output _AND_454

        2 Input(s)
            _PIN_DIR, _PIN_EMOE
        1 Fanout(s)
            OE.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_454 = !_PIN_DIR & !_PIN_EMOE

    Output RA16_PIN

        3 Input(s)
            A16, _PIN_DIR, _PIN_EA16
        1 Fanout(s)
            RA16.IR
        2 Product Term(s)
        1 GLB Level(s)

        RA16_PIN = (!_PIN_DIR & _PIN_EA16
            # A16 & _PIN_DIR)

    Output _BUF_519_part1

        1 Input(s)
            _PIN_DIR
        1 Fanout(s)
            ATDBEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_519_part1 = (_PIN_DIR)


GLB glb02, A7

    14 Input(s)
        (A0.O, A0_PIN, I15), (A1.O, A1_PIN, I14), (A2.O, A2_PIN, I13), 
        (A3.O, A3_PIN, I12), (A4.O, A4_PIN, I11), (glb02.O1, 
        A5_Q, I6), (A5.O, A5_PIN, I10), (glb02.O2, A6_Q, I17), (A6.O, 
        A6_PIN, I9), (glb02.O3, A7_Q, I4), (A7.O, A7_PIN, I8), 
        (glb02.O0, A8_Q, I16), (AINC.O, _PIN_AINC, I0), (CLR.O, 
        _PIN_CLR, I2)
    4 Output(s)
        (A8_Q, O0), (A7_Q, O3), (A6_Q, O2), (A5_Q, O1)
    10 Product Term(s)

    Output A8_Q

        11 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_PIN, A5_PIN, A6_PIN,
            A7_PIN, A8_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb02.I16, A8.IR
        2 Product Term(s)
        1 GLB Level(s)

        A8_Q.D = (A8_Q)
            $ A0_PIN & A1_PIN & A2_PIN & A3_PIN & A4_PIN & A5_PIN
            & A6_PIN & A7_PIN
        A8_Q.C = _PIN_AINC
        A8_Q.R = !_PIN_CLR

    Output A7_Q

        10 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_PIN, A5_PIN, A6_PIN, A7_Q,
            _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb02.I4, A7.IR
        2 Product Term(s)
        1 GLB Level(s)

        A7_Q.D = (A7_Q)
            $ A0_PIN & A1_PIN & A2_PIN & A3_PIN & A4_PIN & A5_PIN
            & A6_PIN
        A7_Q.C = _PIN_AINC
        A7_Q.R = !_PIN_CLR

    Output A6_Q

        9 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_PIN, A5_PIN, A6_Q,
            _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb02.I17, A6.IR
        2 Product Term(s)
        1 GLB Level(s)

        A6_Q.D = (A6_Q)
            $ A0_PIN & A1_PIN & A2_PIN & A3_PIN & A4_PIN & A5_PIN
        A6_Q.C = _PIN_AINC
        A6_Q.R = !_PIN_CLR

    Output A5_Q

        8 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_PIN, A5_Q, _PIN_AINC,
            _PIN_CLR
        2 Fanout(s)
            glb02.I6, A5.IR
        2 Product Term(s)
        1 GLB Level(s)

        A5_Q.D = (A5_Q)
            $ A0_PIN & A1_PIN & A2_PIN & A3_PIN & A4_PIN
        A5_Q.C = _PIN_AINC
        A5_Q.R = !_PIN_CLR


GLB glb03, A6

    13 Input(s)
        (A10.O, A10_PIN, I14), (A11.O, A11_PIN, I15), (glb03.O0, 
        A12_Q, I16), (A12.O, A12_PIN, I7), (glb03.O1, A13_Q, I17), 
        (A13.O, A13_PIN, I6), (glb03.O2, A14_Q, I5), (A14.O, 
        A14_PIN, I1), (glb03.O3, A15_Q, I4), (A9.O, A9_PIN, I13), 
        (AINC.O, _PIN_AINC, I11), (CLR.O, _PIN_CLR, I9), (glb00.O2, 
        _AND_435, I2)
    4 Output(s)
        (A15_Q, O3), (A14_Q, O2), (A13_Q, O1), (A12_Q, O0)
    10 Product Term(s)

    Output A15_Q

        10 Input(s)
            A10_PIN, A11_PIN, A12_PIN, A13_PIN, A14_PIN, A15_Q, A9_PIN,
            _PIN_AINC, _PIN_CLR, _AND_435
        2 Fanout(s)
            glb03.I4, A15.IR
        2 Product Term(s)
        2 GLB Level(s)

        A15_Q.D = (A15_Q)
            $ A10_PIN & A11_PIN & A12_PIN & A13_PIN & A14_PIN & A9_PIN
            & _AND_435
        A15_Q.C = _PIN_AINC
        A15_Q.R = !_PIN_CLR

    Output A14_Q

        9 Input(s)
            A10_PIN, A11_PIN, A12_PIN, A13_PIN, A14_Q, A9_PIN, _PIN_AINC,
            _PIN_CLR, _AND_435
        2 Fanout(s)
            glb03.I5, A14.IR
        2 Product Term(s)
        2 GLB Level(s)

        A14_Q.D = (A14_Q)
            $ A10_PIN & A11_PIN & A12_PIN & A13_PIN & A9_PIN & _AND_435
        A14_Q.C = _PIN_AINC
        A14_Q.R = !_PIN_CLR

    Output A13_Q

        8 Input(s)
            A10_PIN, A11_PIN, A12_PIN, A13_Q, A9_PIN, _PIN_AINC,
            _PIN_CLR, _AND_435
        2 Fanout(s)
            glb03.I17, A13.IR
        2 Product Term(s)
        2 GLB Level(s)

        A13_Q.D = (A13_Q)
            $ A10_PIN & A11_PIN & A12_PIN & A9_PIN & _AND_435
        A13_Q.C = _PIN_AINC
        A13_Q.R = !_PIN_CLR

    Output A12_Q

        7 Input(s)
            A10_PIN, A11_PIN, A12_Q, A9_PIN, _PIN_AINC, _PIN_CLR,
            _AND_435
        2 Fanout(s)
            glb03.I16, A12.IR
        2 Product Term(s)
        2 GLB Level(s)

        A12_Q.D = (A12_Q)
            $ A10_PIN & A11_PIN & A9_PIN & _AND_435
        A12_Q.C = _PIN_AINC
        A12_Q.R = !_PIN_CLR


GLB glb04, A5

    10 Input(s)
        (A0.O, A0_PIN, I15), (glb04.O1, A1_Q, I17), (A1.O, 
        A1_PIN, I14), (glb04.O2, A2_Q, I9), (A2.O, A2_PIN, I13), 
        (glb04.O3, A3_Q, I8), (A3.O, A3_PIN, I12), (glb04.O0, 
        A4_Q, I16), (AINC.O, _PIN_AINC, I11), (CLR.O, _PIN_CLR, I2)
    4 Output(s)
        (A4_Q, O0), (A3_Q, O3), (A2_Q, O2), (A1_Q, O1)
    13 Product Term(s)

    Output A4_Q

        7 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_PIN, A4_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb04.I16, A4.IR
        2 Product Term(s)
        1 GLB Level(s)

        A4_Q.D = (A4_Q)
            $ A0_PIN & A1_PIN & A2_PIN & A3_PIN
        A4_Q.C = _PIN_AINC
        A4_Q.R = !_PIN_CLR

    Output A3_Q

        6 Input(s)
            A0_PIN, A1_PIN, A2_PIN, A3_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb04.I8, A3.IR
        4 Product Term(s)
        1 GLB Level(s)

        A3_Q.D = (A3_Q & !A0_PIN
            # A3_Q & !A1_PIN
            # A3_Q & !A2_PIN
            # A0_PIN & A1_PIN & A2_PIN & !A3_Q)
        A3_Q.C = _PIN_AINC
        A3_Q.R = !_PIN_CLR

    Output A2_Q

        5 Input(s)
            A0_PIN, A1_PIN, A2_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb04.I9, A2.IR
        3 Product Term(s)
        1 GLB Level(s)

        A2_Q.D = (A2_Q & !A0_PIN
            # A2_Q & !A1_PIN
            # A0_PIN & A1_PIN & !A2_Q)
        A2_Q.C = _PIN_AINC
        A2_Q.R = !_PIN_CLR

    Output A1_Q

        4 Input(s)
            A0_PIN, A1_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb04.I17, A1.IR
        2 Product Term(s)
        1 GLB Level(s)

        A1_Q.D = (A1_Q & !A0_PIN
            # A0_PIN & !A1_Q)
        A1_Q.C = _PIN_AINC
        A1_Q.R = !_PIN_CLR


GLB glb05, A4

    9 Input(s)
        (glb05.O0, A0_Q, I16), (glb05.O2, A10_Q, I13), (A10.O, 
        A10_PIN, I14), (glb05.O3, A11_Q, I12), (glb05.O1, A9_Q, I17), 
        (A9.O, A9_PIN, I6), (AINC.O, _PIN_AINC, I11), (CLR.O, 
        _PIN_CLR, I9), (glb00.O2, _AND_435, I2)
    4 Output(s)
        (A9_Q, O1), (A11_Q, O3), (A10_Q, O2), (A0_Q, O0)
    12 Product Term(s)

    Output A9_Q

        4 Input(s)
            A9_Q, _PIN_AINC, _PIN_CLR, _AND_435
        2 Fanout(s)
            glb05.I17, A9.IR
        2 Product Term(s)
        2 GLB Level(s)

        A9_Q.D = (_AND_435 & !A9_Q
            # A9_Q & !_AND_435)
        A9_Q.C = _PIN_AINC
        A9_Q.R = !_PIN_CLR

    Output A11_Q

        6 Input(s)
            A10_PIN, A11_Q, A9_PIN, _PIN_AINC, _PIN_CLR, _AND_435
        2 Fanout(s)
            glb05.I12, A11.IR
        4 Product Term(s)
        2 GLB Level(s)

        A11_Q.D = (A11_Q & !A9_PIN
            # A11_Q & !A10_PIN
            # A11_Q & !_AND_435
            # A10_PIN & A9_PIN & _AND_435 & !A11_Q)
        A11_Q.C = _PIN_AINC
        A11_Q.R = !_PIN_CLR

    Output A10_Q

        5 Input(s)
            A10_Q, A9_PIN, _PIN_AINC, _PIN_CLR, _AND_435
        2 Fanout(s)
            glb05.I13, A10.IR
        3 Product Term(s)
        2 GLB Level(s)

        A10_Q.D = (A10_Q & !A9_PIN
            # A10_Q & !_AND_435
            # A9_PIN & _AND_435 & !A10_Q)
        A10_Q.C = _PIN_AINC
        A10_Q.R = !_PIN_CLR

    Output A0_Q

        3 Input(s)
            A0_Q, _PIN_AINC, _PIN_CLR
        2 Fanout(s)
            glb05.I16, A0.IR
        1 Product Term(s)
        1 GLB Level(s)

        A0_Q.D = !A0_Q
        A0_Q.C = _PIN_AINC
        A0_Q.R = !_PIN_CLR


GLB glb06, A3

    11 Input(s)
        (A10.O, A10_PIN, I1), (A11.O, A11_PIN, I0), (A12.O, 
        A12_PIN, I8), (A13.O, A13_PIN, I9), (A14.O, A14_PIN, I10), 
        (A15.O, A15_PIN, I11), (glb06.O0, A16, I16), (A9.O, 
        A9_PIN, I2), (AINC.O, _PIN_AINC, I4), (CLR.O, _PIN_CLR, I6), 
        (glb00.O2, _AND_435, I13)
    1 Output(s)
        (A16, O0)
    4 Product Term(s)

    Output A16

        11 Input(s)
            A10_PIN, A11_PIN, A12_PIN, A13_PIN, A14_PIN, A15_PIN, A16,
            A9_PIN, _PIN_AINC, _PIN_CLR, _AND_435
        2 Fanout(s)
            glb01.I8, glb06.I16
        2 Product Term(s)
        2 GLB Level(s)

        A16.D = (A16)
            $ A10_PIN & A11_PIN & A12_PIN & A13_PIN & A14_PIN & A15_PIN
            & A9_PIN & _AND_435
        A16.C = _PIN_AINC
        A16.R = !_PIN_CLR


GLB glb07, A0

    1 Input(s)
        (DIR.O, _PIN_DIR, I7)
    0 Output(s)
    1 Enable Output
        _BUF_518
    1 Product Term(s)

    Enable Output _BUF_518

        1 Input(s)
            _PIN_DIR
        16 Fanout(s)
            A9.OE0, A8.OE0, A7.OE0, A6.OE0, A5.OE0, A4.OE0, A3.OE0,
            A2.OE0, A1.OE0, A15.OE0, A14.OE0, A13.OE0, A12.OE0, A11.OE0,
            A10.OE0, A0.OE0
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_518 = _PIN_DIR


Bidirectional A0, IO16

    Input (glb05.O0, A0_Q)
    Output A0_PIN
        3 Fanout(s)
            glb00.I0, glb04.I15, glb02.I15
    Enable (glb07.OE, _BUF_518)

    A0 = A0_Q
    A0.E = _BUF_518


Bidirectional A1, IO17

    Input (glb04.O1, A1_Q)
    Output A1_PIN
        3 Fanout(s)
            glb00.I1, glb04.I14, glb02.I14
    Enable (glb07.OE, _BUF_518)

    A1 = A1_Q
    A1.E = _BUF_518


Bidirectional A10, IO26

    Input (glb05.O2, A10_Q)
    Output A10_PIN
        3 Fanout(s)
            glb06.I1, glb05.I14, glb03.I14
    Enable (glb07.OE, _BUF_518)

    A10 = A10_Q
    A10.E = _BUF_518


Bidirectional A11, IO27

    Input (glb05.O3, A11_Q)
    Output A11_PIN
        2 Fanout(s)
            glb06.I0, glb03.I15
    Enable (glb07.OE, _BUF_518)

    A11 = A11_Q
    A11.E = _BUF_518


Bidirectional A12, IO28

    Input (glb03.O0, A12_Q)
    Output A12_PIN
        2 Fanout(s)
            glb06.I8, glb03.I7
    Enable (glb07.OE, _BUF_518)

    A12 = A12_Q
    A12.E = _BUF_518


Bidirectional A13, IO29

    Input (glb03.O1, A13_Q)
    Output A13_PIN
        2 Fanout(s)
            glb06.I9, glb03.I6
    Enable (glb07.OE, _BUF_518)

    A13 = A13_Q
    A13.E = _BUF_518


Bidirectional A14, IO30

    Input (glb03.O2, A14_Q)
    Output A14_PIN
        2 Fanout(s)
            glb06.I10, glb03.I1
    Enable (glb07.OE, _BUF_518)

    A14 = A14_Q
    A14.E = _BUF_518


Bidirectional A15, IO31

    Input (glb03.O3, A15_Q)
    Output A15_PIN
        1 Fanout(s)
            glb06.I11
    Enable (glb07.OE, _BUF_518)

    A15 = A15_Q
    A15.E = _BUF_518


Bidirectional A2, IO18

    Input (glb04.O2, A2_Q)
    Output A2_PIN
        3 Fanout(s)
            glb00.I2, glb04.I13, glb02.I13
    Enable (glb07.OE, _BUF_518)

    A2 = A2_Q
    A2.E = _BUF_518


Bidirectional A3, IO19

    Input (glb04.O3, A3_Q)
    Output A3_PIN
        3 Fanout(s)
            glb00.I3, glb04.I12, glb02.I12
    Enable (glb07.OE, _BUF_518)

    A3 = A3_Q
    A3.E = _BUF_518


Bidirectional A4, IO20

    Input (glb04.O0, A4_Q)
    Output A4_PIN
        2 Fanout(s)
            glb00.I4, glb02.I11
    Enable (glb07.OE, _BUF_518)

    A4 = A4_Q
    A4.E = _BUF_518


Bidirectional A5, IO21

    Input (glb02.O1, A5_Q)
    Output A5_PIN
        2 Fanout(s)
            glb00.I5, glb02.I10
    Enable (glb07.OE, _BUF_518)

    A5 = A5_Q
    A5.E = _BUF_518


Bidirectional A6, IO22

    Input (glb02.O2, A6_Q)
    Output A6_PIN
        2 Fanout(s)
            glb00.I13, glb02.I9
    Enable (glb07.OE, _BUF_518)

    A6 = A6_Q
    A6.E = _BUF_518


Bidirectional A7, IO23

    Input (glb02.O3, A7_Q)
    Output A7_PIN
        2 Fanout(s)
            glb00.I7, glb02.I8
    Enable (glb07.OE, _BUF_518)

    A7 = A7_Q
    A7.E = _BUF_518


Bidirectional A8, IO24

    Input (glb02.O0, A8_Q)
    Output A8_PIN
        1 Fanout(s)
            glb00.I8
    Enable (glb07.OE, _BUF_518)

    A8 = A8_Q
    A8.E = _BUF_518


Bidirectional A9, IO25

    Input (glb05.O1, A9_Q)
    Output A9_PIN
        3 Fanout(s)
            glb06.I2, glb05.I6, glb03.I13
    Enable (glb07.OE, _BUF_518)

    A9 = A9_Q
    A9.E = _BUF_518


Input AINC, IO4

    Output _PIN_AINC
        5 Fanout(s)
            glb06.I4, glb05.I11, glb04.I11, glb03.I11, glb02.I0


Output ATDBEN, IO10

    Input (glb01.O2, _BUF_519_part1)

    ATDBEN = !_BUF_519_part1


Output BUSENB, IO8

    Input (glb01.O0, _BUF_519_part2)

    BUSENB = _BUF_519_part2


Input CLR, IO6

    Output _PIN_CLR
        5 Fanout(s)
            glb06.I6, glb05.I9, glb04.I2, glb03.I9, glb02.I2


Output CS, IO12

    Input (glb00.O0, CS_PIN)

    CS = CS_PIN


Input DIR, IO7

    Output _PIN_DIR
        3 Fanout(s)
            glb07.I7, glb00.I12, glb01.I7


Input EA16, IO1

    Output _PIN_EA16
        1 Fanout(s)
            glb01.I1


Input EMCE, IO2

    Output _PIN_EMCE
        1 Fanout(s)
            glb00.I6


Output EMDBEN, IO9

    Input (glb00.O1, _AND_453)

    EMDBEN = !_AND_453


Input EMOE, IO3

    Output _PIN_EMOE
        1 Fanout(s)
            glb01.I3


Output OE, IO13

    Input (glb01.O1, _AND_454)

    OE = !_AND_454


Output RA16, IO15

    Input (glb01.O3, RA16_PIN)

    RA16 = RA16_PIN


Output WE, IO11

    Input (glb00.O3, _AND_455)

    WE = !_AND_455


Input WR, IO5

    Output _PIN_WR
        1 Fanout(s)
            glb00.I14


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb00, A1               12,  4,  4          
            CS_PIN                                       2,  1,  1,  1      
            _AND_435                                     9,  3,  1,  1      
            _AND_453                                     2,  1,  1,  1      
            _AND_455                                     2,  1,  1,  1      

        glb01, A2                4,  4,  4          
            RA16_PIN                                     3,  1,  2,  1      
            _AND_454                                     2,  1,  1,  1      
            _BUF_519_part1                               1,  1,  1,  1      
            _BUF_519_part2                               1,  1,  1,  1      

        glb02, A7               14,  4, 10          
            A5_Q                                         8,  2,  2,  1      
            A6_Q                                         9,  2,  2,  1      
            A7_Q                                        10,  2,  2,  1      
            A8_Q                                        11,  2,  2,  1      

        glb03, A6               13,  4, 10          
            A12_Q                                        7,  2,  2,  2      
            A13_Q                                        8,  2,  2,  2      
            A14_Q                                        9,  2,  2,  2      
            A15_Q                                       10,  2,  2,  2      

        glb04, A5               10,  4, 13          
            A1_Q                                         4,  2,  2,  1      
            A2_Q                                         5,  2,  3,  1      
            A3_Q                                         6,  2,  4,  1      
            A4_Q                                         7,  2,  2,  1      

        glb05, A4                9,  4, 12          
            A0_Q                                         3,  2,  1,  1      
            A10_Q                                        5,  2,  3,  2      
            A11_Q                                        6,  2,  4,  2      
            A9_Q                                         4,  2,  2,  2      

        glb06, A3               11,  1,  4          
            A16                                         11,  2,  2,  2      

        glb07, A0                1,  0,  1          


Maximum-Level Trace

    GLB Level, Name, Ins    GLB Output Name

        2, glb03, 18            A15_Q               
        1, glb00                 _AND_435            

        2, glb03, 17            A14_Q               
        1, glb00                 _AND_435            

        2, glb03, 16            A13_Q               
        1, glb00                 _AND_435            

        2, glb03, 15            A12_Q               
        1, glb00                 _AND_435            

        2, glb05, 12            A9_Q                
        1, glb00                 _AND_435            

        2, glb05, 14            A11_Q               
        1, glb00                 _AND_435            

        2, glb05, 13            A10_Q               
        1, glb00                 _AND_435            

        2, glb06, 19            A16                 
        1, glb00                 _AND_435            


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        A8                      3                       Bidirectional
        A9                      4                       Bidirectional
        A10                     5                       Bidirectional
        A11                     6                       Bidirectional
        A12                     7                       Bidirectional
        A13                     8                       Bidirectional
        A14                     9                       Bidirectional
        A15                     10                      Bidirectional
        EA16                    16                      Input
        EMCE                    17                      Input
        EMOE                    18                      Input
        AINC                    19                      Input
        WR                      20                      Input
        CLR                     21                      Input
        DIR                     22                      Input
        BUSENB                  25                      Output
        EMDBEN                  26                      Output
        ATDBEN                  27                      Output
        WE                      28                      Output
        CS                      29                      Output
        OE                      30                      Output
        RA16                    32                      Output
        A0                      37                      Bidirectional
        A1                      38                      Bidirectional
        A2                      39                      Bidirectional
        A3                      40                      Bidirectional
        A4                      41                      Bidirectional
        A5                      42                      Bidirectional
        A6                      43                      Bidirectional
        A7                      44                      Bidirectional


Design process management completed successfully
